348 lines
7.5 KiB
C
348 lines
7.5 KiB
C
/*
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* Copyright (c) 2016-2017 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "hclge_main.h"
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#include "hclge_tm.h"
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#include "hnae3.h"
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#define BW_PERCENT 100
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static int hclge_ieee_ets_to_tm_info(struct hclge_dev *hdev,
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struct ieee_ets *ets)
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{
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u8 i;
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for (i = 0; i < HNAE3_MAX_TC; i++) {
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switch (ets->tc_tsa[i]) {
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case IEEE_8021QAZ_TSA_STRICT:
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hdev->tm_info.tc_info[i].tc_sch_mode =
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HCLGE_SCH_MODE_SP;
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hdev->tm_info.pg_info[0].tc_dwrr[i] = 0;
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break;
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case IEEE_8021QAZ_TSA_ETS:
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hdev->tm_info.tc_info[i].tc_sch_mode =
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HCLGE_SCH_MODE_DWRR;
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hdev->tm_info.pg_info[0].tc_dwrr[i] =
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ets->tc_tx_bw[i];
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break;
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default:
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/* Hardware only supports SP (strict priority)
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* or ETS (enhanced transmission selection)
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* algorithms, if we receive some other value
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* from dcbnl, then throw an error.
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*/
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return -EINVAL;
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}
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}
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return hclge_tm_prio_tc_info_update(hdev, ets->prio_tc);
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}
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static void hclge_tm_info_to_ieee_ets(struct hclge_dev *hdev,
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struct ieee_ets *ets)
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{
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u32 i;
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memset(ets, 0, sizeof(*ets));
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ets->willing = 1;
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ets->ets_cap = hdev->tc_max;
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for (i = 0; i < HNAE3_MAX_TC; i++) {
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ets->prio_tc[i] = hdev->tm_info.prio_tc[i];
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ets->tc_tx_bw[i] = hdev->tm_info.pg_info[0].tc_dwrr[i];
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if (hdev->tm_info.tc_info[i].tc_sch_mode ==
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HCLGE_SCH_MODE_SP)
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ets->tc_tsa[i] = IEEE_8021QAZ_TSA_STRICT;
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else
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ets->tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
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}
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}
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/* IEEE std */
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static int hclge_ieee_getets(struct hnae3_handle *h, struct ieee_ets *ets)
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{
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struct hclge_vport *vport = hclge_get_vport(h);
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struct hclge_dev *hdev = vport->back;
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hclge_tm_info_to_ieee_ets(hdev, ets);
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return 0;
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}
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static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets,
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u8 *tc, bool *changed)
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{
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u32 total_ets_bw = 0;
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u8 max_tc = 0;
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u8 i;
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for (i = 0; i < HNAE3_MAX_TC; i++) {
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if (ets->prio_tc[i] >= hdev->tc_max ||
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i >= hdev->tc_max)
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return -EINVAL;
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if (ets->prio_tc[i] != hdev->tm_info.prio_tc[i])
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*changed = true;
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if (ets->prio_tc[i] > max_tc)
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max_tc = ets->prio_tc[i];
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switch (ets->tc_tsa[i]) {
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case IEEE_8021QAZ_TSA_STRICT:
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if (hdev->tm_info.tc_info[i].tc_sch_mode !=
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HCLGE_SCH_MODE_SP)
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*changed = true;
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break;
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case IEEE_8021QAZ_TSA_ETS:
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if (hdev->tm_info.tc_info[i].tc_sch_mode !=
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HCLGE_SCH_MODE_DWRR)
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*changed = true;
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total_ets_bw += ets->tc_tx_bw[i];
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break;
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default:
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return -EINVAL;
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}
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}
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if (total_ets_bw != BW_PERCENT)
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return -EINVAL;
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*tc = max_tc + 1;
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if (*tc != hdev->tm_info.num_tc)
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*changed = true;
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return 0;
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}
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static int hclge_map_update(struct hnae3_handle *h)
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{
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struct hclge_vport *vport = hclge_get_vport(h);
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struct hclge_dev *hdev = vport->back;
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int ret;
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ret = hclge_tm_map_cfg(hdev);
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if (ret)
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return ret;
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ret = hclge_tm_schd_mode_hw(hdev);
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if (ret)
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return ret;
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ret = hclge_pause_setup_hw(hdev);
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if (ret)
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return ret;
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ret = hclge_buffer_alloc(hdev);
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if (ret)
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return ret;
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return hclge_rss_init_hw(hdev);
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}
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static int hclge_client_setup_tc(struct hclge_dev *hdev)
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{
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struct hclge_vport *vport = hdev->vport;
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struct hnae3_client *client;
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struct hnae3_handle *handle;
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int ret;
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u32 i;
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for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
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handle = &vport[i].nic;
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client = handle->client;
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if (!client || !client->ops || !client->ops->setup_tc)
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continue;
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ret = client->ops->setup_tc(handle, hdev->tm_info.num_tc);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int hclge_ieee_setets(struct hnae3_handle *h, struct ieee_ets *ets)
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{
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struct hclge_vport *vport = hclge_get_vport(h);
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struct hclge_dev *hdev = vport->back;
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bool map_changed = false;
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u8 num_tc = 0;
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int ret;
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if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
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hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
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return -EINVAL;
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ret = hclge_ets_validate(hdev, ets, &num_tc, &map_changed);
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if (ret)
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return ret;
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hclge_tm_schd_info_update(hdev, num_tc);
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ret = hclge_ieee_ets_to_tm_info(hdev, ets);
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if (ret)
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return ret;
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if (map_changed) {
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ret = hclge_client_setup_tc(hdev);
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if (ret)
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return ret;
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}
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return hclge_tm_dwrr_cfg(hdev);
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}
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static int hclge_ieee_getpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
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{
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struct hclge_vport *vport = hclge_get_vport(h);
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struct hclge_dev *hdev = vport->back;
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u8 i, j, pfc_map, *prio_tc;
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memset(pfc, 0, sizeof(*pfc));
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pfc->pfc_cap = hdev->pfc_max;
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prio_tc = hdev->tm_info.prio_tc;
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pfc_map = hdev->tm_info.hw_pfc_map;
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/* Pfc setting is based on TC */
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for (i = 0; i < hdev->tm_info.num_tc; i++) {
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for (j = 0; j < HNAE3_MAX_USER_PRIO; j++) {
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if ((prio_tc[j] == i) && (pfc_map & BIT(i)))
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pfc->pfc_en |= BIT(j);
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}
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}
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return 0;
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}
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static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
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{
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struct hclge_vport *vport = hclge_get_vport(h);
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struct hclge_dev *hdev = vport->back;
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u8 i, j, pfc_map, *prio_tc;
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if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
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hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
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return -EINVAL;
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prio_tc = hdev->tm_info.prio_tc;
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pfc_map = 0;
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for (i = 0; i < hdev->tm_info.num_tc; i++) {
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for (j = 0; j < HNAE3_MAX_USER_PRIO; j++) {
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if ((prio_tc[j] == i) && (pfc->pfc_en & BIT(j))) {
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pfc_map |= BIT(i);
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break;
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}
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}
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}
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if (pfc_map == hdev->tm_info.hw_pfc_map)
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return 0;
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hdev->tm_info.hw_pfc_map = pfc_map;
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return hclge_pause_setup_hw(hdev);
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}
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/* DCBX configuration */
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static u8 hclge_getdcbx(struct hnae3_handle *h)
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{
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struct hclge_vport *vport = hclge_get_vport(h);
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struct hclge_dev *hdev = vport->back;
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if (hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
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return 0;
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return hdev->dcbx_cap;
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}
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static u8 hclge_setdcbx(struct hnae3_handle *h, u8 mode)
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{
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struct hclge_vport *vport = hclge_get_vport(h);
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struct hclge_dev *hdev = vport->back;
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/* No support for LLD_MANAGED modes or CEE */
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if ((mode & DCB_CAP_DCBX_LLD_MANAGED) ||
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(mode & DCB_CAP_DCBX_VER_CEE) ||
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!(mode & DCB_CAP_DCBX_HOST))
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return 1;
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hdev->dcbx_cap = mode;
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return 0;
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}
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/* Set up TC for hardware offloaded mqprio in channel mode */
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static int hclge_setup_tc(struct hnae3_handle *h, u8 tc, u8 *prio_tc)
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{
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struct hclge_vport *vport = hclge_get_vport(h);
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struct hclge_dev *hdev = vport->back;
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int ret;
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if (hdev->flag & HCLGE_FLAG_DCB_ENABLE)
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return -EINVAL;
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if (tc > hdev->tc_max) {
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dev_err(&hdev->pdev->dev,
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"setup tc failed, tc(%u) > tc_max(%u)\n",
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tc, hdev->tc_max);
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return -EINVAL;
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}
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hclge_tm_schd_info_update(hdev, tc);
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ret = hclge_tm_prio_tc_info_update(hdev, prio_tc);
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if (ret)
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return ret;
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ret = hclge_tm_init_hw(hdev);
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if (ret)
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return ret;
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hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
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if (tc > 1)
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hdev->flag |= HCLGE_FLAG_MQPRIO_ENABLE;
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else
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hdev->flag &= ~HCLGE_FLAG_MQPRIO_ENABLE;
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return 0;
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}
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static const struct hnae3_dcb_ops hns3_dcb_ops = {
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.ieee_getets = hclge_ieee_getets,
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.ieee_setets = hclge_ieee_setets,
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.ieee_getpfc = hclge_ieee_getpfc,
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.ieee_setpfc = hclge_ieee_setpfc,
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.getdcbx = hclge_getdcbx,
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.setdcbx = hclge_setdcbx,
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.map_update = hclge_map_update,
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.setup_tc = hclge_setup_tc,
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};
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void hclge_dcb_ops_set(struct hclge_dev *hdev)
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{
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struct hclge_vport *vport = hdev->vport;
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struct hnae3_knic_private_info *kinfo;
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/* Hdev does not support DCB or vport is
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* not a pf, then dcb_ops is not set.
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*/
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if (!hnae3_dev_dcb_supported(hdev) ||
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vport->vport_id != 0)
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return;
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kinfo = &vport->nic.kinfo;
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kinfo->dcb_ops = &hns3_dcb_ops;
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hdev->dcbx_cap = DCB_CAP_DCBX_VER_IEEE | DCB_CAP_DCBX_HOST;
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}
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