232 lines
7.5 KiB
C
232 lines
7.5 KiB
C
/*
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* Copyright 2015 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs <bskeggs@redhat.com>
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*/
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#include "gf100.h"
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#include "ctxgf100.h"
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#include <subdev/secboot.h>
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#include <nvif/class.h>
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/*******************************************************************************
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* PGRAPH engine/subdev functions
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******************************************************************************/
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int
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gm200_gr_rops(struct gf100_gr *gr)
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{
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return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c);
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}
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void
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gm200_gr_init_gpc_mmu(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf0001fff);
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nvkm_wr32(device, 0x418890, 0x00000000);
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nvkm_wr32(device, 0x418894, 0x00000000);
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nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
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nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
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nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
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}
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static void
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gm200_gr_init_rop_active_fbps(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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const u32 fbp_count = nvkm_rd32(device, 0x12006c);
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nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
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nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
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}
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int
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gm200_gr_init(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
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u32 data[TPC_MAX / 8] = {};
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u8 tpcnr[GPC_MAX];
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int gpc, tpc, rop;
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int i;
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gr->func->init_gpc_mmu(gr);
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gf100_gr_mmio(gr, gr->fuc_sw_nonctx);
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gm107_gr_init_bios(gr);
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nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001);
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memset(data, 0x00, sizeof(data));
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memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
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for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
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do {
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gpc = (gpc + 1) % gr->gpc_nr;
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} while (!tpcnr[gpc]);
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tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
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data[i / 8] |= tpc << ((i % 8) * 4);
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}
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nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
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nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
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nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
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nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
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for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
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nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
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gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
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nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
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gr->tpc_total);
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nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
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}
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nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
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nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
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nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804));
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gr->func->init_rop_active_fbps(gr);
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nvkm_wr32(device, 0x400500, 0x00010001);
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nvkm_wr32(device, 0x400100, 0xffffffff);
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nvkm_wr32(device, 0x40013c, 0xffffffff);
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nvkm_wr32(device, 0x400124, 0x00000002);
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nvkm_wr32(device, 0x409c24, 0x000e0000);
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nvkm_wr32(device, 0x405848, 0xc0000000);
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nvkm_wr32(device, 0x40584c, 0x00000001);
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nvkm_wr32(device, 0x404000, 0xc0000000);
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nvkm_wr32(device, 0x404600, 0xc0000000);
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nvkm_wr32(device, 0x408030, 0xc0000000);
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nvkm_wr32(device, 0x404490, 0xc0000000);
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nvkm_wr32(device, 0x406018, 0xc0000000);
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nvkm_wr32(device, 0x407020, 0x40000000);
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nvkm_wr32(device, 0x405840, 0xc0000000);
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nvkm_wr32(device, 0x405844, 0x00ffffff);
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nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
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gr->func->init_ppc_exceptions(gr);
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for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
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nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
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nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
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nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
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nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
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for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
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}
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nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
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nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
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}
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for (rop = 0; rop < gr->rop_nr; rop++) {
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nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000);
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nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000);
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nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
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nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
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}
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nvkm_wr32(device, 0x400108, 0xffffffff);
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nvkm_wr32(device, 0x400138, 0xffffffff);
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nvkm_wr32(device, 0x400118, 0xffffffff);
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nvkm_wr32(device, 0x400130, 0xffffffff);
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nvkm_wr32(device, 0x40011c, 0xffffffff);
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nvkm_wr32(device, 0x400134, 0xffffffff);
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nvkm_wr32(device, 0x400054, 0x2c350f63);
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gf100_gr_zbc_init(gr);
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return gf100_gr_init_ctxctl(gr);
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}
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int
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gm200_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,
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int index, struct nvkm_gr **pgr)
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{
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struct gf100_gr *gr;
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int ret;
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if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
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return -ENOMEM;
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*pgr = &gr->base;
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ret = gf100_gr_ctor(func, device, index, gr);
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if (ret)
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return ret;
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/* Load firmwares for non-secure falcons */
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if (!nvkm_secboot_is_managed(device->secboot,
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NVKM_SECBOOT_FALCON_FECS)) {
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if ((ret = gf100_gr_ctor_fw(gr, "gr/fecs_inst", &gr->fuc409c)) ||
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(ret = gf100_gr_ctor_fw(gr, "gr/fecs_data", &gr->fuc409d)))
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return ret;
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}
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if (!nvkm_secboot_is_managed(device->secboot,
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NVKM_SECBOOT_FALCON_GPCCS)) {
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if ((ret = gf100_gr_ctor_fw(gr, "gr/gpccs_inst", &gr->fuc41ac)) ||
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(ret = gf100_gr_ctor_fw(gr, "gr/gpccs_data", &gr->fuc41ad)))
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return ret;
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}
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if ((ret = gk20a_gr_av_to_init(gr, "gr/sw_nonctx", &gr->fuc_sw_nonctx)) ||
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(ret = gk20a_gr_aiv_to_init(gr, "gr/sw_ctx", &gr->fuc_sw_ctx)) ||
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(ret = gk20a_gr_av_to_init(gr, "gr/sw_bundle_init", &gr->fuc_bundle)) ||
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(ret = gk20a_gr_av_to_method(gr, "gr/sw_method_init", &gr->fuc_method)))
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return ret;
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return 0;
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}
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static const struct gf100_gr_func
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gm200_gr = {
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.init = gm200_gr_init,
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.init_gpc_mmu = gm200_gr_init_gpc_mmu,
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.init_rop_active_fbps = gm200_gr_init_rop_active_fbps,
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.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
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.rops = gm200_gr_rops,
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.ppc_nr = 2,
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.grctx = &gm200_grctx,
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.sclass = {
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{ -1, -1, FERMI_TWOD_A },
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{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
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{ -1, -1, MAXWELL_B, &gf100_fermi },
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{ -1, -1, MAXWELL_COMPUTE_B },
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{}
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}
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};
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int
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gm200_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
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{
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return gm200_gr_new_(&gm200_gr, device, index, pgr);
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}
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