141 lines
4.3 KiB
C
141 lines
4.3 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "rootnv50.h"
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#include "head.h"
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#include "dmacnv50.h"
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#include <core/ramht.h>
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#include <subdev/timer.h>
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#include <nvif/class.h>
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void
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gf119_disp_root_fini(struct nv50_disp_root *root)
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{
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struct nvkm_device *device = root->disp->base.engine.subdev.device;
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/* disable all interrupts */
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nvkm_wr32(device, 0x6100b0, 0x00000000);
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}
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int
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gf119_disp_root_init(struct nv50_disp_root *root)
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{
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struct nv50_disp *disp = root->disp;
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struct nvkm_head *head;
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struct nvkm_device *device = disp->base.engine.subdev.device;
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u32 tmp;
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int i;
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/* The below segments of code copying values from one register to
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* another appear to inform EVO of the display capabilities or
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* something similar.
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*/
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/* ... CRTC caps */
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list_for_each_entry(head, &disp->base.head, head) {
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const u32 hoff = head->id * 0x800;
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tmp = nvkm_rd32(device, 0x616104 + hoff);
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nvkm_wr32(device, 0x6101b4 + hoff, tmp);
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tmp = nvkm_rd32(device, 0x616108 + hoff);
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nvkm_wr32(device, 0x6101b8 + hoff, tmp);
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tmp = nvkm_rd32(device, 0x61610c + hoff);
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nvkm_wr32(device, 0x6101bc + hoff, tmp);
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}
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/* ... DAC caps */
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for (i = 0; i < disp->func->dac.nr; i++) {
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tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800));
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nvkm_wr32(device, 0x6101c0 + (i * 0x800), tmp);
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}
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/* ... SOR caps */
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for (i = 0; i < disp->func->sor.nr; i++) {
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tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
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nvkm_wr32(device, 0x6301c4 + (i * 0x800), tmp);
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}
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/* steal display away from vbios, or something like that */
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if (nvkm_rd32(device, 0x6100ac) & 0x00000100) {
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nvkm_wr32(device, 0x6100ac, 0x00000100);
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nvkm_mask(device, 0x6194e8, 0x00000001, 0x00000000);
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if (nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x6194e8) & 0x00000002))
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break;
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) < 0)
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return -EBUSY;
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}
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/* point at display engine memory area (hash table, objects) */
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nvkm_wr32(device, 0x610010, (root->instmem->addr >> 8) | 9);
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/* enable supervisor interrupts, disable everything else */
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nvkm_wr32(device, 0x610090, 0x00000000);
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nvkm_wr32(device, 0x6100a0, 0x00000000);
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nvkm_wr32(device, 0x6100b0, 0x00000307);
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/* disable underflow reporting, preventing an intermittent issue
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* on some gk104 boards where the production vbios left this
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* setting enabled by default.
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*
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* ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
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*/
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list_for_each_entry(head, &disp->base.head, head) {
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const u32 hoff = head->id * 0x800;
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nvkm_mask(device, 0x616308 + hoff, 0x00000111, 0x00000010);
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}
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return 0;
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}
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static const struct nv50_disp_root_func
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gf119_disp_root = {
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.init = gf119_disp_root_init,
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.fini = gf119_disp_root_fini,
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.dmac = {
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&gf119_disp_core_oclass,
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&gf119_disp_base_oclass,
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&gf119_disp_ovly_oclass,
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},
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.pioc = {
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&gf119_disp_oimm_oclass,
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&gf119_disp_curs_oclass,
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},
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};
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static int
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gf119_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
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void *data, u32 size, struct nvkm_object **pobject)
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{
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return nv50_disp_root_new_(&gf119_disp_root, disp, oclass,
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data, size, pobject);
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}
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const struct nvkm_disp_oclass
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gf119_disp_root_oclass = {
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.base.oclass = GF110_DISP,
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.base.minver = -1,
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.base.maxver = -1,
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.ctor = gf119_disp_root_new,
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};
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