310 lines
8.1 KiB
C
310 lines
8.1 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hdmi.h"
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struct hdmi_bridge {
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struct drm_bridge base;
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struct hdmi *hdmi;
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};
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#define to_hdmi_bridge(x) container_of(x, struct hdmi_bridge, base)
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void msm_hdmi_bridge_destroy(struct drm_bridge *bridge)
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{
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}
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static void msm_hdmi_power_on(struct drm_bridge *bridge)
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{
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struct drm_device *dev = bridge->dev;
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struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
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struct hdmi *hdmi = hdmi_bridge->hdmi;
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const struct hdmi_platform_config *config = hdmi->config;
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int i, ret;
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pm_runtime_get_sync(&hdmi->pdev->dev);
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for (i = 0; i < config->pwr_reg_cnt; i++) {
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ret = regulator_enable(hdmi->pwr_regs[i]);
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if (ret) {
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dev_err(dev->dev, "failed to enable pwr regulator: %s (%d)\n",
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config->pwr_reg_names[i], ret);
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}
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}
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if (config->pwr_clk_cnt > 0) {
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DBG("pixclock: %lu", hdmi->pixclock);
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ret = clk_set_rate(hdmi->pwr_clks[0], hdmi->pixclock);
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if (ret) {
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dev_err(dev->dev, "failed to set pixel clk: %s (%d)\n",
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config->pwr_clk_names[0], ret);
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}
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}
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for (i = 0; i < config->pwr_clk_cnt; i++) {
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ret = clk_prepare_enable(hdmi->pwr_clks[i]);
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if (ret) {
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dev_err(dev->dev, "failed to enable pwr clk: %s (%d)\n",
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config->pwr_clk_names[i], ret);
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}
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}
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}
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static void power_off(struct drm_bridge *bridge)
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{
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struct drm_device *dev = bridge->dev;
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struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
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struct hdmi *hdmi = hdmi_bridge->hdmi;
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const struct hdmi_platform_config *config = hdmi->config;
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int i, ret;
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/* TODO do we need to wait for final vblank somewhere before
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* cutting the clocks?
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*/
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mdelay(16 + 4);
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for (i = 0; i < config->pwr_clk_cnt; i++)
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clk_disable_unprepare(hdmi->pwr_clks[i]);
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for (i = 0; i < config->pwr_reg_cnt; i++) {
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ret = regulator_disable(hdmi->pwr_regs[i]);
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if (ret) {
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dev_err(dev->dev, "failed to disable pwr regulator: %s (%d)\n",
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config->pwr_reg_names[i], ret);
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}
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}
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pm_runtime_put_autosuspend(&hdmi->pdev->dev);
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}
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#define AVI_IFRAME_LINE_NUMBER 1
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static void msm_hdmi_config_avi_infoframe(struct hdmi *hdmi)
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{
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struct drm_crtc *crtc = hdmi->encoder->crtc;
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const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
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union hdmi_infoframe frame;
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u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
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u32 val;
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int len;
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drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false);
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len = hdmi_infoframe_pack(&frame, buffer, sizeof(buffer));
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if (len < 0) {
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dev_err(&hdmi->pdev->dev,
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"failed to configure avi infoframe\n");
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return;
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}
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/*
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* the AVI_INFOx registers don't map exactly to how the AVI infoframes
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* are packed according to the spec. The checksum from the header is
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* written to the LSB byte of AVI_INFO0 and the version is written to
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* the third byte from the LSB of AVI_INFO3
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*/
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hdmi_write(hdmi, REG_HDMI_AVI_INFO(0),
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buffer[3] |
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buffer[4] << 8 |
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buffer[5] << 16 |
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buffer[6] << 24);
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hdmi_write(hdmi, REG_HDMI_AVI_INFO(1),
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buffer[7] |
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buffer[8] << 8 |
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buffer[9] << 16 |
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buffer[10] << 24);
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hdmi_write(hdmi, REG_HDMI_AVI_INFO(2),
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buffer[11] |
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buffer[12] << 8 |
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buffer[13] << 16 |
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buffer[14] << 24);
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hdmi_write(hdmi, REG_HDMI_AVI_INFO(3),
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buffer[15] |
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buffer[16] << 8 |
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buffer[1] << 24);
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hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0,
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HDMI_INFOFRAME_CTRL0_AVI_SEND |
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HDMI_INFOFRAME_CTRL0_AVI_CONT);
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val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1);
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val &= ~HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK;
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val |= HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(AVI_IFRAME_LINE_NUMBER);
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hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL1, val);
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}
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static void msm_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
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{
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struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
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struct hdmi *hdmi = hdmi_bridge->hdmi;
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struct hdmi_phy *phy = hdmi->phy;
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DBG("power up");
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if (!hdmi->power_on) {
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msm_hdmi_phy_resource_enable(phy);
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msm_hdmi_power_on(bridge);
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hdmi->power_on = true;
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if (hdmi->hdmi_mode) {
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msm_hdmi_config_avi_infoframe(hdmi);
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msm_hdmi_audio_update(hdmi);
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}
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}
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msm_hdmi_phy_powerup(phy, hdmi->pixclock);
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msm_hdmi_set_mode(hdmi, true);
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if (hdmi->hdcp_ctrl)
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msm_hdmi_hdcp_on(hdmi->hdcp_ctrl);
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}
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static void msm_hdmi_bridge_enable(struct drm_bridge *bridge)
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{
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}
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static void msm_hdmi_bridge_disable(struct drm_bridge *bridge)
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{
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}
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static void msm_hdmi_bridge_post_disable(struct drm_bridge *bridge)
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{
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struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
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struct hdmi *hdmi = hdmi_bridge->hdmi;
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struct hdmi_phy *phy = hdmi->phy;
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if (hdmi->hdcp_ctrl)
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msm_hdmi_hdcp_off(hdmi->hdcp_ctrl);
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DBG("power down");
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msm_hdmi_set_mode(hdmi, false);
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msm_hdmi_phy_powerdown(phy);
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if (hdmi->power_on) {
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power_off(bridge);
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hdmi->power_on = false;
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if (hdmi->hdmi_mode)
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msm_hdmi_audio_update(hdmi);
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msm_hdmi_phy_resource_disable(phy);
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}
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}
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static void msm_hdmi_bridge_mode_set(struct drm_bridge *bridge,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
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struct hdmi *hdmi = hdmi_bridge->hdmi;
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int hstart, hend, vstart, vend;
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uint32_t frame_ctrl;
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mode = adjusted_mode;
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hdmi->pixclock = mode->clock * 1000;
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hstart = mode->htotal - mode->hsync_start;
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hend = mode->htotal - mode->hsync_start + mode->hdisplay;
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vstart = mode->vtotal - mode->vsync_start - 1;
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vend = mode->vtotal - mode->vsync_start + mode->vdisplay - 1;
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DBG("htotal=%d, vtotal=%d, hstart=%d, hend=%d, vstart=%d, vend=%d",
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mode->htotal, mode->vtotal, hstart, hend, vstart, vend);
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hdmi_write(hdmi, REG_HDMI_TOTAL,
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HDMI_TOTAL_H_TOTAL(mode->htotal - 1) |
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HDMI_TOTAL_V_TOTAL(mode->vtotal - 1));
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hdmi_write(hdmi, REG_HDMI_ACTIVE_HSYNC,
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HDMI_ACTIVE_HSYNC_START(hstart) |
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HDMI_ACTIVE_HSYNC_END(hend));
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hdmi_write(hdmi, REG_HDMI_ACTIVE_VSYNC,
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HDMI_ACTIVE_VSYNC_START(vstart) |
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HDMI_ACTIVE_VSYNC_END(vend));
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if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
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hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
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HDMI_VSYNC_TOTAL_F2_V_TOTAL(mode->vtotal));
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hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
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HDMI_VSYNC_ACTIVE_F2_START(vstart + 1) |
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HDMI_VSYNC_ACTIVE_F2_END(vend + 1));
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} else {
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hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
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HDMI_VSYNC_TOTAL_F2_V_TOTAL(0));
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hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
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HDMI_VSYNC_ACTIVE_F2_START(0) |
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HDMI_VSYNC_ACTIVE_F2_END(0));
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}
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frame_ctrl = 0;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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frame_ctrl |= HDMI_FRAME_CTRL_HSYNC_LOW;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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frame_ctrl |= HDMI_FRAME_CTRL_VSYNC_LOW;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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frame_ctrl |= HDMI_FRAME_CTRL_INTERLACED_EN;
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DBG("frame_ctrl=%08x", frame_ctrl);
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hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl);
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if (hdmi->hdmi_mode)
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msm_hdmi_audio_update(hdmi);
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}
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static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = {
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.pre_enable = msm_hdmi_bridge_pre_enable,
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.enable = msm_hdmi_bridge_enable,
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.disable = msm_hdmi_bridge_disable,
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.post_disable = msm_hdmi_bridge_post_disable,
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.mode_set = msm_hdmi_bridge_mode_set,
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};
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/* initialize bridge */
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struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi)
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{
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struct drm_bridge *bridge = NULL;
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struct hdmi_bridge *hdmi_bridge;
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int ret;
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hdmi_bridge = devm_kzalloc(hdmi->dev->dev,
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sizeof(*hdmi_bridge), GFP_KERNEL);
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if (!hdmi_bridge) {
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ret = -ENOMEM;
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goto fail;
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}
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hdmi_bridge->hdmi = hdmi;
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bridge = &hdmi_bridge->base;
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bridge->funcs = &msm_hdmi_bridge_funcs;
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ret = drm_bridge_attach(hdmi->encoder, bridge, NULL);
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if (ret)
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goto fail;
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return bridge;
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fail:
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if (bridge)
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msm_hdmi_bridge_destroy(bridge);
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return ERR_PTR(ret);
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}
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