466 lines
14 KiB
C
466 lines
14 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "i915_drv.h"
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#define PLATFORM_NAME(x) [INTEL_##x] = #x
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static const char * const platform_names[] = {
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PLATFORM_NAME(I830),
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PLATFORM_NAME(I845G),
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PLATFORM_NAME(I85X),
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PLATFORM_NAME(I865G),
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PLATFORM_NAME(I915G),
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PLATFORM_NAME(I915GM),
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PLATFORM_NAME(I945G),
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PLATFORM_NAME(I945GM),
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PLATFORM_NAME(G33),
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PLATFORM_NAME(PINEVIEW),
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PLATFORM_NAME(I965G),
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PLATFORM_NAME(I965GM),
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PLATFORM_NAME(G45),
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PLATFORM_NAME(GM45),
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PLATFORM_NAME(IRONLAKE),
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PLATFORM_NAME(SANDYBRIDGE),
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PLATFORM_NAME(IVYBRIDGE),
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PLATFORM_NAME(VALLEYVIEW),
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PLATFORM_NAME(HASWELL),
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PLATFORM_NAME(BROADWELL),
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PLATFORM_NAME(CHERRYVIEW),
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PLATFORM_NAME(SKYLAKE),
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PLATFORM_NAME(BROXTON),
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PLATFORM_NAME(KABYLAKE),
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PLATFORM_NAME(GEMINILAKE),
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PLATFORM_NAME(COFFEELAKE),
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PLATFORM_NAME(CANNONLAKE),
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};
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#undef PLATFORM_NAME
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const char *intel_platform_name(enum intel_platform platform)
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{
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BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
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if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
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platform_names[platform] == NULL))
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return "<unknown>";
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return platform_names[platform];
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}
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void intel_device_info_dump(struct drm_i915_private *dev_priv)
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{
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const struct intel_device_info *info = &dev_priv->info;
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DRM_DEBUG_DRIVER("i915 device info: platform=%s gen=%i pciid=0x%04x rev=0x%02x",
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intel_platform_name(info->platform),
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info->gen,
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dev_priv->drm.pdev->device,
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dev_priv->drm.pdev->revision);
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#define PRINT_FLAG(name) \
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DRM_DEBUG_DRIVER("i915 device info: " #name ": %s", yesno(info->name))
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DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
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#undef PRINT_FLAG
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}
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static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
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{
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struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
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const u32 fuse2 = I915_READ(GEN8_FUSE2);
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sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
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GEN10_F2_S_ENA_SHIFT;
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sseu->subslice_mask = (1 << 4) - 1;
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sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
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GEN10_F2_SS_DIS_SHIFT);
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sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
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sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
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sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
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sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
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GEN10_EU_DIS_SS_MASK));
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/*
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* CNL is expected to always have a uniform distribution
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* of EU across subslices with the exception that any one
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* EU in any one subslice may be fused off for die
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* recovery.
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*/
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sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
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DIV_ROUND_UP(sseu->eu_total,
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sseu_subslice_total(sseu)) : 0;
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/* No restrictions on Power Gating */
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sseu->has_slice_pg = 1;
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sseu->has_subslice_pg = 1;
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sseu->has_eu_pg = 1;
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}
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static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
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{
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struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
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u32 fuse, eu_dis;
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fuse = I915_READ(CHV_FUSE_GT);
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sseu->slice_mask = BIT(0);
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if (!(fuse & CHV_FGT_DISABLE_SS0)) {
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sseu->subslice_mask |= BIT(0);
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eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
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CHV_FGT_EU_DIS_SS0_R1_MASK);
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sseu->eu_total += 8 - hweight32(eu_dis);
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}
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if (!(fuse & CHV_FGT_DISABLE_SS1)) {
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sseu->subslice_mask |= BIT(1);
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eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
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CHV_FGT_EU_DIS_SS1_R1_MASK);
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sseu->eu_total += 8 - hweight32(eu_dis);
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}
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/*
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* CHV expected to always have a uniform distribution of EU
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* across subslices.
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*/
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sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
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sseu->eu_total / sseu_subslice_total(sseu) :
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0;
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/*
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* CHV supports subslice power gating on devices with more than
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* one subslice, and supports EU power gating on devices with
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* more than one EU pair per subslice.
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*/
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sseu->has_slice_pg = 0;
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sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1;
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sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
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}
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static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
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{
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struct intel_device_info *info = mkwrite_device_info(dev_priv);
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struct sseu_dev_info *sseu = &info->sseu;
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int s_max = 3, ss_max = 4, eu_max = 8;
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int s, ss;
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u32 fuse2, eu_disable;
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u8 eu_mask = 0xff;
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fuse2 = I915_READ(GEN8_FUSE2);
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sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
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/*
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* The subslice disable field is global, i.e. it applies
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* to each of the enabled slices.
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*/
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sseu->subslice_mask = (1 << ss_max) - 1;
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sseu->subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
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GEN9_F2_SS_DIS_SHIFT);
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/*
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* Iterate through enabled slices and subslices to
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* count the total enabled EU.
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*/
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for (s = 0; s < s_max; s++) {
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if (!(sseu->slice_mask & BIT(s)))
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/* skip disabled slice */
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continue;
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eu_disable = I915_READ(GEN9_EU_DISABLE(s));
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for (ss = 0; ss < ss_max; ss++) {
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int eu_per_ss;
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if (!(sseu->subslice_mask & BIT(ss)))
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/* skip disabled subslice */
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continue;
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eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
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eu_mask);
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/*
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* Record which subslice(s) has(have) 7 EUs. we
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* can tune the hash used to spread work among
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* subslices if they are unbalanced.
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*/
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if (eu_per_ss == 7)
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sseu->subslice_7eu[s] |= BIT(ss);
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sseu->eu_total += eu_per_ss;
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}
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}
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/*
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* SKL is expected to always have a uniform distribution
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* of EU across subslices with the exception that any one
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* EU in any one subslice may be fused off for die
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* recovery. BXT is expected to be perfectly uniform in EU
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* distribution.
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*/
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sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
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DIV_ROUND_UP(sseu->eu_total,
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sseu_subslice_total(sseu)) : 0;
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/*
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* SKL+ supports slice power gating on devices with more than
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* one slice, and supports EU power gating on devices with
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* more than one EU pair per subslice. BXT+ supports subslice
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* power gating on devices with more than one subslice, and
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* supports EU power gating on devices with more than one EU
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* pair per subslice.
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*/
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sseu->has_slice_pg =
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!IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
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sseu->has_subslice_pg =
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IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
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sseu->has_eu_pg = sseu->eu_per_subslice > 2;
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if (IS_GEN9_LP(dev_priv)) {
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#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask & BIT(ss)))
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info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
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/*
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* There is a HW issue in 2x6 fused down parts that requires
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* Pooled EU to be enabled as a WA. The pool configuration
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* changes depending upon which subslice is fused down. This
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* doesn't affect if the device has all 3 subslices enabled.
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*/
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/* WaEnablePooledEuFor2x6:bxt */
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info->has_pooled_eu |= (hweight8(sseu->subslice_mask) == 2 &&
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IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST));
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sseu->min_eu_in_pool = 0;
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if (info->has_pooled_eu) {
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if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
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sseu->min_eu_in_pool = 3;
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else if (IS_SS_DISABLED(1))
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sseu->min_eu_in_pool = 6;
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else
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sseu->min_eu_in_pool = 9;
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}
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#undef IS_SS_DISABLED
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}
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}
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static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
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{
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struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
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const int s_max = 3, ss_max = 3, eu_max = 8;
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int s, ss;
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u32 fuse2, eu_disable[3]; /* s_max */
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fuse2 = I915_READ(GEN8_FUSE2);
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sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
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/*
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* The subslice disable field is global, i.e. it applies
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* to each of the enabled slices.
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*/
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sseu->subslice_mask = GENMASK(ss_max - 1, 0);
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sseu->subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
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GEN8_F2_SS_DIS_SHIFT);
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eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
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eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
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((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
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(32 - GEN8_EU_DIS0_S1_SHIFT));
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eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
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((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
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(32 - GEN8_EU_DIS1_S2_SHIFT));
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/*
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* Iterate through enabled slices and subslices to
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* count the total enabled EU.
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*/
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for (s = 0; s < s_max; s++) {
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if (!(sseu->slice_mask & BIT(s)))
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/* skip disabled slice */
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continue;
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for (ss = 0; ss < ss_max; ss++) {
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u32 n_disabled;
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if (!(sseu->subslice_mask & BIT(ss)))
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/* skip disabled subslice */
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continue;
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n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
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/*
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* Record which subslices have 7 EUs.
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*/
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if (eu_max - n_disabled == 7)
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sseu->subslice_7eu[s] |= 1 << ss;
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sseu->eu_total += eu_max - n_disabled;
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}
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}
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/*
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* BDW is expected to always have a uniform distribution of EU across
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* subslices with the exception that any one EU in any one subslice may
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* be fused off for die recovery.
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*/
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sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
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DIV_ROUND_UP(sseu->eu_total,
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sseu_subslice_total(sseu)) : 0;
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/*
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* BDW supports slice power gating on devices with more than
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* one slice.
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*/
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sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
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sseu->has_subslice_pg = 0;
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sseu->has_eu_pg = 0;
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}
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/*
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* Determine various intel_device_info fields at runtime.
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*
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* Use it when either:
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* - it's judged too laborious to fill n static structures with the limit
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* when a simple if statement does the job,
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* - run-time checks (eg read fuse/strap registers) are needed.
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*
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* This function needs to be called:
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* - after the MMIO has been setup as we are reading registers,
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* - after the PCH has been detected,
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* - before the first usage of the fields it can tweak.
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*/
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void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
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{
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struct intel_device_info *info = mkwrite_device_info(dev_priv);
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enum pipe pipe;
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if (INTEL_GEN(dev_priv) >= 9) {
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info->num_scalers[PIPE_A] = 2;
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info->num_scalers[PIPE_B] = 2;
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info->num_scalers[PIPE_C] = 1;
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}
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/*
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* Skylake and Broxton currently don't expose the topmost plane as its
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* use is exclusive with the legacy cursor and we only want to expose
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* one of those, not both. Until we can safely expose the topmost plane
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* as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
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* we don't expose the topmost plane at all to prevent ABI breakage
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* down the line.
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*/
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if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv))
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for_each_pipe(dev_priv, pipe)
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info->num_sprites[pipe] = 3;
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else if (IS_BROXTON(dev_priv)) {
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info->num_sprites[PIPE_A] = 2;
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info->num_sprites[PIPE_B] = 2;
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info->num_sprites[PIPE_C] = 1;
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} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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for_each_pipe(dev_priv, pipe)
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info->num_sprites[pipe] = 2;
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} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
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for_each_pipe(dev_priv, pipe)
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info->num_sprites[pipe] = 1;
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}
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if (i915_modparams.disable_display) {
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DRM_INFO("Display disabled (module parameter)\n");
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info->num_pipes = 0;
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} else if (info->num_pipes > 0 &&
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(IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
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HAS_PCH_SPLIT(dev_priv)) {
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u32 fuse_strap = I915_READ(FUSE_STRAP);
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u32 sfuse_strap = I915_READ(SFUSE_STRAP);
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/*
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* SFUSE_STRAP is supposed to have a bit signalling the display
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* is fused off. Unfortunately it seems that, at least in
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* certain cases, fused off display means that PCH display
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* reads don't land anywhere. In that case, we read 0s.
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*
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* On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
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* should be set when taking over after the firmware.
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*/
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if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
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sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
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(HAS_PCH_CPT(dev_priv) &&
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!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
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DRM_INFO("Display fused off, disabling\n");
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info->num_pipes = 0;
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} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
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DRM_INFO("PipeC fused off\n");
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info->num_pipes -= 1;
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}
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} else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
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u32 dfsm = I915_READ(SKL_DFSM);
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u8 disabled_mask = 0;
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bool invalid;
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int num_bits;
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if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
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disabled_mask |= BIT(PIPE_A);
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if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
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disabled_mask |= BIT(PIPE_B);
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if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
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disabled_mask |= BIT(PIPE_C);
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num_bits = hweight8(disabled_mask);
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switch (disabled_mask) {
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case BIT(PIPE_A):
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case BIT(PIPE_B):
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case BIT(PIPE_A) | BIT(PIPE_B):
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case BIT(PIPE_A) | BIT(PIPE_C):
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invalid = true;
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break;
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default:
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invalid = false;
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}
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if (num_bits > info->num_pipes || invalid)
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DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
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disabled_mask);
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else
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info->num_pipes -= num_bits;
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}
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/* Initialize slice/subslice/EU info */
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if (IS_CHERRYVIEW(dev_priv))
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cherryview_sseu_info_init(dev_priv);
|
|
else if (IS_BROADWELL(dev_priv))
|
|
broadwell_sseu_info_init(dev_priv);
|
|
else if (INTEL_GEN(dev_priv) == 9)
|
|
gen9_sseu_info_init(dev_priv);
|
|
else if (INTEL_GEN(dev_priv) >= 10)
|
|
gen10_sseu_info_init(dev_priv);
|
|
|
|
DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
|
|
DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
|
|
DRM_DEBUG_DRIVER("subslice total: %u\n",
|
|
sseu_subslice_total(&info->sseu));
|
|
DRM_DEBUG_DRIVER("subslice mask %04x\n", info->sseu.subslice_mask);
|
|
DRM_DEBUG_DRIVER("subslice per slice: %u\n",
|
|
hweight8(info->sseu.subslice_mask));
|
|
DRM_DEBUG_DRIVER("EU total: %u\n", info->sseu.eu_total);
|
|
DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->sseu.eu_per_subslice);
|
|
DRM_DEBUG_DRIVER("has slice power gating: %s\n",
|
|
info->sseu.has_slice_pg ? "y" : "n");
|
|
DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
|
|
info->sseu.has_subslice_pg ? "y" : "n");
|
|
DRM_DEBUG_DRIVER("has EU power gating: %s\n",
|
|
info->sseu.has_eu_pg ? "y" : "n");
|
|
}
|