685 lines
16 KiB
C
685 lines
16 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors: Dave Airlie <airlied@redhat.com>
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*/
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#include <drm/drmP.h>
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#include "ast_drv.h"
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_crtc_helper.h>
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void ast_set_index_reg_mask(struct ast_private *ast,
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uint32_t base, uint8_t index,
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uint8_t mask, uint8_t val)
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{
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u8 tmp;
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ast_io_write8(ast, base, index);
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tmp = (ast_io_read8(ast, base + 1) & mask) | val;
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ast_set_index_reg(ast, base, index, tmp);
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}
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uint8_t ast_get_index_reg(struct ast_private *ast,
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uint32_t base, uint8_t index)
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{
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uint8_t ret;
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ast_io_write8(ast, base, index);
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ret = ast_io_read8(ast, base + 1);
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return ret;
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}
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uint8_t ast_get_index_reg_mask(struct ast_private *ast,
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uint32_t base, uint8_t index, uint8_t mask)
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{
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uint8_t ret;
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ast_io_write8(ast, base, index);
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ret = ast_io_read8(ast, base + 1) & mask;
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return ret;
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}
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static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
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{
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struct device_node *np = dev->pdev->dev.of_node;
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struct ast_private *ast = dev->dev_private;
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uint32_t data, jregd0, jregd1;
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/* Defaults */
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ast->config_mode = ast_use_defaults;
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*scu_rev = 0xffffffff;
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/* Check if we have device-tree properties */
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if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
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scu_rev)) {
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/* We do, disable P2A access */
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ast->config_mode = ast_use_dt;
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DRM_INFO("Using device-tree for configuration\n");
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return;
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}
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/* Not all families have a P2A bridge */
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if (dev->pdev->device != PCI_CHIP_AST2000)
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return;
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/*
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* The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
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* is disabled. We force using P2A if VGA only mode bit
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* is set D[7]
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*/
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jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
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jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
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if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
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/* Double check it's actually working */
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data = ast_read32(ast, 0xf004);
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if (data != 0xFFFFFFFF) {
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/* P2A works, grab silicon revision */
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ast->config_mode = ast_use_p2a;
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DRM_INFO("Using P2A bridge for configuration\n");
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/* Read SCU7c (silicon revision register) */
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ast_write32(ast, 0xf004, 0x1e6e0000);
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ast_write32(ast, 0xf000, 0x1);
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*scu_rev = ast_read32(ast, 0x1207c);
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return;
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}
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}
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/* We have a P2A bridge but it's disabled */
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DRM_INFO("P2A bridge disabled, using default configuration\n");
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}
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static int ast_detect_chip(struct drm_device *dev, bool *need_post)
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{
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struct ast_private *ast = dev->dev_private;
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uint32_t jreg, scu_rev;
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/*
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* If VGA isn't enabled, we need to enable now or subsequent
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* access to the scratch registers will fail. We also inform
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* our caller that it needs to POST the chip
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* (Assumption: VGA not enabled -> need to POST)
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*/
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if (!ast_is_vga_enabled(dev)) {
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ast_enable_vga(dev);
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DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
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*need_post = true;
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} else
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*need_post = false;
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/* Enable extended register access */
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ast_enable_mmio(dev);
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ast_open_key(ast);
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/* Find out whether P2A works or whether to use device-tree */
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ast_detect_config_mode(dev, &scu_rev);
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/* Identify chipset */
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if (dev->pdev->device == PCI_CHIP_AST1180) {
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ast->chip = AST1100;
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DRM_INFO("AST 1180 detected\n");
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} else {
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if (dev->pdev->revision >= 0x40) {
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ast->chip = AST2500;
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DRM_INFO("AST 2500 detected\n");
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} else if (dev->pdev->revision >= 0x30) {
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ast->chip = AST2400;
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DRM_INFO("AST 2400 detected\n");
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} else if (dev->pdev->revision >= 0x20) {
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ast->chip = AST2300;
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DRM_INFO("AST 2300 detected\n");
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} else if (dev->pdev->revision >= 0x10) {
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switch (scu_rev & 0x0300) {
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case 0x0200:
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ast->chip = AST1100;
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DRM_INFO("AST 1100 detected\n");
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break;
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case 0x0100:
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ast->chip = AST2200;
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DRM_INFO("AST 2200 detected\n");
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break;
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case 0x0000:
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ast->chip = AST2150;
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DRM_INFO("AST 2150 detected\n");
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break;
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default:
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ast->chip = AST2100;
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DRM_INFO("AST 2100 detected\n");
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break;
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}
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ast->vga2_clone = false;
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} else {
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ast->chip = AST2000;
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DRM_INFO("AST 2000 detected\n");
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}
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}
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/* Check if we support wide screen */
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switch (ast->chip) {
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case AST1180:
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ast->support_wide_screen = true;
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break;
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case AST2000:
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ast->support_wide_screen = false;
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break;
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default:
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
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if (!(jreg & 0x80))
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ast->support_wide_screen = true;
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else if (jreg & 0x01)
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ast->support_wide_screen = true;
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else {
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ast->support_wide_screen = false;
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if (ast->chip == AST2300 &&
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(scu_rev & 0x300) == 0x0) /* ast1300 */
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ast->support_wide_screen = true;
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if (ast->chip == AST2400 &&
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(scu_rev & 0x300) == 0x100) /* ast1400 */
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ast->support_wide_screen = true;
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if (ast->chip == AST2500 &&
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scu_rev == 0x100) /* ast2510 */
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ast->support_wide_screen = true;
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}
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break;
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}
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/* Check 3rd Tx option (digital output afaik) */
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ast->tx_chip_type = AST_TX_NONE;
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/*
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* VGACRA3 Enhanced Color Mode Register, check if DVO is already
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* enabled, in that case, assume we have a SIL164 TMDS transmitter
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*
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* Don't make that assumption if we the chip wasn't enabled and
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* is at power-on reset, otherwise we'll incorrectly "detect" a
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* SIL164 when there is none.
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*/
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if (!*need_post) {
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
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if (jreg & 0x80)
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ast->tx_chip_type = AST_TX_SIL164;
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}
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if ((ast->chip == AST2300) || (ast->chip == AST2400)) {
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/*
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* On AST2300 and 2400, look the configuration set by the SoC in
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* the SOC scratch register #1 bits 11:8 (interestingly marked
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* as "reserved" in the spec)
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*/
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
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switch (jreg) {
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case 0x04:
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ast->tx_chip_type = AST_TX_SIL164;
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break;
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case 0x08:
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ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL);
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if (ast->dp501_fw_addr) {
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/* backup firmware */
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if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
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kfree(ast->dp501_fw_addr);
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ast->dp501_fw_addr = NULL;
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}
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}
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/* fallthrough */
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case 0x0c:
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ast->tx_chip_type = AST_TX_DP501;
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}
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}
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/* Print stuff for diagnostic purposes */
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switch(ast->tx_chip_type) {
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case AST_TX_SIL164:
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DRM_INFO("Using Sil164 TMDS transmitter\n");
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break;
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case AST_TX_DP501:
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DRM_INFO("Using DP501 DisplayPort transmitter\n");
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break;
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default:
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DRM_INFO("Analog VGA only\n");
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}
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return 0;
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}
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static int ast_get_dram_info(struct drm_device *dev)
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{
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struct device_node *np = dev->pdev->dev.of_node;
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struct ast_private *ast = dev->dev_private;
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uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
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uint32_t denum, num, div, ref_pll, dsel;
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switch (ast->config_mode) {
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case ast_use_dt:
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/*
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* If some properties are missing, use reasonable
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* defaults for AST2400
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*/
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if (of_property_read_u32(np, "aspeed,mcr-configuration",
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&mcr_cfg))
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mcr_cfg = 0x00000577;
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if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
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&mcr_scu_mpll))
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mcr_scu_mpll = 0x000050C0;
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if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
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&mcr_scu_strap))
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mcr_scu_strap = 0;
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break;
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case ast_use_p2a:
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ast_write32(ast, 0xf004, 0x1e6e0000);
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ast_write32(ast, 0xf000, 0x1);
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mcr_cfg = ast_read32(ast, 0x10004);
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mcr_scu_mpll = ast_read32(ast, 0x10120);
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mcr_scu_strap = ast_read32(ast, 0x10170);
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break;
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case ast_use_defaults:
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default:
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ast->dram_bus_width = 16;
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ast->dram_type = AST_DRAM_1Gx16;
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if (ast->chip == AST2500)
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ast->mclk = 800;
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else
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ast->mclk = 396;
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return 0;
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}
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if (mcr_cfg & 0x40)
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ast->dram_bus_width = 16;
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else
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ast->dram_bus_width = 32;
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if (ast->chip == AST2500) {
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switch (mcr_cfg & 0x03) {
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case 0:
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ast->dram_type = AST_DRAM_1Gx16;
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break;
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default:
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case 1:
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ast->dram_type = AST_DRAM_2Gx16;
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break;
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case 2:
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ast->dram_type = AST_DRAM_4Gx16;
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break;
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case 3:
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ast->dram_type = AST_DRAM_8Gx16;
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break;
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}
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} else if (ast->chip == AST2300 || ast->chip == AST2400) {
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switch (mcr_cfg & 0x03) {
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case 0:
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ast->dram_type = AST_DRAM_512Mx16;
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break;
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default:
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case 1:
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ast->dram_type = AST_DRAM_1Gx16;
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break;
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case 2:
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ast->dram_type = AST_DRAM_2Gx16;
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break;
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case 3:
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ast->dram_type = AST_DRAM_4Gx16;
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break;
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}
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} else {
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switch (mcr_cfg & 0x0c) {
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case 0:
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case 4:
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ast->dram_type = AST_DRAM_512Mx16;
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break;
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case 8:
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if (mcr_cfg & 0x40)
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ast->dram_type = AST_DRAM_1Gx16;
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else
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ast->dram_type = AST_DRAM_512Mx32;
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break;
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case 0xc:
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ast->dram_type = AST_DRAM_1Gx32;
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break;
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}
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}
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if (mcr_scu_strap & 0x2000)
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ref_pll = 14318;
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else
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ref_pll = 12000;
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denum = mcr_scu_mpll & 0x1f;
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num = (mcr_scu_mpll & 0x3fe0) >> 5;
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dsel = (mcr_scu_mpll & 0xc000) >> 14;
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switch (dsel) {
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case 3:
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div = 0x4;
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break;
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case 2:
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case 1:
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div = 0x2;
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break;
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default:
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div = 0x1;
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break;
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}
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ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
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return 0;
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}
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static void ast_user_framebuffer_destroy(struct drm_framebuffer *fb)
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{
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struct ast_framebuffer *ast_fb = to_ast_framebuffer(fb);
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drm_gem_object_put_unlocked(ast_fb->obj);
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drm_framebuffer_cleanup(fb);
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kfree(ast_fb);
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}
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static const struct drm_framebuffer_funcs ast_fb_funcs = {
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.destroy = ast_user_framebuffer_destroy,
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};
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int ast_framebuffer_init(struct drm_device *dev,
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struct ast_framebuffer *ast_fb,
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const struct drm_mode_fb_cmd2 *mode_cmd,
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struct drm_gem_object *obj)
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{
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int ret;
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drm_helper_mode_fill_fb_struct(dev, &ast_fb->base, mode_cmd);
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ast_fb->obj = obj;
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ret = drm_framebuffer_init(dev, &ast_fb->base, &ast_fb_funcs);
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if (ret) {
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DRM_ERROR("framebuffer init failed %d\n", ret);
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return ret;
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}
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return 0;
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}
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static struct drm_framebuffer *
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ast_user_framebuffer_create(struct drm_device *dev,
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struct drm_file *filp,
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const struct drm_mode_fb_cmd2 *mode_cmd)
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{
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struct drm_gem_object *obj;
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struct ast_framebuffer *ast_fb;
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int ret;
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obj = drm_gem_object_lookup(filp, mode_cmd->handles[0]);
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if (obj == NULL)
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return ERR_PTR(-ENOENT);
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ast_fb = kzalloc(sizeof(*ast_fb), GFP_KERNEL);
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if (!ast_fb) {
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drm_gem_object_put_unlocked(obj);
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return ERR_PTR(-ENOMEM);
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}
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ret = ast_framebuffer_init(dev, ast_fb, mode_cmd, obj);
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if (ret) {
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drm_gem_object_put_unlocked(obj);
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kfree(ast_fb);
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return ERR_PTR(ret);
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}
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return &ast_fb->base;
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}
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static const struct drm_mode_config_funcs ast_mode_funcs = {
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.fb_create = ast_user_framebuffer_create,
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};
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static u32 ast_get_vram_info(struct drm_device *dev)
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{
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struct ast_private *ast = dev->dev_private;
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u8 jreg;
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u32 vram_size;
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ast_open_key(ast);
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vram_size = AST_VIDMEM_DEFAULT_SIZE;
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff);
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switch (jreg & 3) {
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case 0: vram_size = AST_VIDMEM_SIZE_8M; break;
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case 1: vram_size = AST_VIDMEM_SIZE_16M; break;
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case 2: vram_size = AST_VIDMEM_SIZE_32M; break;
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case 3: vram_size = AST_VIDMEM_SIZE_64M; break;
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}
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff);
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switch (jreg & 0x03) {
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case 1:
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vram_size -= 0x100000;
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break;
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case 2:
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vram_size -= 0x200000;
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break;
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case 3:
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vram_size -= 0x400000;
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break;
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}
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return vram_size;
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}
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int ast_driver_load(struct drm_device *dev, unsigned long flags)
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{
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struct ast_private *ast;
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bool need_post;
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int ret = 0;
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ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL);
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if (!ast)
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return -ENOMEM;
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dev->dev_private = ast;
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ast->dev = dev;
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ast->regs = pci_iomap(dev->pdev, 1, 0);
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if (!ast->regs) {
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ret = -EIO;
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goto out_free;
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}
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/*
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* If we don't have IO space at all, use MMIO now and
|
|
* assume the chip has MMIO enabled by default (rev 0x20
|
|
* and higher).
|
|
*/
|
|
if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) {
|
|
DRM_INFO("platform has no IO space, trying MMIO\n");
|
|
ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
|
|
}
|
|
|
|
/* "map" IO regs if the above hasn't done so already */
|
|
if (!ast->ioregs) {
|
|
ast->ioregs = pci_iomap(dev->pdev, 2, 0);
|
|
if (!ast->ioregs) {
|
|
ret = -EIO;
|
|
goto out_free;
|
|
}
|
|
}
|
|
|
|
ast_detect_chip(dev, &need_post);
|
|
|
|
if (need_post)
|
|
ast_post_gpu(dev);
|
|
|
|
if (ast->chip != AST1180) {
|
|
ret = ast_get_dram_info(dev);
|
|
if (ret)
|
|
goto out_free;
|
|
ast->vram_size = ast_get_vram_info(dev);
|
|
DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n",
|
|
ast->mclk, ast->dram_type,
|
|
ast->dram_bus_width, ast->vram_size);
|
|
}
|
|
|
|
ret = ast_mm_init(ast);
|
|
if (ret)
|
|
goto out_free;
|
|
|
|
drm_mode_config_init(dev);
|
|
|
|
dev->mode_config.funcs = (void *)&ast_mode_funcs;
|
|
dev->mode_config.min_width = 0;
|
|
dev->mode_config.min_height = 0;
|
|
dev->mode_config.preferred_depth = 24;
|
|
dev->mode_config.prefer_shadow = 1;
|
|
dev->mode_config.fb_base = pci_resource_start(ast->dev->pdev, 0);
|
|
|
|
if (ast->chip == AST2100 ||
|
|
ast->chip == AST2200 ||
|
|
ast->chip == AST2300 ||
|
|
ast->chip == AST2400 ||
|
|
ast->chip == AST2500 ||
|
|
ast->chip == AST1180) {
|
|
dev->mode_config.max_width = 1920;
|
|
dev->mode_config.max_height = 2048;
|
|
} else {
|
|
dev->mode_config.max_width = 1600;
|
|
dev->mode_config.max_height = 1200;
|
|
}
|
|
|
|
ret = ast_mode_init(dev);
|
|
if (ret)
|
|
goto out_free;
|
|
|
|
ret = ast_fbdev_init(dev);
|
|
if (ret)
|
|
goto out_free;
|
|
|
|
return 0;
|
|
out_free:
|
|
kfree(ast);
|
|
dev->dev_private = NULL;
|
|
return ret;
|
|
}
|
|
|
|
void ast_driver_unload(struct drm_device *dev)
|
|
{
|
|
struct ast_private *ast = dev->dev_private;
|
|
|
|
ast_release_firmware(dev);
|
|
kfree(ast->dp501_fw_addr);
|
|
ast_mode_fini(dev);
|
|
ast_fbdev_fini(dev);
|
|
drm_mode_config_cleanup(dev);
|
|
|
|
ast_mm_fini(ast);
|
|
pci_iounmap(dev->pdev, ast->ioregs);
|
|
pci_iounmap(dev->pdev, ast->regs);
|
|
kfree(ast);
|
|
}
|
|
|
|
int ast_gem_create(struct drm_device *dev,
|
|
u32 size, bool iskernel,
|
|
struct drm_gem_object **obj)
|
|
{
|
|
struct ast_bo *astbo;
|
|
int ret;
|
|
|
|
*obj = NULL;
|
|
|
|
size = roundup(size, PAGE_SIZE);
|
|
if (size == 0)
|
|
return -EINVAL;
|
|
|
|
ret = ast_bo_create(dev, size, 0, 0, &astbo);
|
|
if (ret) {
|
|
if (ret != -ERESTARTSYS)
|
|
DRM_ERROR("failed to allocate GEM object\n");
|
|
return ret;
|
|
}
|
|
*obj = &astbo->gem;
|
|
return 0;
|
|
}
|
|
|
|
int ast_dumb_create(struct drm_file *file,
|
|
struct drm_device *dev,
|
|
struct drm_mode_create_dumb *args)
|
|
{
|
|
int ret;
|
|
struct drm_gem_object *gobj;
|
|
u32 handle;
|
|
|
|
args->pitch = args->width * ((args->bpp + 7) / 8);
|
|
args->size = args->pitch * args->height;
|
|
|
|
ret = ast_gem_create(dev, args->size, false,
|
|
&gobj);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = drm_gem_handle_create(file, gobj, &handle);
|
|
drm_gem_object_put_unlocked(gobj);
|
|
if (ret)
|
|
return ret;
|
|
|
|
args->handle = handle;
|
|
return 0;
|
|
}
|
|
|
|
static void ast_bo_unref(struct ast_bo **bo)
|
|
{
|
|
struct ttm_buffer_object *tbo;
|
|
|
|
if ((*bo) == NULL)
|
|
return;
|
|
|
|
tbo = &((*bo)->bo);
|
|
ttm_bo_unref(&tbo);
|
|
*bo = NULL;
|
|
}
|
|
|
|
void ast_gem_free_object(struct drm_gem_object *obj)
|
|
{
|
|
struct ast_bo *ast_bo = gem_to_ast_bo(obj);
|
|
|
|
ast_bo_unref(&ast_bo);
|
|
}
|
|
|
|
|
|
static inline u64 ast_bo_mmap_offset(struct ast_bo *bo)
|
|
{
|
|
return drm_vma_node_offset_addr(&bo->bo.vma_node);
|
|
}
|
|
int
|
|
ast_dumb_mmap_offset(struct drm_file *file,
|
|
struct drm_device *dev,
|
|
uint32_t handle,
|
|
uint64_t *offset)
|
|
{
|
|
struct drm_gem_object *obj;
|
|
struct ast_bo *bo;
|
|
|
|
obj = drm_gem_object_lookup(file, handle);
|
|
if (obj == NULL)
|
|
return -ENOENT;
|
|
|
|
bo = gem_to_ast_bo(obj);
|
|
*offset = ast_bo_mmap_offset(bo);
|
|
|
|
drm_gem_object_put_unlocked(obj);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|