399 lines
11 KiB
C
399 lines
11 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "smumgr.h"
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#include "rv_inc.h"
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#include "pp_soc15.h"
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#include "rv_smumgr.h"
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#include "ppatomctrl.h"
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#include "rv_ppsmc.h"
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#include "smu10_driver_if.h"
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#include "smu10.h"
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#include "ppatomctrl.h"
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#include "pp_debug.h"
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#include "smu_ucode_xfer_vi.h"
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#include "smu7_smumgr.h"
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#define VOLTAGE_SCALE 4
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#define BUFFER_SIZE 80000
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#define MAX_STRING_SIZE 15
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#define BUFFER_SIZETWO 131072
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#define MP0_Public 0x03800000
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#define MP0_SRAM 0x03900000
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#define MP1_Public 0x03b00000
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#define MP1_SRAM 0x03c00004
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#define smnMP1_FIRMWARE_FLAGS 0x3010028
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bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr)
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{
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uint32_t mp1_fw_flags, reg;
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reg = soc15_get_register_offset(NBIF_HWID, 0,
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mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
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cgs_write_register(hwmgr->device, reg,
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(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
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reg = soc15_get_register_offset(NBIF_HWID, 0,
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mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
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mp1_fw_flags = cgs_read_register(hwmgr->device, reg);
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if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
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return true;
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return false;
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}
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static uint32_t rv_wait_for_response(struct pp_hwmgr *hwmgr)
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{
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uint32_t reg;
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if (!rv_is_smc_ram_running(hwmgr))
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return -EINVAL;
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reg = soc15_get_register_offset(MP1_HWID, 0,
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mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
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phm_wait_for_register_unequal(hwmgr, reg,
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0, MP1_C2PMSG_90__CONTENT_MASK);
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return cgs_read_register(hwmgr->device, reg);
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}
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int rv_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
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uint16_t msg)
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{
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uint32_t reg;
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if (!rv_is_smc_ram_running(hwmgr))
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return -EINVAL;
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reg = soc15_get_register_offset(MP1_HWID, 0,
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mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
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cgs_write_register(hwmgr->device, reg, msg);
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return 0;
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}
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int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg)
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{
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uint32_t reg;
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reg = soc15_get_register_offset(MP1_HWID, 0,
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mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
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*arg = cgs_read_register(hwmgr->device, reg);
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return 0;
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}
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int rv_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
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{
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uint32_t reg;
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rv_wait_for_response(hwmgr);
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reg = soc15_get_register_offset(MP1_HWID, 0,
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mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
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cgs_write_register(hwmgr->device, reg, 0);
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rv_send_msg_to_smc_without_waiting(hwmgr, msg);
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if (rv_wait_for_response(hwmgr) == 0)
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printk("Failed to send Message %x.\n", msg);
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return 0;
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}
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int rv_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
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uint16_t msg, uint32_t parameter)
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{
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uint32_t reg;
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rv_wait_for_response(hwmgr);
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reg = soc15_get_register_offset(MP1_HWID, 0,
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mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
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cgs_write_register(hwmgr->device, reg, 0);
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reg = soc15_get_register_offset(MP1_HWID, 0,
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mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
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cgs_write_register(hwmgr->device, reg, parameter);
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rv_send_msg_to_smc_without_waiting(hwmgr, msg);
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if (rv_wait_for_response(hwmgr) == 0)
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printk("Failed to send Message %x.\n", msg);
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return 0;
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}
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int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id)
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{
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struct rv_smumgr *priv =
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(struct rv_smumgr *)(hwmgr->smu_backend);
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PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
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"Invalid SMU Table ID!", return -EINVAL;);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
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"Invalid SMU Table version!", return -EINVAL;);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
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"Invalid SMU Table Length!", return -EINVAL;);
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PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrHigh,
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priv->smu_tables.entry[table_id].table_addr_high) == 0,
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"[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;);
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PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrLow,
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priv->smu_tables.entry[table_id].table_addr_low) == 0,
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"[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
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return -EINVAL;);
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PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_TransferTableSmu2Dram,
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priv->smu_tables.entry[table_id].table_id) == 0,
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"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
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return -EINVAL;);
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memcpy(table, priv->smu_tables.entry[table_id].table,
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priv->smu_tables.entry[table_id].size);
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return 0;
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}
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int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id)
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{
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struct rv_smumgr *priv =
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(struct rv_smumgr *)(hwmgr->smu_backend);
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PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
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"Invalid SMU Table ID!", return -EINVAL;);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
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"Invalid SMU Table version!", return -EINVAL;);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
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"Invalid SMU Table Length!", return -EINVAL;);
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memcpy(priv->smu_tables.entry[table_id].table, table,
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priv->smu_tables.entry[table_id].size);
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PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrHigh,
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priv->smu_tables.entry[table_id].table_addr_high) == 0,
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"[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
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return -EINVAL;);
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PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrLow,
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priv->smu_tables.entry[table_id].table_addr_low) == 0,
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"[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
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return -EINVAL;);
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PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_TransferTableDram2Smu,
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priv->smu_tables.entry[table_id].table_id) == 0,
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"[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
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return -EINVAL;);
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return 0;
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}
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static int rv_verify_smc_interface(struct pp_hwmgr *hwmgr)
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{
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uint32_t smc_driver_if_version;
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PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr,
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PPSMC_MSG_GetDriverIfVersion),
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"Attempt to get SMC IF Version Number Failed!",
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return -EINVAL);
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PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
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&smc_driver_if_version),
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"Attempt to read SMC IF Version Number Failed!",
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return -EINVAL);
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if (smc_driver_if_version != SMU10_DRIVER_IF_VERSION)
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return -EINVAL;
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return 0;
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}
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/* sdma is disabled by default in vbios, need to re-enable in driver */
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static int rv_smc_enable_sdma(struct pp_hwmgr *hwmgr)
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{
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PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr,
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PPSMC_MSG_PowerUpSdma),
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"Attempt to power up sdma Failed!",
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return -EINVAL);
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return 0;
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}
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static int rv_smc_disable_sdma(struct pp_hwmgr *hwmgr)
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{
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PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr,
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PPSMC_MSG_PowerDownSdma),
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"Attempt to power down sdma Failed!",
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return -EINVAL);
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return 0;
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}
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/* vcn is disabled by default in vbios, need to re-enable in driver */
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static int rv_smc_enable_vcn(struct pp_hwmgr *hwmgr)
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{
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PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_PowerUpVcn, 0),
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"Attempt to power up vcn Failed!",
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return -EINVAL);
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return 0;
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}
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static int rv_smc_disable_vcn(struct pp_hwmgr *hwmgr)
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{
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PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_PowerDownVcn, 0),
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"Attempt to power down vcn Failed!",
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return -EINVAL);
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return 0;
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}
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static int rv_smu_fini(struct pp_hwmgr *hwmgr)
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{
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struct rv_smumgr *priv =
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(struct rv_smumgr *)(hwmgr->smu_backend);
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if (priv) {
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rv_smc_disable_sdma(hwmgr);
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rv_smc_disable_vcn(hwmgr);
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cgs_free_gpu_mem(hwmgr->device,
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priv->smu_tables.entry[WMTABLE].handle);
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cgs_free_gpu_mem(hwmgr->device,
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priv->smu_tables.entry[CLOCKTABLE].handle);
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kfree(hwmgr->smu_backend);
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hwmgr->smu_backend = NULL;
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}
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return 0;
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}
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static int rv_start_smu(struct pp_hwmgr *hwmgr)
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{
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if (rv_verify_smc_interface(hwmgr))
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return -EINVAL;
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if (rv_smc_enable_sdma(hwmgr))
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return -EINVAL;
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if (rv_smc_enable_vcn(hwmgr))
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return -EINVAL;
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return 0;
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}
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static int rv_smu_init(struct pp_hwmgr *hwmgr)
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{
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struct rv_smumgr *priv;
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uint64_t mc_addr;
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void *kaddr = NULL;
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unsigned long handle;
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priv = kzalloc(sizeof(struct rv_smumgr), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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hwmgr->smu_backend = priv;
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/* allocate space for watermarks table */
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smu_allocate_memory(hwmgr->device,
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sizeof(Watermarks_t),
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CGS_GPU_MEM_TYPE__GART_CACHEABLE,
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PAGE_SIZE,
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&mc_addr,
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&kaddr,
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&handle);
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PP_ASSERT_WITH_CODE(kaddr,
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"[rv_smu_init] Out of memory for wmtable.",
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kfree(hwmgr->smu_backend);
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hwmgr->smu_backend = NULL;
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return -EINVAL);
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priv->smu_tables.entry[WMTABLE].version = 0x01;
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priv->smu_tables.entry[WMTABLE].size = sizeof(Watermarks_t);
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priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;
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priv->smu_tables.entry[WMTABLE].table_addr_high =
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smu_upper_32_bits(mc_addr);
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priv->smu_tables.entry[WMTABLE].table_addr_low =
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smu_lower_32_bits(mc_addr);
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priv->smu_tables.entry[WMTABLE].table = kaddr;
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priv->smu_tables.entry[WMTABLE].handle = handle;
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/* allocate space for watermarks table */
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smu_allocate_memory(hwmgr->device,
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sizeof(DpmClocks_t),
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CGS_GPU_MEM_TYPE__GART_CACHEABLE,
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PAGE_SIZE,
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&mc_addr,
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&kaddr,
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&handle);
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PP_ASSERT_WITH_CODE(kaddr,
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"[rv_smu_init] Out of memory for CLOCKTABLE.",
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cgs_free_gpu_mem(hwmgr->device,
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(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
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kfree(hwmgr->smu_backend);
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hwmgr->smu_backend = NULL;
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return -EINVAL);
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priv->smu_tables.entry[CLOCKTABLE].version = 0x01;
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priv->smu_tables.entry[CLOCKTABLE].size = sizeof(DpmClocks_t);
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priv->smu_tables.entry[CLOCKTABLE].table_id = TABLE_DPMCLOCKS;
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priv->smu_tables.entry[CLOCKTABLE].table_addr_high =
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smu_upper_32_bits(mc_addr);
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priv->smu_tables.entry[CLOCKTABLE].table_addr_low =
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smu_lower_32_bits(mc_addr);
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priv->smu_tables.entry[CLOCKTABLE].table = kaddr;
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priv->smu_tables.entry[CLOCKTABLE].handle = handle;
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return 0;
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}
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const struct pp_smumgr_func rv_smu_funcs = {
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.smu_init = &rv_smu_init,
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.smu_fini = &rv_smu_fini,
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.start_smu = &rv_start_smu,
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.request_smu_load_specific_fw = NULL,
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.send_msg_to_smc = &rv_send_msg_to_smc,
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.send_msg_to_smc_with_parameter = &rv_send_msg_to_smc_with_parameter,
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.download_pptable_settings = NULL,
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.upload_pptable_settings = NULL,
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};
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