859 lines
24 KiB
C
859 lines
24 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/delay.h>
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#include <linux/gfp.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include "cgs_common.h"
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#include "smu/smu_8_0_d.h"
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#include "smu/smu_8_0_sh_mask.h"
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#include "smu8.h"
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#include "smu8_fusion.h"
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#include "cz_smumgr.h"
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#include "cz_ppsmc.h"
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#include "smu_ucode_xfer_cz.h"
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#include "gca/gfx_8_0_d.h"
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#include "gca/gfx_8_0_sh_mask.h"
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#include "smumgr.h"
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#define SIZE_ALIGN_32(x) (((x) + 31) / 32 * 32)
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static const enum cz_scratch_entry firmware_list[] = {
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CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
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CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
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CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
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};
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static int cz_smum_get_argument(struct pp_hwmgr *hwmgr)
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{
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if (hwmgr == NULL || hwmgr->device == NULL)
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return -EINVAL;
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return cgs_read_register(hwmgr->device,
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mmSMU_MP1_SRBM2P_ARG_0);
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}
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static int cz_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg)
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{
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int result = 0;
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if (hwmgr == NULL || hwmgr->device == NULL)
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return -EINVAL;
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result = PHM_WAIT_FIELD_UNEQUAL(hwmgr,
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SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
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if (result != 0) {
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pr_err("cz_send_msg_to_smc_async (0x%04x) failed\n", msg);
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return result;
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}
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cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0);
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cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg);
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return 0;
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}
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/* Send a message to the SMC, and wait for its response.*/
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static int cz_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
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{
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int result = 0;
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result = cz_send_msg_to_smc_async(hwmgr, msg);
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if (result != 0)
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return result;
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return PHM_WAIT_FIELD_UNEQUAL(hwmgr,
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SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
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}
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static int cz_set_smc_sram_address(struct pp_hwmgr *hwmgr,
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uint32_t smc_address, uint32_t limit)
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{
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if (hwmgr == NULL || hwmgr->device == NULL)
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return -EINVAL;
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if (0 != (3 & smc_address)) {
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pr_err("SMC address must be 4 byte aligned\n");
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return -EINVAL;
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}
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if (limit <= (smc_address + 3)) {
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pr_err("SMC address beyond the SMC RAM area\n");
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return -EINVAL;
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}
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cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX_0,
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SMN_MP1_SRAM_START_ADDR + smc_address);
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return 0;
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}
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static int cz_write_smc_sram_dword(struct pp_hwmgr *hwmgr,
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uint32_t smc_address, uint32_t value, uint32_t limit)
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{
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int result;
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if (hwmgr == NULL || hwmgr->device == NULL)
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return -EINVAL;
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result = cz_set_smc_sram_address(hwmgr, smc_address, limit);
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if (!result)
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cgs_write_register(hwmgr->device, mmMP0PUB_IND_DATA_0, value);
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return result;
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}
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static int cz_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
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uint16_t msg, uint32_t parameter)
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{
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if (hwmgr == NULL || hwmgr->device == NULL)
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return -EINVAL;
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cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
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return cz_send_msg_to_smc(hwmgr, msg);
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}
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static int cz_check_fw_load_finish(struct pp_hwmgr *hwmgr,
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uint32_t firmware)
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{
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int i;
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uint32_t index = SMN_MP1_SRAM_START_ADDR +
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SMU8_FIRMWARE_HEADER_LOCATION +
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offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
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if (hwmgr == NULL || hwmgr->device == NULL)
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return -EINVAL;
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cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
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for (i = 0; i < hwmgr->usec_timeout; i++) {
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if (firmware ==
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(cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA) & firmware))
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break;
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udelay(1);
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}
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if (i >= hwmgr->usec_timeout) {
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pr_err("SMU check loaded firmware failed.\n");
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return -EINVAL;
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}
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return 0;
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}
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static int cz_load_mec_firmware(struct pp_hwmgr *hwmgr)
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{
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uint32_t reg_data;
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uint32_t tmp;
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int ret = 0;
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struct cgs_firmware_info info = {0};
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struct cz_smumgr *cz_smu;
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if (hwmgr == NULL || hwmgr->device == NULL)
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return -EINVAL;
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cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
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ret = cgs_get_firmware_info(hwmgr->device,
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CGS_UCODE_ID_CP_MEC, &info);
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if (ret)
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return -EINVAL;
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/* Disable MEC parsing/prefetching */
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tmp = cgs_read_register(hwmgr->device,
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mmCP_MEC_CNTL);
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tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
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tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
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cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp);
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tmp = cgs_read_register(hwmgr->device,
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mmCP_CPC_IC_BASE_CNTL);
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tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
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tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
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tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
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tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
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cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);
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reg_data = smu_lower_32_bits(info.mc_addr) &
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PHM_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO);
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cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data);
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reg_data = smu_upper_32_bits(info.mc_addr) &
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PHM_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI);
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cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data);
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return 0;
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}
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static uint8_t cz_translate_firmware_enum_to_arg(struct pp_hwmgr *hwmgr,
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enum cz_scratch_entry firmware_enum)
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{
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uint8_t ret = 0;
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switch (firmware_enum) {
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case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0:
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ret = UCODE_ID_SDMA0;
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break;
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case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1:
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if (hwmgr->chip_id == CHIP_STONEY)
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ret = UCODE_ID_SDMA0;
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else
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ret = UCODE_ID_SDMA1;
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break;
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case CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE:
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ret = UCODE_ID_CP_CE;
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break;
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case CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP:
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ret = UCODE_ID_CP_PFP;
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break;
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case CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME:
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ret = UCODE_ID_CP_ME;
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break;
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case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1:
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ret = UCODE_ID_CP_MEC_JT1;
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break;
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case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2:
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if (hwmgr->chip_id == CHIP_STONEY)
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ret = UCODE_ID_CP_MEC_JT1;
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else
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ret = UCODE_ID_CP_MEC_JT2;
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break;
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case CZ_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG:
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ret = UCODE_ID_GMCON_RENG;
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break;
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case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G:
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ret = UCODE_ID_RLC_G;
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break;
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case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH:
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ret = UCODE_ID_RLC_SCRATCH;
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break;
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case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM:
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ret = UCODE_ID_RLC_SRM_ARAM;
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break;
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case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM:
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ret = UCODE_ID_RLC_SRM_DRAM;
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break;
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case CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM:
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ret = UCODE_ID_DMCU_ERAM;
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break;
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case CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM:
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ret = UCODE_ID_DMCU_IRAM;
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break;
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case CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING:
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ret = TASK_ARG_INIT_MM_PWR_LOG;
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break;
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case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_HALT:
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case CZ_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING:
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case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS:
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case CZ_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT:
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case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_START:
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case CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS:
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ret = TASK_ARG_REG_MMIO;
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break;
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case CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE:
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ret = TASK_ARG_INIT_CLK_TABLE;
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break;
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}
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return ret;
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}
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static enum cgs_ucode_id cz_convert_fw_type_to_cgs(uint32_t fw_type)
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{
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enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
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switch (fw_type) {
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case UCODE_ID_SDMA0:
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result = CGS_UCODE_ID_SDMA0;
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break;
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case UCODE_ID_SDMA1:
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result = CGS_UCODE_ID_SDMA1;
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break;
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case UCODE_ID_CP_CE:
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result = CGS_UCODE_ID_CP_CE;
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break;
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case UCODE_ID_CP_PFP:
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result = CGS_UCODE_ID_CP_PFP;
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break;
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case UCODE_ID_CP_ME:
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result = CGS_UCODE_ID_CP_ME;
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break;
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case UCODE_ID_CP_MEC_JT1:
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result = CGS_UCODE_ID_CP_MEC_JT1;
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break;
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case UCODE_ID_CP_MEC_JT2:
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result = CGS_UCODE_ID_CP_MEC_JT2;
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break;
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case UCODE_ID_RLC_G:
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result = CGS_UCODE_ID_RLC_G;
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break;
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default:
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break;
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}
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return result;
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}
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static int cz_smu_populate_single_scratch_task(
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struct pp_hwmgr *hwmgr,
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enum cz_scratch_entry fw_enum,
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uint8_t type, bool is_last)
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{
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uint8_t i;
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struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
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struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
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struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
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task->type = type;
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task->arg = cz_translate_firmware_enum_to_arg(hwmgr, fw_enum);
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task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
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for (i = 0; i < cz_smu->scratch_buffer_length; i++)
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if (cz_smu->scratch_buffer[i].firmware_ID == fw_enum)
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break;
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if (i >= cz_smu->scratch_buffer_length) {
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pr_err("Invalid Firmware Type\n");
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return -EINVAL;
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}
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task->addr.low = cz_smu->scratch_buffer[i].mc_addr_low;
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task->addr.high = cz_smu->scratch_buffer[i].mc_addr_high;
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task->size_bytes = cz_smu->scratch_buffer[i].data_size;
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if (CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS == fw_enum) {
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struct cz_ih_meta_data *pIHReg_restore =
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(struct cz_ih_meta_data *)cz_smu->scratch_buffer[i].kaddr;
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pIHReg_restore->command =
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METADATA_CMD_MODE0 | METADATA_PERFORM_ON_LOAD;
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}
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return 0;
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}
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static int cz_smu_populate_single_ucode_load_task(
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struct pp_hwmgr *hwmgr,
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enum cz_scratch_entry fw_enum,
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bool is_last)
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{
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uint8_t i;
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struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
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struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
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struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
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task->type = TASK_TYPE_UCODE_LOAD;
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task->arg = cz_translate_firmware_enum_to_arg(hwmgr, fw_enum);
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task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
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for (i = 0; i < cz_smu->driver_buffer_length; i++)
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if (cz_smu->driver_buffer[i].firmware_ID == fw_enum)
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break;
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if (i >= cz_smu->driver_buffer_length) {
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pr_err("Invalid Firmware Type\n");
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return -EINVAL;
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}
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task->addr.low = cz_smu->driver_buffer[i].mc_addr_low;
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task->addr.high = cz_smu->driver_buffer[i].mc_addr_high;
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task->size_bytes = cz_smu->driver_buffer[i].data_size;
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return 0;
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}
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static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_hwmgr *hwmgr)
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{
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struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
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cz_smu->toc_entry_aram = cz_smu->toc_entry_used_count;
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cz_smu_populate_single_scratch_task(hwmgr,
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CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
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TASK_TYPE_UCODE_SAVE, true);
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return 0;
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}
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static int cz_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr)
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{
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int i;
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struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
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struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
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for (i = 0; i < NUM_JOBLIST_ENTRIES; i++)
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toc->JobList[i] = (uint8_t)IGNORE_JOB;
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return 0;
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}
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static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_hwmgr *hwmgr)
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{
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struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
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struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
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toc->JobList[JOB_GFX_SAVE] = (uint8_t)cz_smu->toc_entry_used_count;
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cz_smu_populate_single_scratch_task(hwmgr,
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CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
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TASK_TYPE_UCODE_SAVE, false);
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cz_smu_populate_single_scratch_task(hwmgr,
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CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
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TASK_TYPE_UCODE_SAVE, true);
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return 0;
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}
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static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_hwmgr *hwmgr)
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{
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struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
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struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
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|
|
|
toc->JobList[JOB_GFX_RESTORE] = (uint8_t)cz_smu->toc_entry_used_count;
|
|
|
|
cz_smu_populate_single_ucode_load_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
|
|
cz_smu_populate_single_ucode_load_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
|
|
cz_smu_populate_single_ucode_load_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
|
|
cz_smu_populate_single_ucode_load_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
|
|
|
|
if (hwmgr->chip_id == CHIP_STONEY)
|
|
cz_smu_populate_single_ucode_load_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
|
|
else
|
|
cz_smu_populate_single_ucode_load_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
|
|
|
|
cz_smu_populate_single_ucode_load_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
|
|
|
|
/* populate scratch */
|
|
cz_smu_populate_single_scratch_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
|
|
TASK_TYPE_UCODE_LOAD, false);
|
|
|
|
cz_smu_populate_single_scratch_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
|
|
TASK_TYPE_UCODE_LOAD, false);
|
|
|
|
cz_smu_populate_single_scratch_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
|
|
TASK_TYPE_UCODE_LOAD, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_smu_construct_toc_for_power_profiling(struct pp_hwmgr *hwmgr)
|
|
{
|
|
struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
|
|
|
|
cz_smu->toc_entry_power_profiling_index = cz_smu->toc_entry_used_count;
|
|
|
|
cz_smu_populate_single_scratch_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
|
|
TASK_TYPE_INITIALIZE, true);
|
|
return 0;
|
|
}
|
|
|
|
static int cz_smu_construct_toc_for_bootup(struct pp_hwmgr *hwmgr)
|
|
{
|
|
struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
|
|
|
|
cz_smu->toc_entry_initialize_index = cz_smu->toc_entry_used_count;
|
|
|
|
cz_smu_populate_single_ucode_load_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
|
|
if (hwmgr->chip_id != CHIP_STONEY)
|
|
cz_smu_populate_single_ucode_load_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
|
|
cz_smu_populate_single_ucode_load_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
|
|
cz_smu_populate_single_ucode_load_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
|
|
cz_smu_populate_single_ucode_load_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
|
|
cz_smu_populate_single_ucode_load_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
|
|
if (hwmgr->chip_id != CHIP_STONEY)
|
|
cz_smu_populate_single_ucode_load_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
|
|
cz_smu_populate_single_ucode_load_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_smu_construct_toc_for_clock_table(struct pp_hwmgr *hwmgr)
|
|
{
|
|
struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
|
|
|
|
cz_smu->toc_entry_clock_table = cz_smu->toc_entry_used_count;
|
|
|
|
cz_smu_populate_single_scratch_task(hwmgr,
|
|
CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
|
|
TASK_TYPE_INITIALIZE, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_smu_construct_toc(struct pp_hwmgr *hwmgr)
|
|
{
|
|
struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
|
|
|
|
cz_smu->toc_entry_used_count = 0;
|
|
cz_smu_initialize_toc_empty_job_list(hwmgr);
|
|
cz_smu_construct_toc_for_rlc_aram_save(hwmgr);
|
|
cz_smu_construct_toc_for_vddgfx_enter(hwmgr);
|
|
cz_smu_construct_toc_for_vddgfx_exit(hwmgr);
|
|
cz_smu_construct_toc_for_power_profiling(hwmgr);
|
|
cz_smu_construct_toc_for_bootup(hwmgr);
|
|
cz_smu_construct_toc_for_clock_table(hwmgr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_smu_populate_firmware_entries(struct pp_hwmgr *hwmgr)
|
|
{
|
|
struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
|
|
uint32_t firmware_type;
|
|
uint32_t i;
|
|
int ret;
|
|
enum cgs_ucode_id ucode_id;
|
|
struct cgs_firmware_info info = {0};
|
|
|
|
cz_smu->driver_buffer_length = 0;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(firmware_list); i++) {
|
|
|
|
firmware_type = cz_translate_firmware_enum_to_arg(hwmgr,
|
|
firmware_list[i]);
|
|
|
|
ucode_id = cz_convert_fw_type_to_cgs(firmware_type);
|
|
|
|
ret = cgs_get_firmware_info(hwmgr->device,
|
|
ucode_id, &info);
|
|
|
|
if (ret == 0) {
|
|
cz_smu->driver_buffer[i].mc_addr_high =
|
|
smu_upper_32_bits(info.mc_addr);
|
|
|
|
cz_smu->driver_buffer[i].mc_addr_low =
|
|
smu_lower_32_bits(info.mc_addr);
|
|
|
|
cz_smu->driver_buffer[i].data_size = info.image_size;
|
|
|
|
cz_smu->driver_buffer[i].firmware_ID = firmware_list[i];
|
|
cz_smu->driver_buffer_length++;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_smu_populate_single_scratch_entry(
|
|
struct pp_hwmgr *hwmgr,
|
|
enum cz_scratch_entry scratch_type,
|
|
uint32_t ulsize_byte,
|
|
struct cz_buffer_entry *entry)
|
|
{
|
|
struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
|
|
long long mc_addr =
|
|
((long long)(cz_smu->smu_buffer.mc_addr_high) << 32)
|
|
| cz_smu->smu_buffer.mc_addr_low;
|
|
|
|
uint32_t ulsize_aligned = SIZE_ALIGN_32(ulsize_byte);
|
|
|
|
mc_addr += cz_smu->smu_buffer_used_bytes;
|
|
|
|
entry->data_size = ulsize_byte;
|
|
entry->kaddr = (char *) cz_smu->smu_buffer.kaddr +
|
|
cz_smu->smu_buffer_used_bytes;
|
|
entry->mc_addr_low = smu_lower_32_bits(mc_addr);
|
|
entry->mc_addr_high = smu_upper_32_bits(mc_addr);
|
|
entry->firmware_ID = scratch_type;
|
|
|
|
cz_smu->smu_buffer_used_bytes += ulsize_aligned;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table)
|
|
{
|
|
struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
|
|
unsigned long i;
|
|
|
|
for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
|
|
if (cz_smu->scratch_buffer[i].firmware_ID
|
|
== CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE)
|
|
break;
|
|
}
|
|
|
|
*table = (struct SMU8_Fusion_ClkTable *)cz_smu->scratch_buffer[i].kaddr;
|
|
|
|
cz_send_msg_to_smc_with_parameter(hwmgr,
|
|
PPSMC_MSG_SetClkTableAddrHi,
|
|
cz_smu->scratch_buffer[i].mc_addr_high);
|
|
|
|
cz_send_msg_to_smc_with_parameter(hwmgr,
|
|
PPSMC_MSG_SetClkTableAddrLo,
|
|
cz_smu->scratch_buffer[i].mc_addr_low);
|
|
|
|
cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
|
|
cz_smu->toc_entry_clock_table);
|
|
|
|
cz_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToDram);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_upload_pptable_settings(struct pp_hwmgr *hwmgr)
|
|
{
|
|
struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
|
|
unsigned long i;
|
|
|
|
for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
|
|
if (cz_smu->scratch_buffer[i].firmware_ID
|
|
== CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE)
|
|
break;
|
|
}
|
|
|
|
cz_send_msg_to_smc_with_parameter(hwmgr,
|
|
PPSMC_MSG_SetClkTableAddrHi,
|
|
cz_smu->scratch_buffer[i].mc_addr_high);
|
|
|
|
cz_send_msg_to_smc_with_parameter(hwmgr,
|
|
PPSMC_MSG_SetClkTableAddrLo,
|
|
cz_smu->scratch_buffer[i].mc_addr_low);
|
|
|
|
cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
|
|
cz_smu->toc_entry_clock_table);
|
|
|
|
cz_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToSmu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_request_smu_load_fw(struct pp_hwmgr *hwmgr)
|
|
{
|
|
struct cz_smumgr *cz_smu = (struct cz_smumgr *)(hwmgr->smu_backend);
|
|
uint32_t smc_address;
|
|
|
|
if (!hwmgr->reload_fw) {
|
|
pr_info("skip reloading...\n");
|
|
return 0;
|
|
}
|
|
|
|
cz_smu_populate_firmware_entries(hwmgr);
|
|
|
|
cz_smu_construct_toc(hwmgr);
|
|
|
|
smc_address = SMU8_FIRMWARE_HEADER_LOCATION +
|
|
offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
|
|
|
|
cz_write_smc_sram_dword(hwmgr, smc_address, 0, smc_address+4);
|
|
|
|
cz_send_msg_to_smc_with_parameter(hwmgr,
|
|
PPSMC_MSG_DriverDramAddrHi,
|
|
cz_smu->toc_buffer.mc_addr_high);
|
|
|
|
cz_send_msg_to_smc_with_parameter(hwmgr,
|
|
PPSMC_MSG_DriverDramAddrLo,
|
|
cz_smu->toc_buffer.mc_addr_low);
|
|
|
|
cz_send_msg_to_smc(hwmgr, PPSMC_MSG_InitJobs);
|
|
|
|
cz_send_msg_to_smc_with_parameter(hwmgr,
|
|
PPSMC_MSG_ExecuteJob,
|
|
cz_smu->toc_entry_aram);
|
|
cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
|
|
cz_smu->toc_entry_power_profiling_index);
|
|
|
|
return cz_send_msg_to_smc_with_parameter(hwmgr,
|
|
PPSMC_MSG_ExecuteJob,
|
|
cz_smu->toc_entry_initialize_index);
|
|
}
|
|
|
|
static int cz_start_smu(struct pp_hwmgr *hwmgr)
|
|
{
|
|
int ret = 0;
|
|
uint32_t fw_to_check = 0;
|
|
|
|
fw_to_check = UCODE_ID_RLC_G_MASK |
|
|
UCODE_ID_SDMA0_MASK |
|
|
UCODE_ID_SDMA1_MASK |
|
|
UCODE_ID_CP_CE_MASK |
|
|
UCODE_ID_CP_ME_MASK |
|
|
UCODE_ID_CP_PFP_MASK |
|
|
UCODE_ID_CP_MEC_JT1_MASK |
|
|
UCODE_ID_CP_MEC_JT2_MASK;
|
|
|
|
if (hwmgr->chip_id == CHIP_STONEY)
|
|
fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
|
|
|
|
ret = cz_request_smu_load_fw(hwmgr);
|
|
if (ret)
|
|
pr_err("SMU firmware load failed\n");
|
|
|
|
cz_check_fw_load_finish(hwmgr, fw_to_check);
|
|
|
|
ret = cz_load_mec_firmware(hwmgr);
|
|
if (ret)
|
|
pr_err("Mec Firmware load failed\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int cz_smu_init(struct pp_hwmgr *hwmgr)
|
|
{
|
|
uint64_t mc_addr = 0;
|
|
int ret = 0;
|
|
struct cz_smumgr *cz_smu;
|
|
|
|
cz_smu = kzalloc(sizeof(struct cz_smumgr), GFP_KERNEL);
|
|
if (cz_smu == NULL)
|
|
return -ENOMEM;
|
|
|
|
hwmgr->smu_backend = cz_smu;
|
|
|
|
cz_smu->toc_buffer.data_size = 4096;
|
|
cz_smu->smu_buffer.data_size =
|
|
ALIGN(UCODE_ID_RLC_SCRATCH_SIZE_BYTE, 32) +
|
|
ALIGN(UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE, 32) +
|
|
ALIGN(UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE, 32) +
|
|
ALIGN(sizeof(struct SMU8_MultimediaPowerLogData), 32) +
|
|
ALIGN(sizeof(struct SMU8_Fusion_ClkTable), 32);
|
|
|
|
ret = smu_allocate_memory(hwmgr->device,
|
|
cz_smu->toc_buffer.data_size,
|
|
CGS_GPU_MEM_TYPE__GART_CACHEABLE,
|
|
PAGE_SIZE,
|
|
&mc_addr,
|
|
&cz_smu->toc_buffer.kaddr,
|
|
&cz_smu->toc_buffer.handle);
|
|
if (ret != 0)
|
|
return -1;
|
|
|
|
cz_smu->toc_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
|
|
cz_smu->toc_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
|
|
|
|
ret = smu_allocate_memory(hwmgr->device,
|
|
cz_smu->smu_buffer.data_size,
|
|
CGS_GPU_MEM_TYPE__GART_CACHEABLE,
|
|
PAGE_SIZE,
|
|
&mc_addr,
|
|
&cz_smu->smu_buffer.kaddr,
|
|
&cz_smu->smu_buffer.handle);
|
|
if (ret != 0)
|
|
return -1;
|
|
|
|
cz_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
|
|
cz_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
|
|
|
|
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
|
|
UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
|
|
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
|
|
pr_err("Error when Populate Firmware Entry.\n");
|
|
return -1;
|
|
}
|
|
|
|
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
|
|
UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
|
|
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
|
|
pr_err("Error when Populate Firmware Entry.\n");
|
|
return -1;
|
|
}
|
|
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
|
|
UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
|
|
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
|
|
pr_err("Error when Populate Firmware Entry.\n");
|
|
return -1;
|
|
}
|
|
|
|
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
|
|
CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
|
|
sizeof(struct SMU8_MultimediaPowerLogData),
|
|
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
|
|
pr_err("Error when Populate Firmware Entry.\n");
|
|
return -1;
|
|
}
|
|
|
|
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
|
|
CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
|
|
sizeof(struct SMU8_Fusion_ClkTable),
|
|
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
|
|
pr_err("Error when Populate Firmware Entry.\n");
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_smu_fini(struct pp_hwmgr *hwmgr)
|
|
{
|
|
struct cz_smumgr *cz_smu;
|
|
|
|
if (hwmgr == NULL || hwmgr->device == NULL)
|
|
return -EINVAL;
|
|
|
|
cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
|
|
if (cz_smu) {
|
|
cgs_free_gpu_mem(hwmgr->device,
|
|
cz_smu->toc_buffer.handle);
|
|
cgs_free_gpu_mem(hwmgr->device,
|
|
cz_smu->smu_buffer.handle);
|
|
kfree(cz_smu);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
const struct pp_smumgr_func cz_smu_funcs = {
|
|
.smu_init = cz_smu_init,
|
|
.smu_fini = cz_smu_fini,
|
|
.start_smu = cz_start_smu,
|
|
.check_fw_load_finish = cz_check_fw_load_finish,
|
|
.request_smu_load_fw = NULL,
|
|
.request_smu_load_specific_fw = NULL,
|
|
.get_argument = cz_smum_get_argument,
|
|
.send_msg_to_smc = cz_send_msg_to_smc,
|
|
.send_msg_to_smc_with_parameter = cz_send_msg_to_smc_with_parameter,
|
|
.download_pptable_settings = cz_download_pptable_settings,
|
|
.upload_pptable_settings = cz_upload_pptable_settings,
|
|
};
|
|
|