688 lines
19 KiB
C
688 lines
19 KiB
C
/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU72_H
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#define SMU72_H
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#if !defined(SMC_MICROCODE)
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#pragma pack(push, 1)
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#endif
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#define SMU__NUM_SCLK_DPM_STATE 8
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#define SMU__NUM_MCLK_DPM_LEVELS 4
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#define SMU__NUM_LCLK_DPM_LEVELS 8
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#define SMU__NUM_PCIE_DPM_LEVELS 8
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enum SID_OPTION {
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SID_OPTION_HI,
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SID_OPTION_LO,
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SID_OPTION_COUNT
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};
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enum Poly3rdOrderCoeff {
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LEAKAGE_TEMPERATURE_SCALAR,
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LEAKAGE_VOLTAGE_SCALAR,
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DYNAMIC_VOLTAGE_SCALAR,
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POLY_3RD_ORDER_COUNT
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};
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struct SMU7_Poly3rdOrder_Data {
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int32_t a;
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int32_t b;
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int32_t c;
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int32_t d;
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uint8_t a_shift;
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uint8_t b_shift;
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uint8_t c_shift;
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uint8_t x_shift;
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};
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typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data;
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struct Power_Calculator_Data {
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uint16_t NoLoadVoltage;
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uint16_t LoadVoltage;
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uint16_t Resistance;
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uint16_t Temperature;
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uint16_t BaseLeakage;
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uint16_t LkgTempScalar;
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uint16_t LkgVoltScalar;
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uint16_t LkgAreaScalar;
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uint16_t LkgPower;
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uint16_t DynVoltScalar;
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uint32_t Cac;
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uint32_t DynPower;
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uint32_t TotalCurrent;
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uint32_t TotalPower;
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};
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typedef struct Power_Calculator_Data PowerCalculatorData_t;
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struct Gc_Cac_Weight_Data {
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uint8_t index;
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uint32_t value;
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};
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typedef struct Gc_Cac_Weight_Data GcCacWeight_Data;
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typedef struct {
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uint32_t high;
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uint32_t low;
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} data_64_t;
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typedef struct {
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data_64_t high;
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data_64_t low;
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} data_128_t;
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#define SMU7_CONTEXT_ID_SMC 1
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#define SMU7_CONTEXT_ID_VBIOS 2
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#define SMU72_MAX_LEVELS_VDDC 16
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#define SMU72_MAX_LEVELS_VDDGFX 16
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#define SMU72_MAX_LEVELS_VDDCI 8
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#define SMU72_MAX_LEVELS_MVDD 4
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#define SMU_MAX_SMIO_LEVELS 4
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#define SMU72_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
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#define SMU72_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS /* MCLK Levels DPM */
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#define SMU72_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS /* LCLK Levels */
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#define SMU72_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes. */
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#define SMU72_MAX_LEVELS_UVD 8 /* VCLK/DCLK levels for UVD. */
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#define SMU72_MAX_LEVELS_VCE 8 /* ECLK levels for VCE. */
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#define SMU72_MAX_LEVELS_ACP 8 /* ACLK levels for ACP. */
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#define SMU72_MAX_LEVELS_SAMU 8 /* SAMCLK levels for SAMU. */
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#define SMU72_MAX_ENTRIES_SMIO 32 /* Number of entries in SMIO table. */
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#define DPM_NO_LIMIT 0
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#define DPM_NO_UP 1
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#define DPM_GO_DOWN 2
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#define DPM_GO_UP 3
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#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
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#define SMU7_FIRST_DPM_MEMORY_LEVEL 0
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#define GPIO_CLAMP_MODE_VRHOT 1
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#define GPIO_CLAMP_MODE_THERM 2
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#define GPIO_CLAMP_MODE_DC 4
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#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
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#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
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#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
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#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
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#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6
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#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
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#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9
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#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
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#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12
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#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
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#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15
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#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
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#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18
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#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
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#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21
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#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
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#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
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#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
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#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
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#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
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/* Virtualization Defines */
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#define CG_XDMA_MASK 0x1
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#define CG_XDMA_SHIFT 0
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#define CG_UVD_MASK 0x2
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#define CG_UVD_SHIFT 1
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#define CG_VCE_MASK 0x4
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#define CG_VCE_SHIFT 2
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#define CG_SAMU_MASK 0x8
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#define CG_SAMU_SHIFT 3
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#define CG_GFX_MASK 0x10
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#define CG_GFX_SHIFT 4
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#define CG_SDMA_MASK 0x20
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#define CG_SDMA_SHIFT 5
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#define CG_HDP_MASK 0x40
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#define CG_HDP_SHIFT 6
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#define CG_MC_MASK 0x80
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#define CG_MC_SHIFT 7
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#define CG_DRM_MASK 0x100
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#define CG_DRM_SHIFT 8
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#define CG_ROM_MASK 0x200
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#define CG_ROM_SHIFT 9
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#define CG_BIF_MASK 0x400
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#define CG_BIF_SHIFT 10
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#define SMU72_DTE_ITERATIONS 5
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#define SMU72_DTE_SOURCES 3
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#define SMU72_DTE_SINKS 1
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#define SMU72_NUM_CPU_TES 0
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#define SMU72_NUM_GPU_TES 1
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#define SMU72_NUM_NON_TES 2
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#define SMU72_DTE_FAN_SCALAR_MIN 0x100
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#define SMU72_DTE_FAN_SCALAR_MAX 0x166
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#define SMU72_DTE_FAN_TEMP_MAX 93
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#define SMU72_DTE_FAN_TEMP_MIN 83
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#if defined SMU__FUSION_ONLY
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#define SMU7_DTE_ITERATIONS 5
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#define SMU7_DTE_SOURCES 5
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#define SMU7_DTE_SINKS 3
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#define SMU7_NUM_CPU_TES 2
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#define SMU7_NUM_GPU_TES 1
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#define SMU7_NUM_NON_TES 2
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#endif
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struct SMU7_HystController_Data {
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uint8_t waterfall_up;
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uint8_t waterfall_down;
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uint8_t waterfall_limit;
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uint8_t spare;
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uint16_t release_cnt;
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uint16_t release_limit;
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};
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typedef struct SMU7_HystController_Data SMU7_HystController_Data;
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struct SMU72_PIDController {
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uint32_t Ki;
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int32_t LFWindupUpperLim;
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int32_t LFWindupLowerLim;
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uint32_t StatePrecision;
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uint32_t LfPrecision;
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uint32_t LfOffset;
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uint32_t MaxState;
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uint32_t MaxLfFraction;
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uint32_t StateShift;
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};
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typedef struct SMU72_PIDController SMU72_PIDController;
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struct SMU7_LocalDpmScoreboard {
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uint32_t PercentageBusy;
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int32_t PIDError;
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int32_t PIDIntegral;
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int32_t PIDOutput;
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uint32_t SigmaDeltaAccum;
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uint32_t SigmaDeltaOutput;
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uint32_t SigmaDeltaLevel;
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uint32_t UtilizationSetpoint;
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uint8_t TdpClampMode;
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uint8_t TdcClampMode;
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uint8_t ThermClampMode;
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uint8_t VoltageBusy;
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int8_t CurrLevel;
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int8_t TargLevel;
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uint8_t LevelChangeInProgress;
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uint8_t UpHyst;
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uint8_t DownHyst;
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uint8_t VoltageDownHyst;
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uint8_t DpmEnable;
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uint8_t DpmRunning;
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uint8_t DpmForce;
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uint8_t DpmForceLevel;
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uint8_t DisplayWatermark;
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uint8_t McArbIndex;
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uint32_t MinimumPerfSclk;
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uint8_t AcpiReq;
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uint8_t AcpiAck;
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uint8_t GfxClkSlow;
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uint8_t GpioClampMode; /* bit0 = VRHOT: bit1 = THERM: bit2 = DC */
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uint8_t FpsFilterWeight;
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uint8_t EnabledLevelsChange;
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uint8_t DteClampMode;
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uint8_t FpsClampMode;
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uint16_t LevelResidencyCounters[SMU72_MAX_LEVELS_GRAPHICS];
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uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_GRAPHICS];
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void (*TargetStateCalculator)(uint8_t);
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void (*SavedTargetStateCalculator)(uint8_t);
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uint16_t AutoDpmInterval;
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uint16_t AutoDpmRange;
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uint8_t FpsEnabled;
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uint8_t MaxPerfLevel;
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uint8_t AllowLowClkInterruptToHost;
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uint8_t FpsRunning;
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uint32_t MaxAllowedFrequency;
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uint32_t FilteredSclkFrequency;
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uint32_t LastSclkFrequency;
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uint32_t FilteredSclkFrequencyCnt;
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};
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typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
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#define SMU7_MAX_VOLTAGE_CLIENTS 12
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typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
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struct SMU_VoltageLevel {
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uint8_t Vddc;
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uint8_t Vddci;
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uint8_t VddGfx;
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uint8_t Phases;
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};
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typedef struct SMU_VoltageLevel SMU_VoltageLevel;
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struct SMU7_VoltageScoreboard {
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SMU_VoltageLevel CurrentVoltage;
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SMU_VoltageLevel TargetVoltage;
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uint16_t MaxVid;
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uint8_t HighestVidOffset;
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uint8_t CurrentVidOffset;
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uint8_t ControllerBusy;
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uint8_t CurrentVid;
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uint8_t CurrentVddciVid;
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uint8_t VddGfxShutdown; /* 0 = normal mode, 1 = shut down */
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SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
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uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
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uint8_t TargetIndex;
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uint8_t Delay;
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uint8_t ControllerEnable;
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uint8_t ControllerRunning;
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uint16_t CurrentStdVoltageHiSidd;
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uint16_t CurrentStdVoltageLoSidd;
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uint8_t OverrideVoltage;
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uint8_t VddcUseUlvOffset;
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uint8_t VddGfxUseUlvOffset;
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uint8_t padding;
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VoltageChangeHandler_t ChangeVddc;
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VoltageChangeHandler_t ChangeVddGfx;
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VoltageChangeHandler_t ChangeVddci;
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VoltageChangeHandler_t ChangePhase;
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VoltageChangeHandler_t ChangeMvdd;
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VoltageChangeHandler_t functionLinks[6];
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uint8_t *VddcFollower1;
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uint8_t *VddcFollower2;
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int16_t Driver_OD_RequestedVidOffset1;
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int16_t Driver_OD_RequestedVidOffset2;
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};
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typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
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#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
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struct SMU7_PCIeLinkSpeedScoreboard {
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uint8_t DpmEnable;
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uint8_t DpmRunning;
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uint8_t DpmForce;
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uint8_t DpmForceLevel;
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uint8_t CurrentLinkSpeed;
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uint8_t EnabledLevelsChange;
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uint16_t AutoDpmInterval;
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uint16_t AutoDpmRange;
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uint16_t AutoDpmCount;
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uint8_t DpmMode;
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uint8_t AcpiReq;
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uint8_t AcpiAck;
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uint8_t CurrentLinkLevel;
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};
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typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
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/* -------------------------------------------------------- CAC table ------------------------------------------------------ */
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#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
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#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
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#define SMU7_SCALE_I 7
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#define SMU7_SCALE_R 12
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struct SMU7_PowerScoreboard {
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PowerCalculatorData_t VddGfxPowerData[SID_OPTION_COUNT];
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PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT];
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uint32_t TotalGpuPower;
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uint32_t TdcCurrent;
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uint16_t VddciTotalPower;
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uint16_t sparesasfsdfd;
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uint16_t Vddr1Power;
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uint16_t RocPower;
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uint16_t CalcMeasPowerBlend;
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uint8_t SidOptionPower;
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uint8_t SidOptionCurrent;
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uint32_t WinTime;
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uint16_t Telemetry_1_slope;
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uint16_t Telemetry_2_slope;
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int32_t Telemetry_1_offset;
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int32_t Telemetry_2_offset;
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uint32_t VddcCurrentTelemetry;
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uint32_t VddGfxCurrentTelemetry;
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uint32_t VddcPowerTelemetry;
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uint32_t VddGfxPowerTelemetry;
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uint32_t VddciPowerTelemetry;
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uint32_t VddcPower;
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uint32_t VddGfxPower;
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uint32_t VddciPower;
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uint32_t TelemetryCurrent[2];
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uint32_t TelemetryVoltage[2];
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uint32_t TelemetryPower[2];
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};
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typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
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struct SMU7_ThermalScoreboard {
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int16_t GpuLimit;
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int16_t GpuHyst;
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uint16_t CurrGnbTemp;
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uint16_t FilteredGnbTemp;
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uint8_t ControllerEnable;
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uint8_t ControllerRunning;
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uint8_t AutoTmonCalInterval;
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uint8_t AutoTmonCalEnable;
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uint8_t ThermalDpmEnabled;
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uint8_t SclkEnabledMask;
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uint8_t spare[2];
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int32_t temperature_gradient;
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SMU7_HystController_Data HystControllerData;
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int32_t WeightedSensorTemperature;
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uint16_t TemperatureLimit[SMU72_MAX_LEVELS_GRAPHICS];
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uint32_t Alpha;
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};
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typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
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/* For FeatureEnables: */
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#define SMU7_SCLK_DPM_CONFIG_MASK 0x01
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#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
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#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
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#define SMU7_MCLK_DPM_CONFIG_MASK 0x08
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#define SMU7_UVD_DPM_CONFIG_MASK 0x10
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#define SMU7_VCE_DPM_CONFIG_MASK 0x20
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#define SMU7_ACP_DPM_CONFIG_MASK 0x40
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#define SMU7_SAMU_DPM_CONFIG_MASK 0x80
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#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
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#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
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#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
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#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
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#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
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#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
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#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
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/* All 'soft registers' should be uint32_t. */
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struct SMU72_SoftRegisters {
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uint32_t RefClockFrequency;
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uint32_t PmTimerPeriod;
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uint32_t FeatureEnables;
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uint32_t PreVBlankGap;
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uint32_t VBlankTimeout;
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uint32_t TrainTimeGap;
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uint32_t MvddSwitchTime;
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uint32_t LongestAcpiTrainTime;
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uint32_t AcpiDelay;
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uint32_t G5TrainTime;
|
|
uint32_t DelayMpllPwron;
|
|
uint32_t VoltageChangeTimeout;
|
|
|
|
uint32_t HandshakeDisables;
|
|
|
|
uint8_t DisplayPhy1Config;
|
|
uint8_t DisplayPhy2Config;
|
|
uint8_t DisplayPhy3Config;
|
|
uint8_t DisplayPhy4Config;
|
|
|
|
uint8_t DisplayPhy5Config;
|
|
uint8_t DisplayPhy6Config;
|
|
uint8_t DisplayPhy7Config;
|
|
uint8_t DisplayPhy8Config;
|
|
|
|
uint32_t AverageGraphicsActivity;
|
|
uint32_t AverageMemoryActivity;
|
|
uint32_t AverageGioActivity;
|
|
|
|
uint8_t SClkDpmEnabledLevels;
|
|
uint8_t MClkDpmEnabledLevels;
|
|
uint8_t LClkDpmEnabledLevels;
|
|
uint8_t PCIeDpmEnabledLevels;
|
|
|
|
uint8_t UVDDpmEnabledLevels;
|
|
uint8_t SAMUDpmEnabledLevels;
|
|
uint8_t ACPDpmEnabledLevels;
|
|
uint8_t VCEDpmEnabledLevels;
|
|
|
|
uint32_t DRAM_LOG_ADDR_H;
|
|
uint32_t DRAM_LOG_ADDR_L;
|
|
uint32_t DRAM_LOG_PHY_ADDR_H;
|
|
uint32_t DRAM_LOG_PHY_ADDR_L;
|
|
uint32_t DRAM_LOG_BUFF_SIZE;
|
|
uint32_t UlvEnterCount;
|
|
uint32_t UlvTime;
|
|
uint32_t UcodeLoadStatus;
|
|
uint32_t Reserved[2];
|
|
|
|
};
|
|
|
|
typedef struct SMU72_SoftRegisters SMU72_SoftRegisters;
|
|
|
|
struct SMU72_Firmware_Header {
|
|
uint32_t Digest[5];
|
|
uint32_t Version;
|
|
uint32_t HeaderSize;
|
|
uint32_t Flags;
|
|
uint32_t EntryPoint;
|
|
uint32_t CodeSize;
|
|
uint32_t ImageSize;
|
|
|
|
uint32_t Rtos;
|
|
uint32_t SoftRegisters;
|
|
uint32_t DpmTable;
|
|
uint32_t FanTable;
|
|
uint32_t CacConfigTable;
|
|
uint32_t CacStatusTable;
|
|
uint32_t mcRegisterTable;
|
|
uint32_t mcArbDramTimingTable;
|
|
uint32_t PmFuseTable;
|
|
uint32_t Globals;
|
|
uint32_t ClockStretcherTable;
|
|
uint32_t Reserved[41];
|
|
uint32_t Signature;
|
|
};
|
|
|
|
typedef struct SMU72_Firmware_Header SMU72_Firmware_Header;
|
|
|
|
#define SMU72_FIRMWARE_HEADER_LOCATION 0x20000
|
|
|
|
enum DisplayConfig {
|
|
PowerDown = 1,
|
|
DP54x4,
|
|
DP54x2,
|
|
DP54x1,
|
|
DP27x4,
|
|
DP27x2,
|
|
DP27x1,
|
|
HDMI297,
|
|
HDMI162,
|
|
LVDS,
|
|
DP324x4,
|
|
DP324x2,
|
|
DP324x1
|
|
};
|
|
|
|
#define MC_BLOCK_COUNT 1
|
|
#define CPL_BLOCK_COUNT 5
|
|
#define SE_BLOCK_COUNT 15
|
|
#define GC_BLOCK_COUNT 24
|
|
|
|
struct SMU7_Local_Cac {
|
|
uint8_t BlockId;
|
|
uint8_t SignalId;
|
|
uint8_t Threshold;
|
|
uint8_t Padding;
|
|
};
|
|
|
|
typedef struct SMU7_Local_Cac SMU7_Local_Cac;
|
|
|
|
struct SMU7_Local_Cac_Table {
|
|
SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
|
|
SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
|
|
SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
|
|
SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
|
|
};
|
|
|
|
typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
|
|
|
|
#if !defined(SMC_MICROCODE)
|
|
#pragma pack(pop)
|
|
#endif
|
|
|
|
/* Description of Clock Gating bitmask for Tonga: */
|
|
/* System Clock Gating */
|
|
#define CG_SYS_BITMASK_FIRST_BIT 0 /* First bit of Sys CG bitmask */
|
|
#define CG_SYS_BITMASK_LAST_BIT 9 /* Last bit of Sys CG bitmask */
|
|
#define CG_SYS_BIF_MGLS_SHIFT 0
|
|
#define CG_SYS_ROM_SHIFT 1
|
|
#define CG_SYS_MC_MGCG_SHIFT 2
|
|
#define CG_SYS_MC_MGLS_SHIFT 3
|
|
#define CG_SYS_SDMA_MGCG_SHIFT 4
|
|
#define CG_SYS_SDMA_MGLS_SHIFT 5
|
|
#define CG_SYS_DRM_MGCG_SHIFT 6
|
|
#define CG_SYS_HDP_MGCG_SHIFT 7
|
|
#define CG_SYS_HDP_MGLS_SHIFT 8
|
|
#define CG_SYS_DRM_MGLS_SHIFT 9
|
|
|
|
#define CG_SYS_BIF_MGLS_MASK 0x1
|
|
#define CG_SYS_ROM_MASK 0x2
|
|
#define CG_SYS_MC_MGCG_MASK 0x4
|
|
#define CG_SYS_MC_MGLS_MASK 0x8
|
|
#define CG_SYS_SDMA_MGCG_MASK 0x10
|
|
#define CG_SYS_SDMA_MGLS_MASK 0x20
|
|
#define CG_SYS_DRM_MGCG_MASK 0x40
|
|
#define CG_SYS_HDP_MGCG_MASK 0x80
|
|
#define CG_SYS_HDP_MGLS_MASK 0x100
|
|
#define CG_SYS_DRM_MGLS_MASK 0x200
|
|
|
|
/* Graphics Clock Gating */
|
|
#define CG_GFX_BITMASK_FIRST_BIT 16 /* First bit of Gfx CG bitmask */
|
|
#define CG_GFX_BITMASK_LAST_BIT 20 /* Last bit of Gfx CG bitmask */
|
|
#define CG_GFX_CGCG_SHIFT 16
|
|
#define CG_GFX_CGLS_SHIFT 17
|
|
#define CG_CPF_MGCG_SHIFT 18
|
|
#define CG_RLC_MGCG_SHIFT 19
|
|
#define CG_GFX_OTHERS_MGCG_SHIFT 20
|
|
|
|
#define CG_GFX_CGCG_MASK 0x00010000
|
|
#define CG_GFX_CGLS_MASK 0x00020000
|
|
#define CG_CPF_MGCG_MASK 0x00040000
|
|
#define CG_RLC_MGCG_MASK 0x00080000
|
|
#define CG_GFX_OTHERS_MGCG_MASK 0x00100000
|
|
|
|
/* Voltage Regulator Configuration */
|
|
/* VR Config info is contained in dpmTable.VRConfig */
|
|
|
|
#define VRCONF_VDDC_MASK 0x000000FF
|
|
#define VRCONF_VDDC_SHIFT 0
|
|
#define VRCONF_VDDGFX_MASK 0x0000FF00
|
|
#define VRCONF_VDDGFX_SHIFT 8
|
|
#define VRCONF_VDDCI_MASK 0x00FF0000
|
|
#define VRCONF_VDDCI_SHIFT 16
|
|
#define VRCONF_MVDD_MASK 0xFF000000
|
|
#define VRCONF_MVDD_SHIFT 24
|
|
|
|
#define VR_MERGED_WITH_VDDC 0
|
|
#define VR_SVI2_PLANE_1 1
|
|
#define VR_SVI2_PLANE_2 2
|
|
#define VR_SMIO_PATTERN_1 3
|
|
#define VR_SMIO_PATTERN_2 4
|
|
#define VR_STATIC_VOLTAGE 5
|
|
|
|
/* Clock Stretcher Configuration */
|
|
|
|
#define CLOCK_STRETCHER_MAX_ENTRIES 0x4
|
|
#define CKS_LOOKUPTable_MAX_ENTRIES 0x4
|
|
|
|
/* The 'settings' field is subdivided in the following way: */
|
|
#define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01
|
|
#define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0
|
|
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E
|
|
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
|
|
#define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80
|
|
#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7
|
|
|
|
struct SMU_ClockStretcherDataTableEntry {
|
|
uint8_t minVID;
|
|
uint8_t maxVID;
|
|
|
|
uint16_t setting;
|
|
};
|
|
typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
|
|
|
|
struct SMU_ClockStretcherDataTable {
|
|
SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
|
|
};
|
|
typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
|
|
|
|
struct SMU_CKS_LOOKUPTableEntry {
|
|
uint16_t minFreq;
|
|
uint16_t maxFreq;
|
|
|
|
uint8_t setting;
|
|
uint8_t padding[3];
|
|
};
|
|
typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
|
|
|
|
struct SMU_CKS_LOOKUPTable {
|
|
SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
|
|
};
|
|
typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
|
|
|
|
#endif
|
|
|
|
|