83 lines
2.9 KiB
C
83 lines
2.9 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _VEGA10_POWERTUNE_H_
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#define _VEGA10_POWERTUNE_H_
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enum vega10_pt_config_reg_type {
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VEGA10_CONFIGREG_MMR = 0,
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VEGA10_CONFIGREG_SMC_IND,
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VEGA10_CONFIGREG_DIDT_IND,
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VEGA10_CONFIGREG_CACHE,
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VEGA10_CONFIGREG_MAX
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};
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enum vega10_didt_config_reg_type {
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VEGA10_CONFIGREG_DIDT = 0,
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VEGA10_CONFIGREG_GCCAC,
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VEGA10_CONFIGREG_SECAC
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};
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/* PowerContainment Features */
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#define POWERCONTAINMENT_FEATURE_DTE 0x00000001
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#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
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#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
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struct vega10_pt_config_reg {
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uint32_t offset;
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uint32_t mask;
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uint32_t shift;
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uint32_t value;
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enum vega10_pt_config_reg_type type;
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};
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struct vega10_didt_config_reg {
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uint32_t offset;
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uint32_t mask;
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uint32_t shift;
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uint32_t value;
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};
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struct vega10_pt_defaults {
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uint8_t SviLoadLineEn;
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uint8_t SviLoadLineVddC;
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uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
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uint8_t TDC_MAWt;
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uint8_t TdcWaterfallCtl;
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uint8_t DTEAmbientTempBase;
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};
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void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
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int vega10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
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int vega10_populate_pm_fuses(struct pp_hwmgr *hwmgr);
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int vega10_enable_smc_cac(struct pp_hwmgr *hwmgr);
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int vega10_enable_power_containment(struct pp_hwmgr *hwmgr);
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int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
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int vega10_power_control_set_level(struct pp_hwmgr *hwmgr);
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int vega10_disable_power_containment(struct pp_hwmgr *hwmgr);
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int vega10_enable_didt_config(struct pp_hwmgr *hwmgr);
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int vega10_disable_didt_config(struct pp_hwmgr *hwmgr);
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#endif /* _VEGA10_POWERTUNE_H_ */
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