297 lines
10 KiB
C
297 lines
10 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Author: Monk.liu@amd.com
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*/
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#ifndef AMDGPU_VIRT_H
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#define AMDGPU_VIRT_H
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#define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
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#define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */
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#define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */
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#define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
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#define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
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struct amdgpu_mm_table {
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struct amdgpu_bo *bo;
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uint32_t *cpu_addr;
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uint64_t gpu_addr;
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};
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#define AMDGPU_VF_ERROR_ENTRY_SIZE 16
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/* struct error_entry - amdgpu VF error information. */
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struct amdgpu_vf_error_buffer {
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struct mutex lock;
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int read_count;
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int write_count;
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uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
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uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
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uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
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};
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/**
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* struct amdgpu_virt_ops - amdgpu device virt operations
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*/
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struct amdgpu_virt_ops {
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int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
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int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
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int (*reset_gpu)(struct amdgpu_device *adev);
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void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
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};
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/*
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* Firmware Reserve Frame buffer
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*/
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struct amdgpu_virt_fw_reserve {
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struct amdgim_pf2vf_info_header *p_pf2vf;
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struct amdgim_vf2pf_info_header *p_vf2pf;
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unsigned int checksum_key;
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};
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/*
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* Defination between PF and VF
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* Structures forcibly aligned to 4 to keep the same style as PF.
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*/
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#define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024)
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#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
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(total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
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enum AMDGIM_FEATURE_FLAG {
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/* GIM supports feature of Error log collecting */
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AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
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/* GIM supports feature of loading uCodes */
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AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2,
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};
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struct amdgim_pf2vf_info_header {
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/* the total structure size in byte. */
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uint32_t size;
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/* version of this structure, written by the GIM */
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uint32_t version;
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} __aligned(4);
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struct amdgim_pf2vf_info_v1 {
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/* header contains size and version */
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struct amdgim_pf2vf_info_header header;
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/* max_width * max_height */
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unsigned int uvd_enc_max_pixels_count;
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/* 16x16 pixels/sec, codec independent */
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unsigned int uvd_enc_max_bandwidth;
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/* max_width * max_height */
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unsigned int vce_enc_max_pixels_count;
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/* 16x16 pixels/sec, codec independent */
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unsigned int vce_enc_max_bandwidth;
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/* MEC FW position in kb from the start of visible frame buffer */
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unsigned int mecfw_kboffset;
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/* The features flags of the GIM driver supports. */
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unsigned int feature_flags;
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/* use private key from mailbox 2 to create chueksum */
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unsigned int checksum;
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} __aligned(4);
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struct amdgim_pf2vf_info_v2 {
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/* header contains size and version */
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struct amdgim_pf2vf_info_header header;
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/* use private key from mailbox 2 to create chueksum */
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uint32_t checksum;
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/* The features flags of the GIM driver supports. */
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uint32_t feature_flags;
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/* max_width * max_height */
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uint32_t uvd_enc_max_pixels_count;
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/* 16x16 pixels/sec, codec independent */
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uint32_t uvd_enc_max_bandwidth;
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/* max_width * max_height */
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uint32_t vce_enc_max_pixels_count;
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/* 16x16 pixels/sec, codec independent */
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uint32_t vce_enc_max_bandwidth;
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/* MEC FW position in kb from the start of VF visible frame buffer */
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uint64_t mecfw_kboffset;
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/* MEC FW size in KB */
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uint32_t mecfw_ksize;
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/* UVD FW position in kb from the start of VF visible frame buffer */
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uint64_t uvdfw_kboffset;
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/* UVD FW size in KB */
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uint32_t uvdfw_ksize;
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/* VCE FW position in kb from the start of VF visible frame buffer */
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uint64_t vcefw_kboffset;
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/* VCE FW size in KB */
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uint32_t vcefw_ksize;
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uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (9 + sizeof(struct amdgim_pf2vf_info_header)/sizeof(uint32_t)), 3)];
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} __aligned(4);
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struct amdgim_vf2pf_info_header {
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/* the total structure size in byte. */
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uint32_t size;
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/*version of this structure, written by the guest */
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uint32_t version;
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} __aligned(4);
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struct amdgim_vf2pf_info_v1 {
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/* header contains size and version */
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struct amdgim_vf2pf_info_header header;
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/* driver version */
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char driver_version[64];
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/* driver certification, 1=WHQL, 0=None */
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unsigned int driver_cert;
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/* guest OS type and version: need a define */
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unsigned int os_info;
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/* in the unit of 1M */
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unsigned int fb_usage;
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/* guest gfx engine usage percentage */
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unsigned int gfx_usage;
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/* guest gfx engine health percentage */
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unsigned int gfx_health;
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/* guest compute engine usage percentage */
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unsigned int compute_usage;
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/* guest compute engine health percentage */
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unsigned int compute_health;
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/* guest vce engine usage percentage. 0xffff means N/A. */
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unsigned int vce_enc_usage;
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/* guest vce engine health percentage. 0xffff means N/A. */
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unsigned int vce_enc_health;
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/* guest uvd engine usage percentage. 0xffff means N/A. */
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unsigned int uvd_enc_usage;
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/* guest uvd engine usage percentage. 0xffff means N/A. */
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unsigned int uvd_enc_health;
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unsigned int checksum;
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} __aligned(4);
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struct amdgim_vf2pf_info_v2 {
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/* header contains size and version */
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struct amdgim_vf2pf_info_header header;
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uint32_t checksum;
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/* driver version */
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uint8_t driver_version[64];
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/* driver certification, 1=WHQL, 0=None */
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uint32_t driver_cert;
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/* guest OS type and version: need a define */
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uint32_t os_info;
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/* in the unit of 1M */
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uint32_t fb_usage;
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/* guest gfx engine usage percentage */
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uint32_t gfx_usage;
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/* guest gfx engine health percentage */
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uint32_t gfx_health;
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/* guest compute engine usage percentage */
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uint32_t compute_usage;
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/* guest compute engine health percentage */
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uint32_t compute_health;
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/* guest vce engine usage percentage. 0xffff means N/A. */
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uint32_t vce_enc_usage;
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/* guest vce engine health percentage. 0xffff means N/A. */
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uint32_t vce_enc_health;
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/* guest uvd engine usage percentage. 0xffff means N/A. */
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uint32_t uvd_enc_usage;
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/* guest uvd engine usage percentage. 0xffff means N/A. */
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uint32_t uvd_enc_health;
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uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amdgim_vf2pf_info_header)/sizeof(uint32_t)), 0)];
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} __aligned(4);
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#define AMDGPU_FW_VRAM_VF2PF_VER 2
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typedef struct amdgim_vf2pf_info_v2 amdgim_vf2pf_info ;
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#define AMDGPU_FW_VRAM_VF2PF_WRITE(adev, field, val) \
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do { \
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((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field = (val); \
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} while (0)
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#define AMDGPU_FW_VRAM_VF2PF_READ(adev, field, val) \
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do { \
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(*val) = ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field; \
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} while (0)
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#define AMDGPU_FW_VRAM_PF2VF_READ(adev, field, val) \
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do { \
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if (!adev->virt.fw_reserve.p_pf2vf) \
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*(val) = 0; \
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else { \
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if (adev->virt.fw_reserve.p_pf2vf->version == 1) \
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*(val) = ((struct amdgim_pf2vf_info_v1 *)adev->virt.fw_reserve.p_pf2vf)->field; \
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if (adev->virt.fw_reserve.p_pf2vf->version == 2) \
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*(val) = ((struct amdgim_pf2vf_info_v2 *)adev->virt.fw_reserve.p_pf2vf)->field; \
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} \
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} while (0)
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/* GPU virtualization */
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struct amdgpu_virt {
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uint32_t caps;
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struct amdgpu_bo *csa_obj;
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uint64_t csa_vmid0_addr;
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bool chained_ib_support;
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uint32_t reg_val_offs;
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struct mutex lock_reset;
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struct amdgpu_irq_src ack_irq;
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struct amdgpu_irq_src rcv_irq;
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struct work_struct flr_work;
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struct amdgpu_mm_table mm_table;
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const struct amdgpu_virt_ops *ops;
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struct amdgpu_vf_error_buffer vf_errors;
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struct amdgpu_virt_fw_reserve fw_reserve;
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};
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#define AMDGPU_CSA_SIZE (8 * 1024)
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#define AMDGPU_CSA_VADDR (AMDGPU_VA_RESERVED_SIZE - AMDGPU_CSA_SIZE)
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#define amdgpu_sriov_enabled(adev) \
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((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
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#define amdgpu_sriov_vf(adev) \
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((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
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#define amdgpu_sriov_bios(adev) \
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((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
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#define amdgpu_sriov_runtime(adev) \
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((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
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#define amdgpu_passthrough(adev) \
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((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
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static inline bool is_virtual_machine(void)
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{
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#ifdef CONFIG_X86
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return boot_cpu_has(X86_FEATURE_HYPERVISOR);
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#else
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return false;
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#endif
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}
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struct amdgpu_vm;
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int amdgpu_allocate_static_csa(struct amdgpu_device *adev);
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int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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struct amdgpu_bo_va **bo_va);
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void amdgpu_virt_init_setting(struct amdgpu_device *adev);
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uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
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void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
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int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
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int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
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int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
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int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job);
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int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
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void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
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int amdgpu_virt_fw_reserve_get_checksum(void *obj, unsigned long obj_size,
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unsigned int key,
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unsigned int chksum);
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void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
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#endif
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