764 lines
20 KiB
C
764 lines
20 KiB
C
/*
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* PowerNV cpuidle code
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*
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* Copyright 2015 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/device.h>
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#include <linux/cpu.h>
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#include <asm/firmware.h>
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#include <asm/machdep.h>
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#include <asm/opal.h>
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#include <asm/cputhreads.h>
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#include <asm/cpuidle.h>
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#include <asm/code-patching.h>
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#include <asm/smp.h>
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#include <asm/runlatch.h>
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#include "powernv.h"
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#include "subcore.h"
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/* Power ISA 3.0 allows for stop states 0x0 - 0xF */
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#define MAX_STOP_STATE 0xF
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#define P9_STOP_SPR_MSR 2000
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#define P9_STOP_SPR_PSSCR 855
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static u32 supported_cpuidle_states;
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/*
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* The default stop state that will be used by ppc_md.power_save
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* function on platforms that support stop instruction.
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*/
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static u64 pnv_default_stop_val;
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static u64 pnv_default_stop_mask;
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static bool default_stop_found;
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/*
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* First deep stop state. Used to figure out when to save/restore
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* hypervisor context.
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*/
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u64 pnv_first_deep_stop_state = MAX_STOP_STATE;
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/*
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* psscr value and mask of the deepest stop idle state.
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* Used when a cpu is offlined.
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*/
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static u64 pnv_deepest_stop_psscr_val;
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static u64 pnv_deepest_stop_psscr_mask;
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static u64 pnv_deepest_stop_flag;
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static bool deepest_stop_found;
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static int pnv_save_sprs_for_deep_states(void)
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{
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int cpu;
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int rc;
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/*
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* hid0, hid1, hid4, hid5, hmeer and lpcr values are symmetric across
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* all cpus at boot. Get these reg values of current cpu and use the
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* same across all cpus.
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*/
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uint64_t lpcr_val = mfspr(SPRN_LPCR);
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uint64_t hid0_val = mfspr(SPRN_HID0);
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uint64_t hid1_val = mfspr(SPRN_HID1);
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uint64_t hid4_val = mfspr(SPRN_HID4);
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uint64_t hid5_val = mfspr(SPRN_HID5);
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uint64_t hmeer_val = mfspr(SPRN_HMEER);
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uint64_t msr_val = MSR_IDLE;
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uint64_t psscr_val = pnv_deepest_stop_psscr_val;
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for_each_possible_cpu(cpu) {
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uint64_t pir = get_hard_smp_processor_id(cpu);
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uint64_t hsprg0_val = (uint64_t)&paca[cpu];
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rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val);
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if (rc != 0)
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return rc;
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if (cpu_has_feature(CPU_FTR_ARCH_300)) {
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rc = opal_slw_set_reg(pir, P9_STOP_SPR_MSR, msr_val);
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if (rc)
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return rc;
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rc = opal_slw_set_reg(pir,
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P9_STOP_SPR_PSSCR, psscr_val);
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if (rc)
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return rc;
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}
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/* HIDs are per core registers */
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if (cpu_thread_in_core(cpu) == 0) {
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rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val);
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if (rc != 0)
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return rc;
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/* Only p8 needs to set extra HID regiters */
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if (!cpu_has_feature(CPU_FTR_ARCH_300)) {
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rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val);
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if (rc != 0)
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return rc;
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}
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}
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}
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return 0;
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}
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static void pnv_alloc_idle_core_states(void)
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{
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int i, j;
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int nr_cores = cpu_nr_cores();
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u32 *core_idle_state;
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/*
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* core_idle_state - The lower 8 bits track the idle state of
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* each thread of the core.
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*
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* The most significant bit is the lock bit.
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*
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* Initially all the bits corresponding to threads_per_core
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* are set. They are cleared when the thread enters deep idle
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* state like sleep and winkle/stop.
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*
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* Initially the lock bit is cleared. The lock bit has 2
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* purposes:
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* a. While the first thread in the core waking up from
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* idle is restoring core state, it prevents other
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* threads in the core from switching to process
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* context.
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* b. While the last thread in the core is saving the
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* core state, it prevents a different thread from
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* waking up.
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*/
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for (i = 0; i < nr_cores; i++) {
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int first_cpu = i * threads_per_core;
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int node = cpu_to_node(first_cpu);
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size_t paca_ptr_array_size;
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core_idle_state = kmalloc_node(sizeof(u32), GFP_KERNEL, node);
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*core_idle_state = (1 << threads_per_core) - 1;
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paca_ptr_array_size = (threads_per_core *
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sizeof(struct paca_struct *));
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for (j = 0; j < threads_per_core; j++) {
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int cpu = first_cpu + j;
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paca[cpu].core_idle_state_ptr = core_idle_state;
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paca[cpu].thread_idle_state = PNV_THREAD_RUNNING;
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paca[cpu].thread_mask = 1 << j;
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if (!cpu_has_feature(CPU_FTR_POWER9_DD1))
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continue;
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paca[cpu].thread_sibling_pacas =
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kmalloc_node(paca_ptr_array_size,
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GFP_KERNEL, node);
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}
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}
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update_subcore_sibling_mask();
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if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT) {
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int rc = pnv_save_sprs_for_deep_states();
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if (likely(!rc))
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return;
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/*
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* The stop-api is unable to restore hypervisor
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* resources on wakeup from platform idle states which
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* lose full context. So disable such states.
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*/
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supported_cpuidle_states &= ~OPAL_PM_LOSE_FULL_CONTEXT;
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pr_warn("cpuidle-powernv: Disabling idle states that lose full context\n");
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pr_warn("cpuidle-powernv: Idle power-savings, CPU-Hotplug affected\n");
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if (cpu_has_feature(CPU_FTR_ARCH_300) &&
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(pnv_deepest_stop_flag & OPAL_PM_LOSE_FULL_CONTEXT)) {
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/*
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* Use the default stop state for CPU-Hotplug
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* if available.
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*/
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if (default_stop_found) {
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pnv_deepest_stop_psscr_val =
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pnv_default_stop_val;
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pnv_deepest_stop_psscr_mask =
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pnv_default_stop_mask;
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pr_warn("cpuidle-powernv: Offlined CPUs will stop with psscr = 0x%016llx\n",
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pnv_deepest_stop_psscr_val);
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} else { /* Fallback to snooze loop for CPU-Hotplug */
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deepest_stop_found = false;
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pr_warn("cpuidle-powernv: Offlined CPUs will busy wait\n");
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}
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}
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}
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}
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u32 pnv_get_supported_cpuidle_states(void)
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{
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return supported_cpuidle_states;
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}
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EXPORT_SYMBOL_GPL(pnv_get_supported_cpuidle_states);
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static void pnv_fastsleep_workaround_apply(void *info)
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{
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int rc;
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int *err = info;
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rc = opal_config_cpu_idle_state(OPAL_CONFIG_IDLE_FASTSLEEP,
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OPAL_CONFIG_IDLE_APPLY);
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if (rc)
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*err = 1;
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}
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/*
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* Used to store fastsleep workaround state
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* 0 - Workaround applied/undone at fastsleep entry/exit path (Default)
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* 1 - Workaround applied once, never undone.
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*/
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static u8 fastsleep_workaround_applyonce;
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static ssize_t show_fastsleep_workaround_applyonce(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return sprintf(buf, "%u\n", fastsleep_workaround_applyonce);
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}
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static ssize_t store_fastsleep_workaround_applyonce(struct device *dev,
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struct device_attribute *attr, const char *buf,
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size_t count)
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{
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cpumask_t primary_thread_mask;
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int err;
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u8 val;
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if (kstrtou8(buf, 0, &val) || val != 1)
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return -EINVAL;
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if (fastsleep_workaround_applyonce == 1)
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return count;
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/*
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* fastsleep_workaround_applyonce = 1 implies
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* fastsleep workaround needs to be left in 'applied' state on all
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* the cores. Do this by-
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* 1. Patching out the call to 'undo' workaround in fastsleep exit path
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* 2. Sending ipi to all the cores which have at least one online thread
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* 3. Patching out the call to 'apply' workaround in fastsleep entry
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* path
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* There is no need to send ipi to cores which have all threads
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* offlined, as last thread of the core entering fastsleep or deeper
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* state would have applied workaround.
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*/
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err = patch_instruction(
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(unsigned int *)pnv_fastsleep_workaround_at_exit,
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PPC_INST_NOP);
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if (err) {
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pr_err("fastsleep_workaround_applyonce change failed while patching pnv_fastsleep_workaround_at_exit");
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goto fail;
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}
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get_online_cpus();
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primary_thread_mask = cpu_online_cores_map();
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on_each_cpu_mask(&primary_thread_mask,
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pnv_fastsleep_workaround_apply,
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&err, 1);
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put_online_cpus();
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if (err) {
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pr_err("fastsleep_workaround_applyonce change failed while running pnv_fastsleep_workaround_apply");
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goto fail;
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}
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err = patch_instruction(
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(unsigned int *)pnv_fastsleep_workaround_at_entry,
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PPC_INST_NOP);
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if (err) {
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pr_err("fastsleep_workaround_applyonce change failed while patching pnv_fastsleep_workaround_at_entry");
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goto fail;
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}
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fastsleep_workaround_applyonce = 1;
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return count;
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fail:
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return -EIO;
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}
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static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600,
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show_fastsleep_workaround_applyonce,
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store_fastsleep_workaround_applyonce);
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static unsigned long __power7_idle_type(unsigned long type)
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{
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unsigned long srr1;
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if (!prep_irq_for_idle_irqsoff())
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return 0;
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__ppc64_runlatch_off();
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srr1 = power7_idle_insn(type);
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__ppc64_runlatch_on();
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fini_irq_for_idle_irqsoff();
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return srr1;
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}
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void power7_idle_type(unsigned long type)
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{
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unsigned long srr1;
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srr1 = __power7_idle_type(type);
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irq_set_pending_from_srr1(srr1);
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}
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void power7_idle(void)
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{
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if (!powersave_nap)
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return;
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power7_idle_type(PNV_THREAD_NAP);
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}
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static unsigned long __power9_idle_type(unsigned long stop_psscr_val,
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unsigned long stop_psscr_mask)
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{
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unsigned long psscr;
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unsigned long srr1;
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if (!prep_irq_for_idle_irqsoff())
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return 0;
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psscr = mfspr(SPRN_PSSCR);
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psscr = (psscr & ~stop_psscr_mask) | stop_psscr_val;
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__ppc64_runlatch_off();
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srr1 = power9_idle_stop(psscr);
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__ppc64_runlatch_on();
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fini_irq_for_idle_irqsoff();
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return srr1;
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}
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void power9_idle_type(unsigned long stop_psscr_val,
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unsigned long stop_psscr_mask)
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{
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unsigned long srr1;
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srr1 = __power9_idle_type(stop_psscr_val, stop_psscr_mask);
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irq_set_pending_from_srr1(srr1);
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}
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/*
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* Used for ppc_md.power_save which needs a function with no parameters
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*/
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void power9_idle(void)
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{
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power9_idle_type(pnv_default_stop_val, pnv_default_stop_mask);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static void pnv_program_cpu_hotplug_lpcr(unsigned int cpu, u64 lpcr_val)
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{
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u64 pir = get_hard_smp_processor_id(cpu);
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mtspr(SPRN_LPCR, lpcr_val);
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/*
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* Program the LPCR via stop-api only if the deepest stop state
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* can lose hypervisor context.
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*/
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if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT)
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opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val);
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}
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/*
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* pnv_cpu_offline: A function that puts the CPU into the deepest
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* available platform idle state on a CPU-Offline.
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* interrupts hard disabled and no lazy irq pending.
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*/
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unsigned long pnv_cpu_offline(unsigned int cpu)
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{
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unsigned long srr1;
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u32 idle_states = pnv_get_supported_cpuidle_states();
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u64 lpcr_val;
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/*
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* We don't want to take decrementer interrupts while we are
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* offline, so clear LPCR:PECE1. We keep PECE2 (and
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* LPCR_PECE_HVEE on P9) enabled as to let IPIs in.
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*
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* If the CPU gets woken up by a special wakeup, ensure that
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* the SLW engine sets LPCR with decrementer bit cleared, else
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* the CPU will come back to the kernel due to a spurious
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* wakeup.
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*/
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lpcr_val = mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1;
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pnv_program_cpu_hotplug_lpcr(cpu, lpcr_val);
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__ppc64_runlatch_off();
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if (cpu_has_feature(CPU_FTR_ARCH_300) && deepest_stop_found) {
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unsigned long psscr;
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psscr = mfspr(SPRN_PSSCR);
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psscr = (psscr & ~pnv_deepest_stop_psscr_mask) |
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pnv_deepest_stop_psscr_val;
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srr1 = power9_idle_stop(psscr);
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} else if ((idle_states & OPAL_PM_WINKLE_ENABLED) &&
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(idle_states & OPAL_PM_LOSE_FULL_CONTEXT)) {
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srr1 = power7_idle_insn(PNV_THREAD_WINKLE);
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} else if ((idle_states & OPAL_PM_SLEEP_ENABLED) ||
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(idle_states & OPAL_PM_SLEEP_ENABLED_ER1)) {
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srr1 = power7_idle_insn(PNV_THREAD_SLEEP);
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} else if (idle_states & OPAL_PM_NAP_ENABLED) {
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srr1 = power7_idle_insn(PNV_THREAD_NAP);
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} else {
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/* This is the fallback method. We emulate snooze */
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while (!generic_check_cpu_restart(cpu)) {
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HMT_low();
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HMT_very_low();
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}
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srr1 = 0;
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HMT_medium();
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}
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__ppc64_runlatch_on();
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/*
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* Re-enable decrementer interrupts in LPCR.
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*
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* Further, we want stop states to be woken up by decrementer
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* for non-hotplug cases. So program the LPCR via stop api as
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* well.
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*/
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lpcr_val = mfspr(SPRN_LPCR) | (u64)LPCR_PECE1;
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pnv_program_cpu_hotplug_lpcr(cpu, lpcr_val);
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return srr1;
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}
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#endif
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|
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/*
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* Power ISA 3.0 idle initialization.
|
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*
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* POWER ISA 3.0 defines a new SPR Processor stop Status and Control
|
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* Register (PSSCR) to control idle behavior.
|
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*
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* PSSCR layout:
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* ----------------------------------------------------------
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* | PLS | /// | SD | ESL | EC | PSLL | /// | TR | MTL | RL |
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* ----------------------------------------------------------
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* 0 4 41 42 43 44 48 54 56 60
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*
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* PSSCR key fields:
|
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* Bits 0:3 - Power-Saving Level Status (PLS). This field indicates the
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* lowest power-saving state the thread entered since stop instruction was
|
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* last executed.
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*
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* Bit 41 - Status Disable(SD)
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* 0 - Shows PLS entries
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* 1 - PLS entries are all 0
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*
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* Bit 42 - Enable State Loss
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* 0 - No state is lost irrespective of other fields
|
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* 1 - Allows state loss
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*
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* Bit 43 - Exit Criterion
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* 0 - Exit from power-save mode on any interrupt
|
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* 1 - Exit from power-save mode controlled by LPCR's PECE bits
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*
|
|
* Bits 44:47 - Power-Saving Level Limit
|
|
* This limits the power-saving level that can be entered into.
|
|
*
|
|
* Bits 60:63 - Requested Level
|
|
* Used to specify which power-saving level must be entered on executing
|
|
* stop instruction
|
|
*/
|
|
|
|
int validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags)
|
|
{
|
|
int err = 0;
|
|
|
|
/*
|
|
* psscr_mask == 0xf indicates an older firmware.
|
|
* Set remaining fields of psscr to the default values.
|
|
* See NOTE above definition of PSSCR_HV_DEFAULT_VAL
|
|
*/
|
|
if (*psscr_mask == 0xf) {
|
|
*psscr_val = *psscr_val | PSSCR_HV_DEFAULT_VAL;
|
|
*psscr_mask = PSSCR_HV_DEFAULT_MASK;
|
|
return err;
|
|
}
|
|
|
|
/*
|
|
* New firmware is expected to set the psscr_val bits correctly.
|
|
* Validate that the following invariants are correctly maintained by
|
|
* the new firmware.
|
|
* - ESL bit value matches the EC bit value.
|
|
* - ESL bit is set for all the deep stop states.
|
|
*/
|
|
if (GET_PSSCR_ESL(*psscr_val) != GET_PSSCR_EC(*psscr_val)) {
|
|
err = ERR_EC_ESL_MISMATCH;
|
|
} else if ((flags & OPAL_PM_LOSE_FULL_CONTEXT) &&
|
|
GET_PSSCR_ESL(*psscr_val) == 0) {
|
|
err = ERR_DEEP_STATE_ESL_MISMATCH;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
/*
|
|
* pnv_arch300_idle_init: Initializes the default idle state, first
|
|
* deep idle state and deepest idle state on
|
|
* ISA 3.0 CPUs.
|
|
*
|
|
* @np: /ibm,opal/power-mgt device node
|
|
* @flags: cpu-idle-state-flags array
|
|
* @dt_idle_states: Number of idle state entries
|
|
* Returns 0 on success
|
|
*/
|
|
static int __init pnv_power9_idle_init(struct device_node *np, u32 *flags,
|
|
int dt_idle_states)
|
|
{
|
|
u64 *psscr_val = NULL;
|
|
u64 *psscr_mask = NULL;
|
|
u32 *residency_ns = NULL;
|
|
u64 max_residency_ns = 0;
|
|
int rc = 0, i;
|
|
|
|
psscr_val = kcalloc(dt_idle_states, sizeof(*psscr_val), GFP_KERNEL);
|
|
psscr_mask = kcalloc(dt_idle_states, sizeof(*psscr_mask), GFP_KERNEL);
|
|
residency_ns = kcalloc(dt_idle_states, sizeof(*residency_ns),
|
|
GFP_KERNEL);
|
|
|
|
if (!psscr_val || !psscr_mask || !residency_ns) {
|
|
rc = -1;
|
|
goto out;
|
|
}
|
|
|
|
if (of_property_read_u64_array(np,
|
|
"ibm,cpu-idle-state-psscr",
|
|
psscr_val, dt_idle_states)) {
|
|
pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr in DT\n");
|
|
rc = -1;
|
|
goto out;
|
|
}
|
|
|
|
if (of_property_read_u64_array(np,
|
|
"ibm,cpu-idle-state-psscr-mask",
|
|
psscr_mask, dt_idle_states)) {
|
|
pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr-mask in DT\n");
|
|
rc = -1;
|
|
goto out;
|
|
}
|
|
|
|
if (of_property_read_u32_array(np,
|
|
"ibm,cpu-idle-state-residency-ns",
|
|
residency_ns, dt_idle_states)) {
|
|
pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-residency-ns in DT\n");
|
|
rc = -1;
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Set pnv_first_deep_stop_state, pnv_deepest_stop_psscr_{val,mask},
|
|
* and the pnv_default_stop_{val,mask}.
|
|
*
|
|
* pnv_first_deep_stop_state should be set to the first stop
|
|
* level to cause hypervisor state loss.
|
|
*
|
|
* pnv_deepest_stop_{val,mask} should be set to values corresponding to
|
|
* the deepest stop state.
|
|
*
|
|
* pnv_default_stop_{val,mask} should be set to values corresponding to
|
|
* the shallowest (OPAL_PM_STOP_INST_FAST) loss-less stop state.
|
|
*/
|
|
pnv_first_deep_stop_state = MAX_STOP_STATE;
|
|
for (i = 0; i < dt_idle_states; i++) {
|
|
int err;
|
|
u64 psscr_rl = psscr_val[i] & PSSCR_RL_MASK;
|
|
|
|
if ((flags[i] & OPAL_PM_LOSE_FULL_CONTEXT) &&
|
|
(pnv_first_deep_stop_state > psscr_rl))
|
|
pnv_first_deep_stop_state = psscr_rl;
|
|
|
|
err = validate_psscr_val_mask(&psscr_val[i], &psscr_mask[i],
|
|
flags[i]);
|
|
if (err) {
|
|
report_invalid_psscr_val(psscr_val[i], err);
|
|
continue;
|
|
}
|
|
|
|
if (max_residency_ns < residency_ns[i]) {
|
|
max_residency_ns = residency_ns[i];
|
|
pnv_deepest_stop_psscr_val = psscr_val[i];
|
|
pnv_deepest_stop_psscr_mask = psscr_mask[i];
|
|
pnv_deepest_stop_flag = flags[i];
|
|
deepest_stop_found = true;
|
|
}
|
|
|
|
if (!default_stop_found &&
|
|
(flags[i] & OPAL_PM_STOP_INST_FAST)) {
|
|
pnv_default_stop_val = psscr_val[i];
|
|
pnv_default_stop_mask = psscr_mask[i];
|
|
default_stop_found = true;
|
|
}
|
|
}
|
|
|
|
if (unlikely(!default_stop_found)) {
|
|
pr_warn("cpuidle-powernv: No suitable default stop state found. Disabling platform idle.\n");
|
|
} else {
|
|
ppc_md.power_save = power9_idle;
|
|
pr_info("cpuidle-powernv: Default stop: psscr = 0x%016llx,mask=0x%016llx\n",
|
|
pnv_default_stop_val, pnv_default_stop_mask);
|
|
}
|
|
|
|
if (unlikely(!deepest_stop_found)) {
|
|
pr_warn("cpuidle-powernv: No suitable stop state for CPU-Hotplug. Offlined CPUs will busy wait");
|
|
} else {
|
|
pr_info("cpuidle-powernv: Deepest stop: psscr = 0x%016llx,mask=0x%016llx\n",
|
|
pnv_deepest_stop_psscr_val,
|
|
pnv_deepest_stop_psscr_mask);
|
|
}
|
|
|
|
pr_info("cpuidle-powernv: Requested Level (RL) value of first deep stop = 0x%llx\n",
|
|
pnv_first_deep_stop_state);
|
|
out:
|
|
kfree(psscr_val);
|
|
kfree(psscr_mask);
|
|
kfree(residency_ns);
|
|
return rc;
|
|
}
|
|
|
|
/*
|
|
* Probe device tree for supported idle states
|
|
*/
|
|
static void __init pnv_probe_idle_states(void)
|
|
{
|
|
struct device_node *np;
|
|
int dt_idle_states;
|
|
u32 *flags = NULL;
|
|
int i;
|
|
|
|
np = of_find_node_by_path("/ibm,opal/power-mgt");
|
|
if (!np) {
|
|
pr_warn("opal: PowerMgmt Node not found\n");
|
|
goto out;
|
|
}
|
|
dt_idle_states = of_property_count_u32_elems(np,
|
|
"ibm,cpu-idle-state-flags");
|
|
if (dt_idle_states < 0) {
|
|
pr_warn("cpuidle-powernv: no idle states found in the DT\n");
|
|
goto out;
|
|
}
|
|
|
|
flags = kcalloc(dt_idle_states, sizeof(*flags), GFP_KERNEL);
|
|
|
|
if (of_property_read_u32_array(np,
|
|
"ibm,cpu-idle-state-flags", flags, dt_idle_states)) {
|
|
pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-flags in DT\n");
|
|
goto out;
|
|
}
|
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_300)) {
|
|
if (pnv_power9_idle_init(np, flags, dt_idle_states))
|
|
goto out;
|
|
}
|
|
|
|
for (i = 0; i < dt_idle_states; i++)
|
|
supported_cpuidle_states |= flags[i];
|
|
|
|
out:
|
|
kfree(flags);
|
|
}
|
|
static int __init pnv_init_idle_states(void)
|
|
{
|
|
|
|
supported_cpuidle_states = 0;
|
|
|
|
if (cpuidle_disable != IDLE_NO_OVERRIDE)
|
|
goto out;
|
|
|
|
pnv_probe_idle_states();
|
|
|
|
if (!(supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) {
|
|
patch_instruction(
|
|
(unsigned int *)pnv_fastsleep_workaround_at_entry,
|
|
PPC_INST_NOP);
|
|
patch_instruction(
|
|
(unsigned int *)pnv_fastsleep_workaround_at_exit,
|
|
PPC_INST_NOP);
|
|
} else {
|
|
/*
|
|
* OPAL_PM_SLEEP_ENABLED_ER1 is set. It indicates that
|
|
* workaround is needed to use fastsleep. Provide sysfs
|
|
* control to choose how this workaround has to be applied.
|
|
*/
|
|
device_create_file(cpu_subsys.dev_root,
|
|
&dev_attr_fastsleep_workaround_applyonce);
|
|
}
|
|
|
|
pnv_alloc_idle_core_states();
|
|
|
|
/*
|
|
* For each CPU, record its PACA address in each of it's
|
|
* sibling thread's PACA at the slot corresponding to this
|
|
* CPU's index in the core.
|
|
*/
|
|
if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
|
|
int cpu;
|
|
|
|
pr_info("powernv: idle: Saving PACA pointers of all CPUs in their thread sibling PACA\n");
|
|
for_each_possible_cpu(cpu) {
|
|
int base_cpu = cpu_first_thread_sibling(cpu);
|
|
int idx = cpu_thread_in_core(cpu);
|
|
int i;
|
|
|
|
for (i = 0; i < threads_per_core; i++) {
|
|
int j = base_cpu + i;
|
|
|
|
paca[j].thread_sibling_pacas[idx] = &paca[cpu];
|
|
}
|
|
}
|
|
}
|
|
|
|
if (supported_cpuidle_states & OPAL_PM_NAP_ENABLED)
|
|
ppc_md.power_save = power7_idle;
|
|
|
|
out:
|
|
return 0;
|
|
}
|
|
machine_subsys_initcall(powernv, pnv_init_idle_states);
|