367 lines
8.4 KiB
Plaintext
367 lines
8.4 KiB
Plaintext
/* Device Tree Source for GEFanuc C2K
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*
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* Author: Remi Machet <rmachet@slac.stanford.edu>
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*
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* Originated from prpmc2800.dts
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*
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* 2008 (c) Stanford University
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* 2007 (c) MontaVista, Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "C2K";
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compatible = "GEFanuc,C2K";
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coherency-off;
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aliases {
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pci0 = &PCI0;
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pci1 = &PCI1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "PowerPC,7447";
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reg = <0>;
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clock-frequency = <996000000>; /* 996 MHz */
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bus-frequency = <166666667>; /* 166.6666 MHz */
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timebase-frequency = <41666667>; /* 166.6666/4 MHz */
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x40000000>; /* 1GB */
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};
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system-controller@d8000000 { /* Marvell Discovery */
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#address-cells = <1>;
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#size-cells = <1>;
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model = "mv64460";
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compatible = "marvell,mv64360";
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clock-frequency = <166666667>; /* 166.66... MHz */
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reg = <0xd8000000 0x00010000>;
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virtual-reg = <0xd8000000>;
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ranges = <0xd4000000 0xd4000000 0x01000000 /* PCI 0 I/O Space */
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0x80000000 0x80000000 0x08000000 /* PCI 0 MEM Space */
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0xd0000000 0xd0000000 0x01000000 /* PCI 1 I/O Space */
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0xa0000000 0xa0000000 0x08000000 /* PCI 1 MEM Space */
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0xd8100000 0xd8100000 0x00010000 /* FPGA */
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0xd8110000 0xd8110000 0x00010000 /* FPGA USARTs */
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0xf8000000 0xf8000000 0x08000000 /* User FLASH */
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0x00000000 0xd8000000 0x00010000 /* Bridge's regs */
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0xd8140000 0xd8140000 0x00040000>; /* Integrated SRAM */
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mdio@2000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,mv64360-mdio";
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reg = <0x2000 4>;
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PHY0: ethernet-phy@0 {
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interrupts = <76>; /* GPP 12 */
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interrupt-parent = <&PIC>;
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reg = <0>;
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};
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PHY1: ethernet-phy@1 {
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interrupts = <76>; /* GPP 12 */
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interrupt-parent = <&PIC>;
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reg = <1>;
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};
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PHY2: ethernet-phy@2 {
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interrupts = <76>; /* GPP 12 */
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interrupt-parent = <&PIC>;
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reg = <2>;
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};
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};
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ethernet-group@2000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,mv64360-eth-group";
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reg = <0x2000 0x2000>;
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ethernet@0 {
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device_type = "network";
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compatible = "marvell,mv64360-eth";
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reg = <0>;
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interrupts = <32>;
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interrupt-parent = <&PIC>;
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phy = <&PHY0>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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ethernet@1 {
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device_type = "network";
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compatible = "marvell,mv64360-eth";
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reg = <1>;
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interrupts = <33>;
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interrupt-parent = <&PIC>;
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phy = <&PHY1>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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ethernet@2 {
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device_type = "network";
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compatible = "marvell,mv64360-eth";
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reg = <2>;
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interrupts = <34>;
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interrupt-parent = <&PIC>;
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phy = <&PHY2>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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};
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SDMA0: sdma@4000 {
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compatible = "marvell,mv64360-sdma";
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reg = <0x4000 0xc18>;
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virtual-reg = <0xd8004000>;
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interrupt-base = <0>;
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interrupts = <36>;
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interrupt-parent = <&PIC>;
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};
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SDMA1: sdma@6000 {
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compatible = "marvell,mv64360-sdma";
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reg = <0x6000 0xc18>;
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virtual-reg = <0xd8006000>;
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interrupt-base = <0>;
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interrupts = <38>;
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interrupt-parent = <&PIC>;
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};
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BRG0: brg@b200 {
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compatible = "marvell,mv64360-brg";
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reg = <0xb200 0x8>;
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clock-src = <8>;
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clock-frequency = <133333333>;
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current-speed = <115200>;
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};
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BRG1: brg@b208 {
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compatible = "marvell,mv64360-brg";
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reg = <0xb208 0x8>;
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clock-src = <8>;
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clock-frequency = <133333333>;
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current-speed = <115200>;
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};
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CUNIT: cunit@f200 {
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reg = <0xf200 0x200>;
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};
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MPSCROUTING: mpscrouting@b400 {
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reg = <0xb400 0xc>;
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};
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MPSCINTR: mpscintr@b800 {
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reg = <0xb800 0x100>;
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virtual-reg = <0xd800b800>;
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};
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MPSC0: mpsc@8000 {
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compatible = "marvell,mv64360-mpsc";
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reg = <0x8000 0x38>;
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virtual-reg = <0xd8008000>;
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sdma = <&SDMA0>;
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brg = <&BRG0>;
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cunit = <&CUNIT>;
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mpscrouting = <&MPSCROUTING>;
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mpscintr = <&MPSCINTR>;
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cell-index = <0>;
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interrupts = <40>;
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interrupt-parent = <&PIC>;
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};
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MPSC1: mpsc@9000 {
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compatible = "marvell,mv64360-mpsc";
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reg = <0x9000 0x38>;
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virtual-reg = <0xd8009000>;
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sdma = <&SDMA1>;
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brg = <&BRG1>;
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cunit = <&CUNIT>;
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mpscrouting = <&MPSCROUTING>;
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mpscintr = <&MPSCINTR>;
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cell-index = <1>;
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interrupts = <42>;
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interrupt-parent = <&PIC>;
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};
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wdt@b410 { /* watchdog timer */
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compatible = "marvell,mv64360-wdt";
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reg = <0xb410 0x8>;
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};
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i2c@c000 {
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compatible = "marvell,mv64360-i2c";
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reg = <0xc000 0x20>;
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virtual-reg = <0xd800c000>;
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interrupts = <37>;
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interrupt-parent = <&PIC>;
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};
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PIC: pic {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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compatible = "marvell,mv64360-pic";
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reg = <0x0000 0x88>;
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interrupt-controller;
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};
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mpp@f000 {
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compatible = "marvell,mv64360-mpp";
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reg = <0xf000 0x10>;
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};
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gpp@f100 {
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compatible = "marvell,mv64360-gpp";
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reg = <0xf100 0x20>;
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};
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PCI0: pci@80000000 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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compatible = "marvell,mv64360-pci";
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reg = <0x0cf8 0x8>;
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ranges = <0x01000000 0x0 0x00000000 0xd4000000 0x0 0x01000000
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0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>;
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bus-range = <0 255>;
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clock-frequency = <66000000>;
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interrupt-pci-iack = <0x0c34>;
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interrupt-parent = <&PIC>;
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interrupt-map-mask = <0x0000 0x0 0x0 0x7>;
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interrupt-map = <
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/* Only one interrupt line for PMC0 slot (INTA) */
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0x0000 0 0 1 &PIC 88
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>;
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};
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PCI1: pci@a0000000 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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compatible = "marvell,mv64360-pci";
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reg = <0x0c78 0x8>;
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ranges = <0x01000000 0x0 0x00000000 0xd0000000 0x0 0x01000000
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0x02000000 0x0 0x80000000 0xa0000000 0x0 0x08000000>;
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bus-range = <0 255>;
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clock-frequency = <66000000>;
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interrupt-pci-iack = <0x0cb4>;
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interrupt-parent = <&PIC>;
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interrupt-map-mask = <0xf800 0x00 0x00 0x7>;
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interrupt-map = <
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/* IDSEL 0x01: PMC1 ? */
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0x0800 0 0 1 &PIC 88
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/* IDSEL 0x02: cPCI bridge */
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0x1000 0 0 1 &PIC 88
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/* IDSEL 0x03: USB controller */
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0x1800 0 0 1 &PIC 91
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/* IDSEL 0x04: SATA controller */
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0x2000 0 0 1 &PIC 95
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>;
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};
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cpu-error@0070 {
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compatible = "marvell,mv64360-cpu-error";
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reg = <0x0070 0x10 0x0128 0x28>;
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interrupts = <3>;
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interrupt-parent = <&PIC>;
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};
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sram-ctrl@0380 {
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compatible = "marvell,mv64360-sram-ctrl";
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reg = <0x0380 0x80>;
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interrupts = <13>;
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interrupt-parent = <&PIC>;
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};
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pci-error@1d40 {
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compatible = "marvell,mv64360-pci-error";
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reg = <0x1d40 0x40 0x0c28 0x4>;
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interrupts = <12>;
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interrupt-parent = <&PIC>;
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};
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pci-error@1dc0 {
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compatible = "marvell,mv64360-pci-error";
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reg = <0x1dc0 0x40 0x0ca8 0x4>;
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interrupts = <16>;
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interrupt-parent = <&PIC>;
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};
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mem-ctrl@1400 {
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compatible = "marvell,mv64360-mem-ctrl";
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reg = <0x1400 0x60>;
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interrupts = <17>;
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interrupt-parent = <&PIC>;
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};
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/* Devices attached to the device controller */
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devicebus@045c {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "marvell,mv64306-devctrl";
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reg = <0x45C 0x88>;
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interrupts = <1>;
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interrupt-parent = <&PIC>;
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ranges = <0 0 0xd8100000 0x10000
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2 0 0xd8110000 0x10000
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4 0 0xf8000000 0x8000000>;
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fpga@0,0 {
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compatible = "sbs,fpga-c2k";
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reg = <0 0 0x10000>;
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};
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fpga_usart@2,0 {
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compatible = "sbs,fpga_usart-c2k";
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reg = <2 0 0x10000>;
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};
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nor_flash@4,0 {
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compatible = "cfi-flash";
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reg = <4 0 0x8000000>; /* 128MB */
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bank-width = <4>;
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device-width = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "boot";
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reg = <0x00000000 0x00080000>;
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};
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partition@40000 {
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label = "kernel";
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reg = <0x00080000 0x00400000>;
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};
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partition@440000 {
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label = "initrd";
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reg = <0x00480000 0x00B80000>;
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};
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partition@1000000 {
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label = "rootfs";
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reg = <0x01000000 0x06800000>;
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};
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partition@7800000 {
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label = "recovery";
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reg = <0x07800000 0x00800000>;
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read-only;
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};
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};
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};
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};
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chosen {
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linux,stdout-path = &MPSC0;
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};
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};
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