423 lines
18 KiB
C
423 lines
18 KiB
C
/* *********************************************************************
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* SB1250 Board Support Package
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*
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* LDT constants File: sb1250_ldt.h
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*
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* This module contains constants and macros to describe
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* the LDT interface on the SB1250.
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*
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* SB1250 specification level: User's manual 1/02/02
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*
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*********************************************************************
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*
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* Copyright 2000, 2001, 2002, 2003
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* Broadcom Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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********************************************************************* */
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#ifndef _SB1250_LDT_H
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#define _SB1250_LDT_H
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#include <asm/sibyte/sb1250_defs.h>
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#define K_LDT_VENDOR_SIBYTE 0x166D
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#define K_LDT_DEVICE_SB1250 0x0002
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/*
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* LDT Interface Type 1 (bridge) configuration header
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*/
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#define R_LDT_TYPE1_DEVICEID 0x0000
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#define R_LDT_TYPE1_CMDSTATUS 0x0004
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#define R_LDT_TYPE1_CLASSREV 0x0008
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#define R_LDT_TYPE1_DEVHDR 0x000C
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#define R_LDT_TYPE1_BAR0 0x0010 /* not used */
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#define R_LDT_TYPE1_BAR1 0x0014 /* not used */
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#define R_LDT_TYPE1_BUSID 0x0018 /* bus ID register */
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#define R_LDT_TYPE1_SECSTATUS 0x001C /* secondary status / I/O base/limit */
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#define R_LDT_TYPE1_MEMLIMIT 0x0020
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#define R_LDT_TYPE1_PREFETCH 0x0024
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#define R_LDT_TYPE1_PREF_BASE 0x0028
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#define R_LDT_TYPE1_PREF_LIMIT 0x002C
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#define R_LDT_TYPE1_IOLIMIT 0x0030
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#define R_LDT_TYPE1_CAPPTR 0x0034
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#define R_LDT_TYPE1_ROMADDR 0x0038
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#define R_LDT_TYPE1_BRCTL 0x003C
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#define R_LDT_TYPE1_CMD 0x0040
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#define R_LDT_TYPE1_LINKCTRL 0x0044
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#define R_LDT_TYPE1_LINKFREQ 0x0048
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#define R_LDT_TYPE1_RESERVED1 0x004C
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#define R_LDT_TYPE1_SRICMD 0x0050
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#define R_LDT_TYPE1_SRITXNUM 0x0054
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#define R_LDT_TYPE1_SRIRXNUM 0x0058
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#define R_LDT_TYPE1_ERRSTATUS 0x0068
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#define R_LDT_TYPE1_SRICTRL 0x006C
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
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#define R_LDT_TYPE1_ADDSTATUS 0x0070
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#endif /* 1250 PASS2 || 112x PASS1 */
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#define R_LDT_TYPE1_TXBUFCNT 0x00C8
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#define R_LDT_TYPE1_EXPCRC 0x00DC
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#define R_LDT_TYPE1_RXCRC 0x00F0
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/*
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* LDT Device ID register
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*/
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#define S_LDT_DEVICEID_VENDOR 0
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#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16, S_LDT_DEVICEID_VENDOR)
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#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR)
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#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR)
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#define S_LDT_DEVICEID_DEVICEID 16
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#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16, S_LDT_DEVICEID_DEVICEID)
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#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID)
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#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVICEID)
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/*
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* LDT Command Register (Table 8-13)
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*/
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#define M_LDT_CMD_IOSPACE_EN _SB_MAKEMASK1_32(0)
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#define M_LDT_CMD_MEMSPACE_EN _SB_MAKEMASK1_32(1)
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#define M_LDT_CMD_MASTER_EN _SB_MAKEMASK1_32(2)
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#define M_LDT_CMD_SPECCYC_EN _SB_MAKEMASK1_32(3)
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#define M_LDT_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4)
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#define M_LDT_CMD_VGAPALSNP_EN _SB_MAKEMASK1_32(5)
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#define M_LDT_CMD_PARERRRESP _SB_MAKEMASK1_32(6)
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#define M_LDT_CMD_WAITCYCCTRL _SB_MAKEMASK1_32(7)
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#define M_LDT_CMD_SERR_EN _SB_MAKEMASK1_32(8)
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#define M_LDT_CMD_FASTB2B_EN _SB_MAKEMASK1_32(9)
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/*
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* LDT class and revision registers
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*/
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#define S_LDT_CLASSREV_REV 0
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#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8, S_LDT_CLASSREV_REV)
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#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV)
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#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV)
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#define S_LDT_CLASSREV_CLASS 8
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#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24, S_LDT_CLASSREV_CLASS)
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#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS)
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#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_CLASS, M_LDT_CLASSREV_CLASS)
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#define K_LDT_REV 0x01
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#define K_LDT_CLASS 0x060000
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/*
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* Device Header (offset 0x0C)
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*/
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#define S_LDT_DEVHDR_CLINESZ 0
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#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8, S_LDT_DEVHDR_CLINESZ)
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#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_CLINESZ)
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#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_CLINESZ, M_LDT_DEVHDR_CLINESZ)
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#define S_LDT_DEVHDR_LATTMR 8
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#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8, S_LDT_DEVHDR_LATTMR)
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#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_LATTMR)
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#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_LATTMR, M_LDT_DEVHDR_LATTMR)
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#define S_LDT_DEVHDR_HDRTYPE 16
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#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8, S_LDT_DEVHDR_HDRTYPE)
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#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_HDRTYPE)
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#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_HDRTYPE, M_LDT_DEVHDR_HDRTYPE)
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#define K_LDT_DEVHDR_HDRTYPE_TYPE1 1
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#define S_LDT_DEVHDR_BIST 24
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#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8, S_LDT_DEVHDR_BIST)
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#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_BIST)
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#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_BIST, M_LDT_DEVHDR_BIST)
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/*
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* LDT Status Register (Table 8-14). Note that these constants
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* assume you've read the command and status register
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* together (32-bit read at offset 0x04)
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*
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* These bits also apply to the secondary status
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* register (Table 8-15), offset 0x1C
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*/
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
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#define M_LDT_STATUS_VGAEN _SB_MAKEMASK1_32(3)
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#endif /* 1250 PASS2 || 112x PASS1 */
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#define M_LDT_STATUS_CAPLIST _SB_MAKEMASK1_32(20)
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#define M_LDT_STATUS_66MHZCAP _SB_MAKEMASK1_32(21)
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#define M_LDT_STATUS_RESERVED2 _SB_MAKEMASK1_32(22)
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#define M_LDT_STATUS_FASTB2BCAP _SB_MAKEMASK1_32(23)
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#define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24)
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#define S_LDT_STATUS_DEVSELTIMING 25
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#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2, S_LDT_STATUS_DEVSELTIMING)
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#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x, S_LDT_STATUS_DEVSELTIMING)
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#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x, S_LDT_STATUS_DEVSELTIMING, M_LDT_STATUS_DEVSELTIMING)
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#define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27)
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#define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28)
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#define M_LDT_STATUS_RCVDMSTRABORT _SB_MAKEMASK1_32(29)
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#define M_LDT_STATUS_SIGDSERR _SB_MAKEMASK1_32(30)
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#define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31)
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/*
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* Bridge Control Register (Table 8-16). Note that these
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* constants assume you've read the register as a 32-bit
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* read (offset 0x3C)
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*/
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#define M_LDT_BRCTL_PARERRRESP_EN _SB_MAKEMASK1_32(16)
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#define M_LDT_BRCTL_SERR_EN _SB_MAKEMASK1_32(17)
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#define M_LDT_BRCTL_ISA_EN _SB_MAKEMASK1_32(18)
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#define M_LDT_BRCTL_VGA_EN _SB_MAKEMASK1_32(19)
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#define M_LDT_BRCTL_MSTRABORTMODE _SB_MAKEMASK1_32(21)
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#define M_LDT_BRCTL_SECBUSRESET _SB_MAKEMASK1_32(22)
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#define M_LDT_BRCTL_FASTB2B_EN _SB_MAKEMASK1_32(23)
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#define M_LDT_BRCTL_PRIDISCARD _SB_MAKEMASK1_32(24)
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#define M_LDT_BRCTL_SECDISCARD _SB_MAKEMASK1_32(25)
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#define M_LDT_BRCTL_DISCARDSTAT _SB_MAKEMASK1_32(26)
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#define M_LDT_BRCTL_DISCARDSERR_EN _SB_MAKEMASK1_32(27)
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/*
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* LDT Command Register (Table 8-17). Note that these constants
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* assume you've read the command and status register together
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* 32-bit read at offset 0x40
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*/
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#define M_LDT_CMD_WARMRESET _SB_MAKEMASK1_32(16)
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#define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17)
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#define S_LDT_CMD_CAPTYPE 29
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#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3, S_LDT_CMD_CAPTYPE)
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#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_CMD_CAPTYPE)
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#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x, S_LDT_CMD_CAPTYPE, M_LDT_CMD_CAPTYPE)
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/*
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* LDT link control register (Table 8-18), and (Table 8-19)
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*/
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#define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN _SB_MAKEMASK1_32(1)
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#define M_LDT_LINKCTRL_CRCSTARTTEST _SB_MAKEMASK1_32(2)
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#define M_LDT_LINKCTRL_CRCFORCEERR _SB_MAKEMASK1_32(3)
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#define M_LDT_LINKCTRL_LINKFAIL _SB_MAKEMASK1_32(4)
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#define M_LDT_LINKCTRL_INITDONE _SB_MAKEMASK1_32(5)
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#define M_LDT_LINKCTRL_EOC _SB_MAKEMASK1_32(6)
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#define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7)
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#define S_LDT_LINKCTRL_CRCERR 8
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#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4, S_LDT_LINKCTRL_CRCERR)
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#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_CRCERR)
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#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_CRCERR, M_LDT_LINKCTRL_CRCERR)
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#define S_LDT_LINKCTRL_MAXIN 16
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#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXIN)
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#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXIN)
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#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXIN, M_LDT_LINKCTRL_MAXIN)
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#define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19)
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#define S_LDT_LINKCTRL_MAXOUT 20
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#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXOUT)
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#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXOUT)
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#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXOUT, M_LDT_LINKCTRL_MAXOUT)
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#define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23)
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#define S_LDT_LINKCTRL_WIDTHIN 24
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#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHIN)
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#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN)
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#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN, M_LDT_LINKCTRL_WIDTHIN)
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#define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27)
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#define S_LDT_LINKCTRL_WIDTHOUT 28
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#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHOUT)
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#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT)
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#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT, M_LDT_LINKCTRL_WIDTHOUT)
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#define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31)
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/*
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* LDT Link frequency register (Table 8-20) offset 0x48
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*/
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#define S_LDT_LINKFREQ_FREQ 8
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#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4, S_LDT_LINKFREQ_FREQ)
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#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x, S_LDT_LINKFREQ_FREQ)
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#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x, S_LDT_LINKFREQ_FREQ, M_LDT_LINKFREQ_FREQ)
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#define K_LDT_LINKFREQ_200MHZ 0
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#define K_LDT_LINKFREQ_300MHZ 1
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#define K_LDT_LINKFREQ_400MHZ 2
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#define K_LDT_LINKFREQ_500MHZ 3
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#define K_LDT_LINKFREQ_600MHZ 4
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#define K_LDT_LINKFREQ_800MHZ 5
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#define K_LDT_LINKFREQ_1000MHZ 6
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/*
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* LDT SRI Command Register (Table 8-21). Note that these constants
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* assume you've read the command and status register together
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* 32-bit read at offset 0x50
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*/
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#define M_LDT_SRICMD_SIPREADY _SB_MAKEMASK1_32(16)
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#define M_LDT_SRICMD_SYNCPTRCTL _SB_MAKEMASK1_32(17)
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#define M_LDT_SRICMD_REDUCESYNCZERO _SB_MAKEMASK1_32(18)
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#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
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#define M_LDT_SRICMD_DISSTARVATIONCNT _SB_MAKEMASK1_32(19) /* PASS1 */
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#endif /* up to 1250 PASS1 */
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
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#define M_LDT_SRICMD_DISMULTTXVLD _SB_MAKEMASK1_32(19)
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#define M_LDT_SRICMD_EXPENDIAN _SB_MAKEMASK1_32(26)
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#endif /* 1250 PASS2 || 112x PASS1 */
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#define S_LDT_SRICMD_RXMARGIN 20
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#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5, S_LDT_SRICMD_RXMARGIN)
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#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_RXMARGIN)
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#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_RXMARGIN, M_LDT_SRICMD_RXMARGIN)
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#define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25)
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#define S_LDT_SRICMD_TXINITIALOFFSET 28
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#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET)
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#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET)
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#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET)
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#define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31)
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/*
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* LDT Error control and status register (Table 8-22) (Table 8-23)
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*/
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#define M_LDT_ERRCTL_PROTFATAL_EN _SB_MAKEMASK1_32(0)
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#define M_LDT_ERRCTL_PROTNONFATAL_EN _SB_MAKEMASK1_32(1)
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#define M_LDT_ERRCTL_PROTSYNCFLOOD_EN _SB_MAKEMASK1_32(2)
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#define M_LDT_ERRCTL_OVFFATAL_EN _SB_MAKEMASK1_32(3)
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#define M_LDT_ERRCTL_OVFNONFATAL_EN _SB_MAKEMASK1_32(4)
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#define M_LDT_ERRCTL_OVFSYNCFLOOD_EN _SB_MAKEMASK1_32(5)
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#define M_LDT_ERRCTL_EOCNXAFATAL_EN _SB_MAKEMASK1_32(6)
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#define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7)
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#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8)
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#define M_LDT_ERRCTL_CRCFATAL_EN _SB_MAKEMASK1_32(9)
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#define M_LDT_ERRCTL_CRCNONFATAL_EN _SB_MAKEMASK1_32(10)
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#define M_LDT_ERRCTL_SERRFATAL_EN _SB_MAKEMASK1_32(11)
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#define M_LDT_ERRCTL_SRCTAGFATAL_EN _SB_MAKEMASK1_32(12)
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#define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13)
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#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14)
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#define M_LDT_ERRCTL_MAPNXAFATAL_EN _SB_MAKEMASK1_32(15)
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#define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16)
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#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17)
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#define M_LDT_ERRCTL_PROTOERR _SB_MAKEMASK1_32(24)
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#define M_LDT_ERRCTL_OVFERR _SB_MAKEMASK1_32(25)
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#define M_LDT_ERRCTL_EOCNXAERR _SB_MAKEMASK1_32(26)
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#define M_LDT_ERRCTL_SRCTAGERR _SB_MAKEMASK1_32(27)
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#define M_LDT_ERRCTL_MAPNXAERR _SB_MAKEMASK1_32(28)
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/*
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* SRI Control register (Table 8-24, 8-25) Offset 0x6C
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*/
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#define S_LDT_SRICTRL_NEEDRESP 0
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#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDRESP)
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#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDRESP)
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#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDRESP, M_LDT_SRICTRL_NEEDRESP)
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#define S_LDT_SRICTRL_NEEDNPREQ 2
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#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDNPREQ)
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#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ)
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#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ, M_LDT_SRICTRL_NEEDNPREQ)
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#define S_LDT_SRICTRL_NEEDPREQ 4
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#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDPREQ)
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#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ)
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#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ, M_LDT_SRICTRL_NEEDPREQ)
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#define S_LDT_SRICTRL_WANTRESP 8
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#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTRESP)
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#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTRESP)
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#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTRESP, M_LDT_SRICTRL_WANTRESP)
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#define S_LDT_SRICTRL_WANTNPREQ 10
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#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTNPREQ)
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#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ)
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#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ, M_LDT_SRICTRL_WANTNPREQ)
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#define S_LDT_SRICTRL_WANTPREQ 12
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#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTPREQ)
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#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTPREQ)
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#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTPREQ, M_LDT_SRICTRL_WANTPREQ)
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#define S_LDT_SRICTRL_BUFRELSPACE 16
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#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4, S_LDT_SRICTRL_BUFRELSPACE)
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#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE)
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#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE, M_LDT_SRICTRL_BUFRELSPACE)
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/*
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* LDT SRI Transmit Buffer Count register (Table 8-26)
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*/
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#define S_LDT_TXBUFCNT_PCMD 0
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#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PCMD)
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#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PCMD)
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#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PCMD, M_LDT_TXBUFCNT_PCMD)
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#define S_LDT_TXBUFCNT_PDATA 4
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#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PDATA)
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#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PDATA)
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#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PDATA, M_LDT_TXBUFCNT_PDATA)
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#define S_LDT_TXBUFCNT_NPCMD 8
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#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPCMD)
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#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPCMD)
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#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPCMD, M_LDT_TXBUFCNT_NPCMD)
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#define S_LDT_TXBUFCNT_NPDATA 12
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#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPDATA)
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#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPDATA)
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#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPDATA, M_LDT_TXBUFCNT_NPDATA)
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#define S_LDT_TXBUFCNT_RCMD 16
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#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RCMD)
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#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RCMD)
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#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RCMD, M_LDT_TXBUFCNT_RCMD)
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#define S_LDT_TXBUFCNT_RDATA 20
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#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RDATA)
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#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RDATA)
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#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RDATA, M_LDT_TXBUFCNT_RDATA)
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
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/*
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* Additional Status Register
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*/
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#define S_LDT_ADDSTATUS_TGTDONE 0
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#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8, S_LDT_ADDSTATUS_TGTDONE)
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#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE)
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#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE, M_LDT_ADDSTATUS_TGTDONE)
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#endif /* 1250 PASS2 || 112x PASS1 */
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#endif
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