261 lines
5.6 KiB
C
261 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles.
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*
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* Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com>
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*/
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#ifndef _GPIO_AU1300_H_
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#define _GPIO_AU1300_H_
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#include <asm/mach-au1x00/au1000.h>
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struct gpio;
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struct gpio_chip;
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/* with the current GPIC design, up to 128 GPIOs are possible.
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* The only implementation so far is in the Au1300, which has 75 externally
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* available GPIOs.
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*/
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#define AU1300_GPIO_BASE 0
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#define AU1300_GPIO_NUM 75
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#define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1)
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#define AU1300_GPIC_ADDR \
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(void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR)
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static inline int au1300_gpio_get_value(unsigned int gpio)
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{
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void __iomem *roff = AU1300_GPIC_ADDR;
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int bit;
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gpio -= AU1300_GPIO_BASE;
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roff += GPIC_GPIO_BANKOFF(gpio);
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bit = GPIC_GPIO_TO_BIT(gpio);
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return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit;
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}
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static inline int au1300_gpio_direction_input(unsigned int gpio)
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{
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void __iomem *roff = AU1300_GPIC_ADDR;
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unsigned long bit;
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gpio -= AU1300_GPIO_BASE;
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roff += GPIC_GPIO_BANKOFF(gpio);
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bit = GPIC_GPIO_TO_BIT(gpio);
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__raw_writel(bit, roff + AU1300_GPIC_DEVCLR);
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wmb();
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return 0;
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}
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static inline int au1300_gpio_set_value(unsigned int gpio, int v)
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{
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void __iomem *roff = AU1300_GPIC_ADDR;
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unsigned long bit;
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gpio -= AU1300_GPIO_BASE;
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roff += GPIC_GPIO_BANKOFF(gpio);
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bit = GPIC_GPIO_TO_BIT(gpio);
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__raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
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: AU1300_GPIC_PINVALCLR));
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wmb();
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return 0;
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}
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static inline int au1300_gpio_direction_output(unsigned int gpio, int v)
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{
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/* hw switches to output automatically */
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return au1300_gpio_set_value(gpio, v);
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}
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static inline int au1300_gpio_to_irq(unsigned int gpio)
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{
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return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE);
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}
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static inline int au1300_irq_to_gpio(unsigned int irq)
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{
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return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE;
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}
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static inline int au1300_gpio_is_valid(unsigned int gpio)
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{
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int ret;
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switch (alchemy_get_cputype()) {
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case ALCHEMY_CPU_AU1300:
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ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX));
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break;
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default:
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ret = 0;
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}
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return ret;
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}
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static inline int au1300_gpio_cansleep(unsigned int gpio)
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{
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return 0;
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}
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/* hardware remembers gpio 0-63 levels on powerup */
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static inline int au1300_gpio_getinitlvl(unsigned int gpio)
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{
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void __iomem *roff = AU1300_GPIC_ADDR;
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unsigned long v;
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if (unlikely(gpio > 63))
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return 0;
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else if (gpio > 31) {
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gpio -= 32;
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roff += 4;
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}
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v = __raw_readl(roff + AU1300_GPIC_RSTVAL);
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return (v >> gpio) & 1;
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}
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/**********************************************************************/
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/* Linux gpio framework integration.
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*
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* 4 use cases of Alchemy GPIOS:
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*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
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* Board must register gpiochips.
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*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
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* A gpiochip for the 75 GPIOs is registered.
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*
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*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
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* the boards' gpio.h must provide the linux gpio wrapper functions,
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*
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*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
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* inlinable gpio functions are provided which enable access to the
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* Au1300 gpios only by using the numbers straight out of the data-
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* sheets.
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* Cases 1 and 3 are intended for boards which want to provide their own
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* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
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* which are in part provided by spare Au1300 GPIO pins and in part by
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* an external FPGA but you still want them to be accessible in linux
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* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
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* as required).
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*/
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#ifndef CONFIG_GPIOLIB
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#ifdef CONFIG_ALCHEMY_GPIOINT_AU1300
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#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
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static inline int gpio_direction_input(unsigned int gpio)
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{
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return au1300_gpio_direction_input(gpio);
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}
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static inline int gpio_direction_output(unsigned int gpio, int v)
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{
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return au1300_gpio_direction_output(gpio, v);
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}
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static inline int gpio_get_value(unsigned int gpio)
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{
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return au1300_gpio_get_value(gpio);
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}
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static inline void gpio_set_value(unsigned int gpio, int v)
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{
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au1300_gpio_set_value(gpio, v);
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}
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static inline int gpio_get_value_cansleep(unsigned gpio)
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{
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return gpio_get_value(gpio);
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}
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static inline void gpio_set_value_cansleep(unsigned gpio, int value)
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{
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gpio_set_value(gpio, value);
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}
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static inline int gpio_is_valid(unsigned int gpio)
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{
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return au1300_gpio_is_valid(gpio);
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}
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static inline int gpio_cansleep(unsigned int gpio)
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{
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return au1300_gpio_cansleep(gpio);
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}
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static inline int gpio_to_irq(unsigned int gpio)
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{
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return au1300_gpio_to_irq(gpio);
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}
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static inline int irq_to_gpio(unsigned int irq)
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{
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return au1300_irq_to_gpio(irq);
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}
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static inline int gpio_request(unsigned int gpio, const char *label)
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{
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return 0;
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}
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static inline int gpio_request_one(unsigned gpio,
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unsigned long flags, const char *label)
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{
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return 0;
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}
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static inline int gpio_request_array(struct gpio *array, size_t num)
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{
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return 0;
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}
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static inline void gpio_free(unsigned gpio)
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{
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}
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static inline void gpio_free_array(struct gpio *array, size_t num)
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{
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}
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static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
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{
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return -ENOSYS;
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}
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static inline void gpio_unexport(unsigned gpio)
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{
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}
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static inline int gpio_export(unsigned gpio, bool direction_may_change)
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{
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return -ENOSYS;
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}
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static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
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{
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return -ENOSYS;
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}
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static inline int gpio_export_link(struct device *dev, const char *name,
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unsigned gpio)
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{
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return -ENOSYS;
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}
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#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
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#endif /* CONFIG_ALCHEMY_GPIOINT_AU1300 */
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#endif /* CONFIG GPIOLIB */
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#endif /* _GPIO_AU1300_H_ */
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