410 lines
8.8 KiB
C
410 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include <linux/clk.h>
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#include <linux/mutex.h>
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#include <linux/spinlock.h>
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#include <linux/debugfs.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/timer.h>
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#include <linux/io.h>
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#include <linux/seq_file.h>
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#include <linux/clkdev.h>
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#include <asm/clocks.h>
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#define CGU0_CTL_DF (1 << 0)
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#define CGU0_CTL_MSEL_SHIFT 8
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#define CGU0_CTL_MSEL_MASK (0x7f << 8)
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#define CGU0_STAT_PLLEN (1 << 0)
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#define CGU0_STAT_PLLBP (1 << 1)
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#define CGU0_STAT_PLLLK (1 << 2)
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#define CGU0_STAT_CLKSALGN (1 << 3)
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#define CGU0_STAT_CCBF0 (1 << 4)
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#define CGU0_STAT_CCBF1 (1 << 5)
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#define CGU0_STAT_SCBF0 (1 << 6)
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#define CGU0_STAT_SCBF1 (1 << 7)
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#define CGU0_STAT_DCBF (1 << 8)
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#define CGU0_STAT_OCBF (1 << 9)
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#define CGU0_STAT_ADDRERR (1 << 16)
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#define CGU0_STAT_LWERR (1 << 17)
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#define CGU0_STAT_DIVERR (1 << 18)
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#define CGU0_STAT_WDFMSERR (1 << 19)
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#define CGU0_STAT_WDIVERR (1 << 20)
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#define CGU0_STAT_PLOCKERR (1 << 21)
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#define CGU0_DIV_CSEL_SHIFT 0
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#define CGU0_DIV_CSEL_MASK 0x0000001F
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#define CGU0_DIV_S0SEL_SHIFT 5
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#define CGU0_DIV_S0SEL_MASK (0x3 << CGU0_DIV_S0SEL_SHIFT)
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#define CGU0_DIV_SYSSEL_SHIFT 8
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#define CGU0_DIV_SYSSEL_MASK (0x1f << CGU0_DIV_SYSSEL_SHIFT)
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#define CGU0_DIV_S1SEL_SHIFT 13
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#define CGU0_DIV_S1SEL_MASK (0x3 << CGU0_DIV_S1SEL_SHIFT)
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#define CGU0_DIV_DSEL_SHIFT 16
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#define CGU0_DIV_DSEL_MASK (0x1f << CGU0_DIV_DSEL_SHIFT)
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#define CGU0_DIV_OSEL_SHIFT 22
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#define CGU0_DIV_OSEL_MASK (0x7f << CGU0_DIV_OSEL_SHIFT)
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#define CLK(_clk, _devname, _conname) \
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{ \
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.clk = &_clk, \
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.dev_id = _devname, \
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.con_id = _conname, \
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}
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#define NEEDS_INITIALIZATION 0x11
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static LIST_HEAD(clk_list);
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static void clk_reg_write_mask(u32 reg, uint32_t val, uint32_t mask)
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{
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u32 val2;
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val2 = bfin_read32(reg);
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val2 &= ~mask;
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val2 |= val;
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bfin_write32(reg, val2);
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}
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int wait_for_pll_align(void)
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{
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int i = 10000;
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while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN));
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if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) {
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printk(KERN_CRIT "fail to align clk\n");
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return -1;
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}
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return 0;
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}
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int clk_enable(struct clk *clk)
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{
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int ret = -EIO;
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if (clk->ops && clk->ops->enable)
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ret = clk->ops->enable(clk);
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return ret;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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if (!clk)
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return;
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if (clk->ops && clk->ops->disable)
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clk->ops->disable(clk);
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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unsigned long ret = 0;
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if (clk->ops && clk->ops->get_rate)
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ret = clk->ops->get_rate(clk);
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return ret;
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}
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EXPORT_SYMBOL(clk_get_rate);
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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long ret = 0;
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if (clk->ops && clk->ops->round_rate)
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ret = clk->ops->round_rate(clk, rate);
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return ret;
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}
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EXPORT_SYMBOL(clk_round_rate);
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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int ret = -EIO;
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if (clk->ops && clk->ops->set_rate)
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ret = clk->ops->set_rate(clk, rate);
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return ret;
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}
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EXPORT_SYMBOL(clk_set_rate);
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unsigned long vco_get_rate(struct clk *clk)
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{
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return clk->rate;
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}
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unsigned long pll_get_rate(struct clk *clk)
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{
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u32 df;
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u32 msel;
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u32 ctl = bfin_read32(CGU0_CTL);
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u32 stat = bfin_read32(CGU0_STAT);
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if (stat & CGU0_STAT_PLLBP)
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return 0;
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msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
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df = (ctl & CGU0_CTL_DF);
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clk->parent->rate = clk_get_rate(clk->parent);
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return clk->parent->rate / (df + 1) * msel * 2;
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}
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unsigned long pll_round_rate(struct clk *clk, unsigned long rate)
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{
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u32 div;
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div = rate / clk->parent->rate;
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return clk->parent->rate * div;
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}
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int pll_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 msel;
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u32 stat = bfin_read32(CGU0_STAT);
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if (!(stat & CGU0_STAT_PLLEN))
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return -EBUSY;
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if (!(stat & CGU0_STAT_PLLLK))
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return -EBUSY;
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if (wait_for_pll_align())
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return -EBUSY;
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msel = rate / clk->parent->rate / 2;
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clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT,
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CGU0_CTL_MSEL_MASK);
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clk->rate = rate;
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return 0;
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}
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unsigned long cclk_get_rate(struct clk *clk)
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{
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if (clk->parent)
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return clk->parent->rate;
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else
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return 0;
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}
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unsigned long sys_clk_get_rate(struct clk *clk)
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{
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unsigned long drate;
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u32 msel;
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u32 df;
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u32 ctl = bfin_read32(CGU0_CTL);
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u32 div = bfin_read32(CGU0_DIV);
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div = (div & clk->mask) >> clk->shift;
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msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
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df = (ctl & CGU0_CTL_DF);
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if (!strcmp(clk->parent->name, "SYS_CLKIN")) {
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drate = clk->parent->rate / (df + 1);
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drate *= msel;
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drate /= div;
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return drate;
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} else {
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clk->parent->rate = clk_get_rate(clk->parent);
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return clk->parent->rate / div;
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}
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}
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unsigned long dummy_get_rate(struct clk *clk)
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{
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clk->parent->rate = clk_get_rate(clk->parent);
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return clk->parent->rate;
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}
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unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long max_rate;
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unsigned long drate;
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int i;
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u32 msel;
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u32 df;
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u32 ctl = bfin_read32(CGU0_CTL);
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msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
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df = (ctl & CGU0_CTL_DF);
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max_rate = clk->parent->rate / (df + 1) * msel;
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if (rate > max_rate)
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return 0;
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for (i = 1; i < clk->mask; i++) {
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drate = max_rate / i;
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if (rate >= drate)
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return drate;
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}
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return 0;
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}
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int sys_clk_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 div = bfin_read32(CGU0_DIV);
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div = (div & clk->mask) >> clk->shift;
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rate = clk_round_rate(clk, rate);
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if (!rate)
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return -EINVAL;
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div = (clk_get_rate(clk) * div) / rate;
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if (wait_for_pll_align())
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return -EBUSY;
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clk_reg_write_mask(CGU0_DIV, div << clk->shift,
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clk->mask);
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clk->rate = rate;
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return 0;
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}
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static struct clk_ops vco_ops = {
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.get_rate = vco_get_rate,
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};
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static struct clk_ops pll_ops = {
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.get_rate = pll_get_rate,
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.set_rate = pll_set_rate,
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};
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static struct clk_ops cclk_ops = {
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.get_rate = cclk_get_rate,
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};
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static struct clk_ops sys_clk_ops = {
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.get_rate = sys_clk_get_rate,
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.set_rate = sys_clk_set_rate,
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.round_rate = sys_clk_round_rate,
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};
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static struct clk_ops dummy_clk_ops = {
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.get_rate = dummy_get_rate,
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};
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static struct clk sys_clkin = {
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.name = "SYS_CLKIN",
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.rate = CONFIG_CLKIN_HZ,
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.ops = &vco_ops,
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};
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static struct clk pll_clk = {
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.name = "PLLCLK",
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.rate = 500000000,
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.parent = &sys_clkin,
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.ops = &pll_ops,
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.flags = NEEDS_INITIALIZATION,
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};
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static struct clk cclk = {
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.name = "CCLK",
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.rate = 500000000,
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.mask = CGU0_DIV_CSEL_MASK,
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.shift = CGU0_DIV_CSEL_SHIFT,
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.parent = &sys_clkin,
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.ops = &sys_clk_ops,
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.flags = NEEDS_INITIALIZATION,
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};
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static struct clk cclk0 = {
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.name = "CCLK0",
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.parent = &cclk,
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.ops = &cclk_ops,
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};
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static struct clk cclk1 = {
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.name = "CCLK1",
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.parent = &cclk,
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.ops = &cclk_ops,
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};
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static struct clk sysclk = {
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.name = "SYSCLK",
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.rate = 500000000,
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.mask = CGU0_DIV_SYSSEL_MASK,
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.shift = CGU0_DIV_SYSSEL_SHIFT,
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.parent = &sys_clkin,
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.ops = &sys_clk_ops,
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.flags = NEEDS_INITIALIZATION,
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};
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static struct clk sclk0 = {
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.name = "SCLK0",
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.rate = 500000000,
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.mask = CGU0_DIV_S0SEL_MASK,
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.shift = CGU0_DIV_S0SEL_SHIFT,
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.parent = &sysclk,
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.ops = &sys_clk_ops,
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};
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static struct clk sclk1 = {
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.name = "SCLK1",
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.rate = 500000000,
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.mask = CGU0_DIV_S1SEL_MASK,
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.shift = CGU0_DIV_S1SEL_SHIFT,
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.parent = &sysclk,
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.ops = &sys_clk_ops,
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};
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static struct clk dclk = {
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.name = "DCLK",
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.rate = 500000000,
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.mask = CGU0_DIV_DSEL_MASK,
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.shift = CGU0_DIV_DSEL_SHIFT,
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.parent = &sys_clkin,
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.ops = &sys_clk_ops,
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};
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static struct clk oclk = {
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.name = "OCLK",
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.rate = 500000000,
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.mask = CGU0_DIV_OSEL_MASK,
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.shift = CGU0_DIV_OSEL_SHIFT,
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.parent = &pll_clk,
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};
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static struct clk ethclk = {
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.name = "stmmaceth",
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.parent = &sclk0,
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.ops = &dummy_clk_ops,
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};
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static struct clk ethpclk = {
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.name = "pclk",
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.parent = &sclk0,
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.ops = &dummy_clk_ops,
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};
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static struct clk spiclk = {
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.name = "spi",
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.parent = &sclk1,
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.ops = &dummy_clk_ops,
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};
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static struct clk_lookup bf609_clks[] = {
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CLK(sys_clkin, NULL, "SYS_CLKIN"),
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CLK(pll_clk, NULL, "PLLCLK"),
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CLK(cclk, NULL, "CCLK"),
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CLK(cclk0, NULL, "CCLK0"),
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CLK(cclk1, NULL, "CCLK1"),
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CLK(sysclk, NULL, "SYSCLK"),
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CLK(sclk0, NULL, "SCLK0"),
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CLK(sclk1, NULL, "SCLK1"),
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CLK(dclk, NULL, "DCLK"),
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CLK(oclk, NULL, "OCLK"),
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CLK(ethclk, NULL, "stmmaceth"),
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CLK(ethpclk, NULL, "pclk"),
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CLK(spiclk, NULL, "spi"),
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};
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int __init clk_init(void)
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{
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int i;
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struct clk *clkp;
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for (i = 0; i < ARRAY_SIZE(bf609_clks); i++) {
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clkp = bf609_clks[i].clk;
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if (clkp->flags & NEEDS_INITIALIZATION)
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clk_get_rate(clkp);
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}
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clkdev_add_table(bf609_clks, ARRAY_SIZE(bf609_clks));
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return 0;
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}
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