1861 lines
55 KiB
Plaintext
1861 lines
55 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/mfd/max77620.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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#include "tegra210.dtsi"
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/ {
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model = "Google Pixel C";
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compatible = "google,smaug-rev8", "google,smaug-rev7",
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"google,smaug-rev6", "google,smaug-rev5",
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"google,smaug-rev4", "google,smaug-rev3",
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"google,smaug-rev2", "google,smaug-rev1",
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"google,smaug", "nvidia,tegra210";
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aliases {
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serial0 = &uarta;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0xc0000000>;
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};
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host1x@50000000 {
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dpaux: dpaux@545c0000 {
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status = "okay";
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};
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};
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pinmux: pinmux@700008d4 {
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pinctrl-names = "boot";
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pinctrl-0 = <&state_boot>;
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state_boot: pinmux {
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pex_l0_rst_n_pa0 {
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nvidia,pins = "pex_l0_rst_n_pa0";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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nvidia,io-hv = <TEGRA_PIN_DISABLE>;
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};
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pex_l0_clkreq_n_pa1 {
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nvidia,pins = "pex_l0_clkreq_n_pa1";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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nvidia,io-hv = <TEGRA_PIN_DISABLE>;
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};
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pex_wake_n_pa2 {
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nvidia,pins = "pex_wake_n_pa2";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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nvidia,io-hv = <TEGRA_PIN_DISABLE>;
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};
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pex_l1_rst_n_pa3 {
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nvidia,pins = "pex_l1_rst_n_pa3";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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nvidia,io-hv = <TEGRA_PIN_DISABLE>;
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};
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pex_l1_clkreq_n_pa4 {
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nvidia,pins = "pex_l1_clkreq_n_pa4";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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nvidia,io-hv = <TEGRA_PIN_DISABLE>;
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};
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sata_led_active_pa5 {
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nvidia,pins = "sata_led_active_pa5";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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pa6 {
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nvidia,pins = "pa6";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dap1_fs_pb0 {
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nvidia,pins = "dap1_fs_pb0";
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nvidia,function = "i2s1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dap1_din_pb1 {
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nvidia,pins = "dap1_din_pb1";
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nvidia,function = "i2s1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dap1_dout_pb2 {
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nvidia,pins = "dap1_dout_pb2";
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nvidia,function = "i2s1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dap1_sclk_pb3 {
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nvidia,pins = "dap1_sclk_pb3";
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nvidia,function = "i2s1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi2_mosi_pb4 {
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nvidia,pins = "spi2_mosi_pb4";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi2_miso_pb5 {
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nvidia,pins = "spi2_miso_pb5";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi2_sck_pb6 {
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nvidia,pins = "spi2_sck_pb6";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi2_cs0_pb7 {
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nvidia,pins = "spi2_cs0_pb7";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi1_mosi_pc0 {
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nvidia,pins = "spi1_mosi_pc0";
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nvidia,function = "spi1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi1_miso_pc1 {
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nvidia,pins = "spi1_miso_pc1";
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nvidia,function = "spi1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi1_sck_pc2 {
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nvidia,pins = "spi1_sck_pc2";
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nvidia,function = "spi1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi1_cs0_pc3 {
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nvidia,pins = "spi1_cs0_pc3";
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nvidia,function = "spi1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi1_cs1_pc4 {
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nvidia,pins = "spi1_cs1_pc4";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi4_sck_pc5 {
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nvidia,pins = "spi4_sck_pc5";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi4_cs0_pc6 {
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nvidia,pins = "spi4_cs0_pc6";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi4_mosi_pc7 {
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nvidia,pins = "spi4_mosi_pc7";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi4_miso_pd0 {
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nvidia,pins = "spi4_miso_pd0";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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uart3_tx_pd1 {
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nvidia,pins = "uart3_tx_pd1";
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nvidia,function = "uartc";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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uart3_rx_pd2 {
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nvidia,pins = "uart3_rx_pd2";
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nvidia,function = "uartc";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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uart3_rts_pd3 {
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nvidia,pins = "uart3_rts_pd3";
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nvidia,function = "uartc";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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uart3_cts_pd4 {
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nvidia,pins = "uart3_cts_pd4";
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nvidia,function = "uartc";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dmic1_clk_pe0 {
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nvidia,pins = "dmic1_clk_pe0";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dmic1_dat_pe1 {
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nvidia,pins = "dmic1_dat_pe1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dmic2_clk_pe2 {
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nvidia,pins = "dmic2_clk_pe2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dmic2_dat_pe3 {
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nvidia,pins = "dmic2_dat_pe3";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dmic3_clk_pe4 {
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nvidia,pins = "dmic3_clk_pe4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dmic3_dat_pe5 {
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nvidia,pins = "dmic3_dat_pe5";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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pe6 {
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nvidia,pins = "pe6";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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pe7 {
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nvidia,pins = "pe7";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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gen3_i2c_scl_pf0 {
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nvidia,pins = "gen3_i2c_scl_pf0";
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nvidia,function = "i2c3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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nvidia,io-hv = <TEGRA_PIN_DISABLE>;
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};
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gen3_i2c_sda_pf1 {
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nvidia,pins = "gen3_i2c_sda_pf1";
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nvidia,function = "i2c3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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nvidia,io-hv = <TEGRA_PIN_DISABLE>;
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};
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uart2_tx_pg0 {
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nvidia,pins = "uart2_tx_pg0";
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nvidia,function = "uartb";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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uart2_rx_pg1 {
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nvidia,pins = "uart2_rx_pg1";
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nvidia,function = "uartb";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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uart2_rts_pg2 {
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nvidia,pins = "uart2_rts_pg2";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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uart2_cts_pg3 {
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nvidia,pins = "uart2_cts_pg3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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wifi_en_ph0 {
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nvidia,pins = "wifi_en_ph0";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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wifi_rst_ph1 {
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nvidia,pins = "wifi_rst_ph1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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wifi_wake_ap_ph2 {
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nvidia,pins = "wifi_wake_ap_ph2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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ap_wake_bt_ph3 {
|
|
nvidia,pins = "ap_wake_bt_ph3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
bt_rst_ph4 {
|
|
nvidia,pins = "bt_rst_ph4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
bt_wake_ap_ph5 {
|
|
nvidia,pins = "bt_wake_ap_ph5";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ph6 {
|
|
nvidia,pins = "ph6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ap_wake_nfc_ph7 {
|
|
nvidia,pins = "ap_wake_nfc_ph7";
|
|
nvidia,function = "rsvd0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
nfc_en_pi0 {
|
|
nvidia,pins = "nfc_en_pi0";
|
|
nvidia,function = "rsvd0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
nfc_int_pi1 {
|
|
nvidia,pins = "nfc_int_pi1";
|
|
nvidia,function = "rsvd0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gps_en_pi2 {
|
|
nvidia,pins = "gps_en_pi2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gps_rst_pi3 {
|
|
nvidia,pins = "gps_rst_pi3";
|
|
nvidia,function = "rsvd0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart4_tx_pi4 {
|
|
nvidia,pins = "uart4_tx_pi4";
|
|
nvidia,function = "uartd";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart4_rx_pi5 {
|
|
nvidia,pins = "uart4_rx_pi5";
|
|
nvidia,function = "uartd";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart4_rts_pi6 {
|
|
nvidia,pins = "uart4_rts_pi6";
|
|
nvidia,function = "uartd";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart4_cts_pi7 {
|
|
nvidia,pins = "uart4_cts_pi7";
|
|
nvidia,function = "uartd";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gen1_i2c_sda_pj0 {
|
|
nvidia,pins = "gen1_i2c_sda_pj0";
|
|
nvidia,function = "i2c1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gen1_i2c_scl_pj1 {
|
|
nvidia,pins = "gen1_i2c_scl_pj1";
|
|
nvidia,function = "i2c1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gen2_i2c_scl_pj2 {
|
|
nvidia,pins = "gen2_i2c_scl_pj2";
|
|
nvidia,function = "i2c2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gen2_i2c_sda_pj3 {
|
|
nvidia,pins = "gen2_i2c_sda_pj3";
|
|
nvidia,function = "i2c2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
dap4_fs_pj4 {
|
|
nvidia,pins = "dap4_fs_pj4";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap4_din_pj5 {
|
|
nvidia,pins = "dap4_din_pj5";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap4_dout_pj6 {
|
|
nvidia,pins = "dap4_dout_pj6";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap4_sclk_pj7 {
|
|
nvidia,pins = "dap4_sclk_pj7";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk0 {
|
|
nvidia,pins = "pk0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk1 {
|
|
nvidia,pins = "pk1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk2 {
|
|
nvidia,pins = "pk2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk3 {
|
|
nvidia,pins = "pk3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk4 {
|
|
nvidia,pins = "pk4";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk5 {
|
|
nvidia,pins = "pk5";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk6 {
|
|
nvidia,pins = "pk6";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk7 {
|
|
nvidia,pins = "pk7";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pl0 {
|
|
nvidia,pins = "pl0";
|
|
nvidia,function = "rsvd0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pl1 {
|
|
nvidia,pins = "pl1";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc1_clk_pm0 {
|
|
nvidia,pins = "sdmmc1_clk_pm0";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc1_cmd_pm1 {
|
|
nvidia,pins = "sdmmc1_cmd_pm1";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc1_dat3_pm2 {
|
|
nvidia,pins = "sdmmc1_dat3_pm2";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc1_dat2_pm3 {
|
|
nvidia,pins = "sdmmc1_dat2_pm3";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc1_dat1_pm4 {
|
|
nvidia,pins = "sdmmc1_dat1_pm4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc1_dat0_pm5 {
|
|
nvidia,pins = "sdmmc1_dat0_pm5";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc3_clk_pp0 {
|
|
nvidia,pins = "sdmmc3_clk_pp0";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc3_cmd_pp1 {
|
|
nvidia,pins = "sdmmc3_cmd_pp1";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc3_dat3_pp2 {
|
|
nvidia,pins = "sdmmc3_dat3_pp2";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc3_dat2_pp3 {
|
|
nvidia,pins = "sdmmc3_dat2_pp3";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc3_dat1_pp4 {
|
|
nvidia,pins = "sdmmc3_dat1_pp4";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc3_dat0_pp5 {
|
|
nvidia,pins = "sdmmc3_dat0_pp5";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
cam1_mclk_ps0 {
|
|
nvidia,pins = "cam1_mclk_ps0";
|
|
nvidia,function = "extperiph3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
cam2_mclk_ps1 {
|
|
nvidia,pins = "cam2_mclk_ps1";
|
|
nvidia,function = "extperiph3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
cam_i2c_scl_ps2 {
|
|
nvidia,pins = "cam_i2c_scl_ps2";
|
|
nvidia,function = "i2cvi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
cam_i2c_sda_ps3 {
|
|
nvidia,pins = "cam_i2c_sda_ps3";
|
|
nvidia,function = "i2cvi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
cam_rst_ps4 {
|
|
nvidia,pins = "cam_rst_ps4";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
cam_af_en_ps5 {
|
|
nvidia,pins = "cam_af_en_ps5";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
cam_flash_en_ps6 {
|
|
nvidia,pins = "cam_flash_en_ps6";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
cam1_pwdn_ps7 {
|
|
nvidia,pins = "cam1_pwdn_ps7";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
cam2_pwdn_pt0 {
|
|
nvidia,pins = "cam2_pwdn_pt0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
cam1_strobe_pt1 {
|
|
nvidia,pins = "cam1_strobe_pt1";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart1_tx_pu0 {
|
|
nvidia,pins = "uart1_tx_pu0";
|
|
nvidia,function = "uarta";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart1_rx_pu1 {
|
|
nvidia,pins = "uart1_rx_pu1";
|
|
nvidia,function = "uarta";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart1_rts_pu2 {
|
|
nvidia,pins = "uart1_rts_pu2";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart1_cts_pu3 {
|
|
nvidia,pins = "uart1_cts_pu3";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
lcd_bl_pwm_pv0 {
|
|
nvidia,pins = "lcd_bl_pwm_pv0";
|
|
nvidia,function = "rsvd3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
lcd_bl_en_pv1 {
|
|
nvidia,pins = "lcd_bl_en_pv1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
lcd_rst_pv2 {
|
|
nvidia,pins = "lcd_rst_pv2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
lcd_gpio1_pv3 {
|
|
nvidia,pins = "lcd_gpio1_pv3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
lcd_gpio2_pv4 {
|
|
nvidia,pins = "lcd_gpio2_pv4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ap_ready_pv5 {
|
|
nvidia,pins = "ap_ready_pv5";
|
|
nvidia,function = "rsvd0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
touch_rst_pv6 {
|
|
nvidia,pins = "touch_rst_pv6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
touch_clk_pv7 {
|
|
nvidia,pins = "touch_clk_pv7";
|
|
nvidia,function = "touch";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
modem_wake_ap_px0 {
|
|
nvidia,pins = "modem_wake_ap_px0";
|
|
nvidia,function = "rsvd0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
touch_int_px1 {
|
|
nvidia,pins = "touch_int_px1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
motion_int_px2 {
|
|
nvidia,pins = "motion_int_px2";
|
|
nvidia,function = "rsvd0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
als_prox_int_px3 {
|
|
nvidia,pins = "als_prox_int_px3";
|
|
nvidia,function = "rsvd0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
temp_alert_px4 {
|
|
nvidia,pins = "temp_alert_px4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
button_power_on_px5 {
|
|
nvidia,pins = "button_power_on_px5";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
button_vol_up_px6 {
|
|
nvidia,pins = "button_vol_up_px6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
button_vol_down_px7 {
|
|
nvidia,pins = "button_vol_down_px7";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
button_slide_sw_py0 {
|
|
nvidia,pins = "button_slide_sw_py0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
button_home_py1 {
|
|
nvidia,pins = "button_home_py1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
lcd_te_py2 {
|
|
nvidia,pins = "lcd_te_py2";
|
|
nvidia,function = "displaya";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pwr_i2c_scl_py3 {
|
|
nvidia,pins = "pwr_i2c_scl_py3";
|
|
nvidia,function = "i2cpmu";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pwr_i2c_sda_py4 {
|
|
nvidia,pins = "pwr_i2c_sda_py4";
|
|
nvidia,function = "i2cpmu";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
clk_32k_out_py5 {
|
|
nvidia,pins = "clk_32k_out_py5";
|
|
nvidia,function = "soc";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pz0 {
|
|
nvidia,pins = "pz0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pz1 {
|
|
nvidia,pins = "pz1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pz2 {
|
|
nvidia,pins = "pz2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pz3 {
|
|
nvidia,pins = "pz3";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pz4 {
|
|
nvidia,pins = "pz4";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pz5 {
|
|
nvidia,pins = "pz5";
|
|
nvidia,function = "soc";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap2_fs_paa0 {
|
|
nvidia,pins = "dap2_fs_paa0";
|
|
nvidia,function = "i2s2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap2_sclk_paa1 {
|
|
nvidia,pins = "dap2_sclk_paa1";
|
|
nvidia,function = "i2s2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap2_din_paa2 {
|
|
nvidia,pins = "dap2_din_paa2";
|
|
nvidia,function = "i2s2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap2_dout_paa3 {
|
|
nvidia,pins = "dap2_dout_paa3";
|
|
nvidia,function = "i2s2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
aud_mclk_pbb0 {
|
|
nvidia,pins = "aud_mclk_pbb0";
|
|
nvidia,function = "aud";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dvfs_pwm_pbb1 {
|
|
nvidia,pins = "dvfs_pwm_pbb1";
|
|
nvidia,function = "rsvd0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dvfs_clk_pbb2 {
|
|
nvidia,pins = "dvfs_clk_pbb2";
|
|
nvidia,function = "rsvd0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gpio_x1_aud_pbb3 {
|
|
nvidia,pins = "gpio_x1_aud_pbb3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gpio_x3_aud_pbb4 {
|
|
nvidia,pins = "gpio_x3_aud_pbb4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
hdmi_cec_pcc0 {
|
|
nvidia,pins = "hdmi_cec_pcc0";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
hdmi_int_dp_hpd_pcc1 {
|
|
nvidia,pins = "hdmi_int_dp_hpd_pcc1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
spdif_out_pcc2 {
|
|
nvidia,pins = "spdif_out_pcc2";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
spdif_in_pcc3 {
|
|
nvidia,pins = "spdif_in_pcc3";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
usb_vbus_en0_pcc4 {
|
|
nvidia,pins = "usb_vbus_en0_pcc4";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
usb_vbus_en1_pcc5 {
|
|
nvidia,pins = "usb_vbus_en1_pcc5";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dp_hpd0_pcc6 {
|
|
nvidia,pins = "dp_hpd0_pcc6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pcc7 {
|
|
nvidia,pins = "pcc7";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
spi2_cs1_pdd0 {
|
|
nvidia,pins = "spi2_cs1_pdd0";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
qspi_sck_pee0 {
|
|
nvidia,pins = "qspi_sck_pee0";
|
|
nvidia,function = "qspi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
qspi_cs_n_pee1 {
|
|
nvidia,pins = "qspi_cs_n_pee1";
|
|
nvidia,function = "qspi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
qspi_io0_pee2 {
|
|
nvidia,pins = "qspi_io0_pee2";
|
|
nvidia,function = "qspi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
qspi_io1_pee3 {
|
|
nvidia,pins = "qspi_io1_pee3";
|
|
nvidia,function = "qspi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
qspi_io2_pee4 {
|
|
nvidia,pins = "qspi_io2_pee4";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
qspi_io3_pee5 {
|
|
nvidia,pins = "qspi_io3_pee5";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
core_pwr_req {
|
|
nvidia,pins = "core_pwr_req";
|
|
nvidia,function = "core";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
cpu_pwr_req {
|
|
nvidia,pins = "cpu_pwr_req";
|
|
nvidia,function = "cpu";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pwr_int_n {
|
|
nvidia,pins = "pwr_int_n";
|
|
nvidia,function = "pmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
clk_32k_in {
|
|
nvidia,pins = "clk_32k_in";
|
|
nvidia,function = "clk";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
jtag_rtck {
|
|
nvidia,pins = "jtag_rtck";
|
|
nvidia,function = "jtag";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
clk_req {
|
|
nvidia,pins = "clk_req";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
shutdown {
|
|
nvidia,pins = "shutdown";
|
|
nvidia,function = "shutdown";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
};
|
|
};
|
|
|
|
serial@70006000 {
|
|
status = "okay";
|
|
};
|
|
|
|
i2c@7000c400 {
|
|
status = "okay";
|
|
clock-frequency = <1000000>;
|
|
|
|
ec@1e {
|
|
compatible = "google,cros-ec-i2c";
|
|
reg = <0x1e>;
|
|
interrupt-parent = <&gpio>;
|
|
interrupts = <TEGRA_GPIO(Z, 1) IRQ_TYPE_LEVEL_LOW>;
|
|
wakeup-source;
|
|
|
|
ec_i2c_0: i2c-tunnel {
|
|
compatible = "google,cros-ec-i2c-tunnel";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
google,remote-bus = <0>;
|
|
|
|
battery: bq27742@55 {
|
|
compatible = "ti,bq27742";
|
|
reg = <0x55>;
|
|
battery-name = "battery";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
i2c@7000d000 {
|
|
status = "okay";
|
|
clock-frequency = <1000000>;
|
|
|
|
max77620: max77620@3c {
|
|
compatible = "maxim,max77620";
|
|
reg = <0x3c>;
|
|
interrupts = <0 86 IRQ_TYPE_NONE>;
|
|
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&max77620_default>;
|
|
|
|
max77620_default: pinmux@0 {
|
|
pin_gpio {
|
|
pins = "gpio0", "gpio1", "gpio2", "gpio7";
|
|
function = "gpio";
|
|
};
|
|
|
|
/*
|
|
* GPIO3 is used to en_pp3300, and it is part of power
|
|
* sequence, So it must be sequenced up (automatically
|
|
* set by OTP) and down properly.
|
|
*/
|
|
pin_gpio3 {
|
|
pins = "gpio3";
|
|
function = "fps-out";
|
|
drive-open-drain = <1>;
|
|
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
|
|
maxim,active-fps-power-up-slot = <4>;
|
|
maxim,active-fps-power-down-slot = <2>;
|
|
};
|
|
|
|
pin_gpio5_6 {
|
|
pins = "gpio5", "gpio6";
|
|
function = "gpio";
|
|
drive-push-pull = <1>;
|
|
};
|
|
|
|
pin_32k {
|
|
pins = "gpio4";
|
|
function = "32k-out1";
|
|
};
|
|
};
|
|
|
|
fps {
|
|
fps0 {
|
|
maxim,shutdown-fps-time-period-us = <5120>;
|
|
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
|
|
};
|
|
|
|
fps1 {
|
|
maxim,shutdown-fps-time-period-us = <5120>;
|
|
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
|
|
maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>;
|
|
};
|
|
|
|
fps2 {
|
|
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
|
|
};
|
|
};
|
|
|
|
regulators {
|
|
in-ldo0-1-supply = <&pp1350>;
|
|
in-ldo2-supply = <&pp3300>;
|
|
in-ldo3-5-supply = <&pp3300>;
|
|
in-ldo7-8-supply = <&pp1350>;
|
|
|
|
ppvar_soc: sd0 {
|
|
regulator-name = "PPVAR_SOC";
|
|
regulator-min-microvolt = <825000>;
|
|
regulator-max-microvolt = <1125000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
|
|
maxim,active-fps-power-up-slot = <1>;
|
|
maxim,active-fps-power-down-slot = <7>;
|
|
};
|
|
|
|
pp1100_sd1: sd1 {
|
|
regulator-name = "PP1100";
|
|
regulator-min-microvolt = <1125000>;
|
|
regulator-max-microvolt = <1125000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
|
|
maxim,active-fps-power-up-slot = <5>;
|
|
maxim,active-fps-power-down-slot = <1>;
|
|
};
|
|
|
|
pp1350: sd2 {
|
|
regulator-name = "PP1350";
|
|
regulator-min-microvolt = <1350000>;
|
|
regulator-max-microvolt = <1350000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
|
|
maxim,active-fps-power-up-slot = <2>;
|
|
maxim,active-fps-power-down-slot = <5>;
|
|
};
|
|
|
|
pp1800: sd3 {
|
|
regulator-name = "PP1800";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
|
|
maxim,active-fps-power-up-slot = <3>;
|
|
maxim,active-fps-power-down-slot = <3>;
|
|
};
|
|
|
|
pp1200_avdd: ldo0 {
|
|
regulator-name = "PP1200_AVDD";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-enable-ramp-delay = <26>;
|
|
regulator-ramp-delay = <100000>;
|
|
regulator-boot-on;
|
|
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
|
|
maxim,active-fps-power-up-slot = <0>;
|
|
maxim,active-fps-power-down-slot = <7>;
|
|
};
|
|
|
|
pp1200_rcam: ldo1 {
|
|
regulator-name = "PP1200_RCAM";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-enable-ramp-delay = <22>;
|
|
regulator-ramp-delay = <100000>;
|
|
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
|
|
maxim,active-fps-power-up-slot = <0>;
|
|
maxim,active-fps-power-down-slot = <7>;
|
|
};
|
|
|
|
pp_ldo2: ldo2 {
|
|
regulator-name = "PP_LDO2";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-enable-ramp-delay = <62>;
|
|
regulator-ramp-delay = <11000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
|
|
maxim,active-fps-power-up-slot = <0>;
|
|
maxim,active-fps-power-down-slot = <7>;
|
|
};
|
|
|
|
pp2800l_rcam: ldo3 {
|
|
regulator-name = "PP2800L_RCAM";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
regulator-enable-ramp-delay = <50>;
|
|
regulator-ramp-delay = <100000>;
|
|
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
|
|
maxim,active-fps-power-up-slot = <0>;
|
|
maxim,active-fps-power-down-slot = <7>;
|
|
};
|
|
|
|
pp100_soc_rtc: ldo4 {
|
|
regulator-name = "PP1100_SOC_RTC";
|
|
regulator-min-microvolt = <850000>;
|
|
regulator-max-microvolt = <850000>;
|
|
regulator-enable-ramp-delay = <22>;
|
|
regulator-ramp-delay = <100000>;
|
|
regulator-always-on; /* Check this */
|
|
regulator-boot-on;
|
|
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
|
|
maxim,active-fps-power-up-slot = <1>;
|
|
maxim,active-fps-power-down-slot = <7>;
|
|
};
|
|
|
|
pp2800l_fcam: ldo5 {
|
|
regulator-name = "PP2800L_FCAM";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
regulator-enable-ramp-delay = <62>;
|
|
regulator-ramp-delay = <100000>;
|
|
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
|
|
maxim,active-fps-power-up-slot = <0>;
|
|
maxim,active-fps-power-down-slot = <7>;
|
|
};
|
|
|
|
ldo6 {
|
|
/* Unused. */
|
|
regulator-name = "PP_LDO6";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-enable-ramp-delay = <36>;
|
|
regulator-ramp-delay = <100000>;
|
|
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
|
|
maxim,active-fps-power-up-slot = <0>;
|
|
maxim,active-fps-power-down-slot = <7>;
|
|
};
|
|
|
|
pp1050_avdd: ldo7 {
|
|
regulator-name = "PP1050_AVDD";
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
regulator-enable-ramp-delay = <24>;
|
|
regulator-ramp-delay = <100000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
|
|
maxim,active-fps-power-up-slot = <3>;
|
|
maxim,active-fps-power-down-slot = <4>;
|
|
};
|
|
|
|
avddio_1v05: ldo8 {
|
|
regulator-name = "AVDDIO_1V05";
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
regulator-enable-ramp-delay = <22>;
|
|
regulator-ramp-delay = <100000>;
|
|
regulator-boot-on;
|
|
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
|
|
maxim,active-fps-power-up-slot = <0>;
|
|
maxim,active-fps-power-down-slot = <7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
i2c@7000d100 {
|
|
status = "okay";
|
|
clock-frequency = <400000>;
|
|
|
|
nau8825@1a {
|
|
compatible = "nuvoton,nau8825";
|
|
reg = <0x1a>;
|
|
interrupt-parent = <&gpio>;
|
|
interrupts = <TEGRA_GPIO(E, 6) IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>;
|
|
clock-names = "mclk";
|
|
|
|
nuvoton,jkdet-enable;
|
|
nuvoton,jkdet-polarity = <GPIO_ACTIVE_LOW>;
|
|
nuvoton,vref-impedance = <2>;
|
|
nuvoton,micbias-voltage = <6>;
|
|
nuvoton,sar-threshold-num = <4>;
|
|
nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>;
|
|
nuvoton,sar-hysteresis = <1>;
|
|
nuvoton,sar-voltage = <0>;
|
|
nuvoton,sar-compare-time = <0>;
|
|
nuvoton,sar-sampling-time = <0>;
|
|
nuvoton,short-key-debounce = <2>;
|
|
nuvoton,jack-insert-debounce = <7>;
|
|
nuvoton,jack-eject-debounce = <7>;
|
|
status = "okay";
|
|
};
|
|
|
|
audio-codec@2d {
|
|
compatible = "realtek,rt5677";
|
|
reg = <0x2d>;
|
|
interrupt-parent = <&gpio>;
|
|
interrupts = <TEGRA_GPIO(X, 0) IRQ_TYPE_LEVEL_HIGH>;
|
|
realtek,reset-gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_LOW>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
pmc@7000e400 {
|
|
nvidia,invert-interrupt;
|
|
nvidia,suspend-mode = <0>;
|
|
nvidia,cpu-pwr-good-time = <0>;
|
|
nvidia,cpu-pwr-off-time = <0>;
|
|
nvidia,core-pwr-good-time = <12000 6000>;
|
|
nvidia,core-pwr-off-time = <39053>;
|
|
nvidia,core-power-req-active-high;
|
|
nvidia,sys-clock-req-active-high;
|
|
status = "okay";
|
|
};
|
|
|
|
usb@70090000 {
|
|
phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
|
|
<&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
|
|
phy-names = "usb2-0", "usb3-0";
|
|
|
|
dvddio-pex-supply = <&avddio_1v05>;
|
|
hvddio-pex-supply = <&pp1800>;
|
|
avdd-usb-supply = <&pp3300>;
|
|
avdd-pll-utmip-supply = <&pp1800>;
|
|
avdd-pll-uerefe-supply = <&pp1050_avdd>;
|
|
dvdd-pex-pll-supply = <&avddio_1v05>;
|
|
hvdd-pex-pll-e-supply = <&pp1800>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
padctl@7009f000 {
|
|
status = "okay";
|
|
|
|
pads {
|
|
usb2 {
|
|
status = "okay";
|
|
|
|
lanes {
|
|
usb2-0 {
|
|
nvidia,function = "xusb";
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
pcie {
|
|
status = "okay";
|
|
|
|
lanes {
|
|
pcie-6 {
|
|
nvidia,function = "usb3-ss";
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ports {
|
|
usb2-0 {
|
|
status = "okay";
|
|
vbus-supply = <&usbc_vbus>;
|
|
mode = "otg";
|
|
};
|
|
|
|
usb3-0 {
|
|
nvidia,usb2-companion = <0>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
sdhci@700b0600 {
|
|
bus-width = <8>;
|
|
non-removable;
|
|
status = "okay";
|
|
};
|
|
|
|
aconnect@702c0000 {
|
|
status = "okay";
|
|
|
|
dma@702e2000 {
|
|
status = "okay";
|
|
};
|
|
|
|
agic@702f9000 {
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
clk32k_in: clock@0 {
|
|
compatible = "fixed-clock";
|
|
reg = <0>;
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
cpu@0 {
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@1 {
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@2 {
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@3 {
|
|
enable-method = "psci";
|
|
};
|
|
};
|
|
|
|
gpio-keys {
|
|
compatible = "gpio-keys";
|
|
gpio-keys,name = "gpio-keys";
|
|
|
|
power {
|
|
label = "Power";
|
|
gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_POWER>;
|
|
debounce-interval = <30>;
|
|
wakeup-source;
|
|
};
|
|
|
|
lid {
|
|
label = "Lid";
|
|
gpios = <&gpio TEGRA_GPIO(B, 4) GPIO_ACTIVE_LOW>;
|
|
linux,input-type = <EV_SW>;
|
|
linux,code = <SW_LID>;
|
|
wakeup-source;
|
|
};
|
|
|
|
tablet_mode {
|
|
label = "Tablet Mode";
|
|
gpios = <&gpio TEGRA_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
|
|
linux,input-type = <EV_SW>;
|
|
linux,code = <SW_TABLET_MODE>;
|
|
wakeup-source;
|
|
};
|
|
|
|
volume_down {
|
|
label = "Volume Down";
|
|
gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_VOLUMEDOWN>;
|
|
};
|
|
|
|
volume_up {
|
|
label = "Volume Up";
|
|
gpios = <&gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_VOLUMEUP>;
|
|
};
|
|
};
|
|
|
|
max98357a {
|
|
compatible = "maxim,max98357a";
|
|
status = "okay";
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
regulators {
|
|
compatible = "simple-bus";
|
|
device_type = "fixed-regulators";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ppvar_sys: regulator@0 {
|
|
compatible = "regulator-fixed";
|
|
reg = <0>;
|
|
regulator-name = "PPVAR_SYS";
|
|
regulator-min-microvolt = <4400000>;
|
|
regulator-max-microvolt = <4400000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
pplcd_vdd: regulator@1 {
|
|
compatible = "regulator-fixed";
|
|
reg = <1>;
|
|
regulator-name = "PPLCD_VDD";
|
|
regulator-min-microvolt = <4400000>;
|
|
regulator-max-microvolt = <4400000>;
|
|
gpio = <&gpio TEGRA_GPIO(V, 4) 0>;
|
|
enable-active-high;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
pp3000_always: regulator@2 {
|
|
compatible = "regulator-fixed";
|
|
reg = <2>;
|
|
regulator-name = "PP3000_ALWAYS";
|
|
regulator-min-microvolt = <3000000>;
|
|
regulator-max-microvolt = <3000000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
pp3300: regulator@3 {
|
|
compatible = "regulator-fixed";
|
|
reg = <3>;
|
|
regulator-name = "PP3300";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
enable-active-high;
|
|
};
|
|
|
|
pp5000: regulator@4 {
|
|
compatible = "regulator-fixed";
|
|
reg = <4>;
|
|
regulator-name = "PP5000";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
pp1800_lcdio: regulator@5 {
|
|
compatible = "regulator-fixed";
|
|
reg = <5>;
|
|
regulator-name = "PP1800_LCDIO";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
gpio = <&gpio TEGRA_GPIO(V, 3) 0>;
|
|
enable-active-high;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
pp1800_cam: regulator@6 {
|
|
compatible = "regulator-fixed";
|
|
reg= <6>;
|
|
regulator-name = "PP1800_CAM";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
gpio = <&gpio TEGRA_GPIO(K, 3) 0>;
|
|
enable-active-high;
|
|
};
|
|
|
|
usbc_vbus: regulator@7 {
|
|
compatible = "regulator-fixed";
|
|
reg = <7>;
|
|
regulator-name = "USBC_VBUS";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
};
|
|
};
|
|
};
|