329 lines
7.9 KiB
C
329 lines
7.9 KiB
C
/*
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* SMP support for SoCs with APMU
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/cpu_pm.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include <linux/suspend.h>
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#include <linux/threads.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/proc-fns.h>
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#include <asm/smp_plat.h>
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#include <asm/suspend.h>
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#include "common.h"
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#include "platsmp-apmu.h"
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#include "rcar-gen2.h"
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static struct {
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void __iomem *iomem;
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int bit;
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} apmu_cpus[NR_CPUS];
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#define WUPCR_OFFS 0x10 /* Wake Up Control Register */
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#define PSTR_OFFS 0x40 /* Power Status Register */
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#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n)))
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/* CPUn Power Status Control Register */
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#define DBGRCR_OFFS 0x180 /* Debug Resource Reset Control Reg. */
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/* Power Status Register */
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#define CPUNST(r, n) (((r) >> (n * 4)) & 3) /* CPUn Status Bit */
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#define CPUST_RUN 0 /* Run Mode */
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#define CPUST_STANDBY 3 /* CoreStandby Mode */
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/* Debug Resource Reset Control Register */
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#define DBGCPUREN BIT(24) /* CPU Other Reset Request Enable */
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#define DBGCPUNREN(n) BIT((n) + 20) /* CPUn Reset Request Enable */
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#define DBGCPUPREN BIT(19) /* CPU Peripheral Reset Req. Enable */
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static int __maybe_unused apmu_power_on(void __iomem *p, int bit)
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{
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/* request power on */
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writel_relaxed(BIT(bit), p + WUPCR_OFFS);
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/* wait for APMU to finish */
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while (readl_relaxed(p + WUPCR_OFFS) != 0)
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;
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return 0;
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}
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static int __maybe_unused apmu_power_off(void __iomem *p, int bit)
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{
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/* request Core Standby for next WFI */
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writel_relaxed(3, p + CPUNCR_OFFS(bit));
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return 0;
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}
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static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit)
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{
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int k;
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for (k = 0; k < 1000; k++) {
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if (CPUNST(readl_relaxed(p + PSTR_OFFS), bit) == CPUST_STANDBY)
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return 1;
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mdelay(1);
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}
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return 0;
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}
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static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu))
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{
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void __iomem *p = apmu_cpus[cpu].iomem;
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return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL;
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}
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#ifdef CONFIG_SMP
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static void apmu_init_cpu(struct resource *res, int cpu, int bit)
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{
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u32 x;
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if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem)
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return;
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apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res));
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apmu_cpus[cpu].bit = bit;
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pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res);
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/* Setup for debug mode */
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x = readl(apmu_cpus[cpu].iomem + DBGRCR_OFFS);
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x |= DBGCPUREN | DBGCPUNREN(bit) | DBGCPUPREN;
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writel(x, apmu_cpus[cpu].iomem + DBGRCR_OFFS);
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}
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static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit),
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struct rcar_apmu_config *apmu_config, int num)
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{
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int id;
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int k;
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int bit, index;
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bool is_allowed;
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for (k = 0; k < num; k++) {
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/* only enable the cluster that includes the boot CPU */
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is_allowed = false;
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for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
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id = apmu_config[k].cpus[bit];
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if (id >= 0) {
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if (id == cpu_logical_map(0))
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is_allowed = true;
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}
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}
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if (!is_allowed)
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continue;
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for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
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id = apmu_config[k].cpus[bit];
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if (id >= 0) {
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index = get_logical_index(id);
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if (index >= 0)
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fn(&apmu_config[k].iomem, index, bit);
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}
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}
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}
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}
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static const struct of_device_id apmu_ids[] = {
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{ .compatible = "renesas,apmu" },
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{ /*sentinel*/ }
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};
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static void apmu_parse_dt(void (*fn)(struct resource *res, int cpu, int bit))
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{
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struct device_node *np_apmu, *np_cpu;
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struct resource res;
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int bit, index;
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u32 id;
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for_each_matching_node(np_apmu, apmu_ids) {
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/* only enable the cluster that includes the boot CPU */
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bool is_allowed = false;
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for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
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np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
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if (np_cpu) {
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if (!of_property_read_u32(np_cpu, "reg", &id)) {
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if (id == cpu_logical_map(0)) {
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is_allowed = true;
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of_node_put(np_cpu);
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break;
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}
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}
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of_node_put(np_cpu);
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}
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}
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if (!is_allowed)
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continue;
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for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
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np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
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if (np_cpu) {
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if (!of_property_read_u32(np_cpu, "reg", &id)) {
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index = get_logical_index(id);
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if ((index >= 0) &&
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!of_address_to_resource(np_apmu,
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0, &res))
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fn(&res, index, bit);
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}
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of_node_put(np_cpu);
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}
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}
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}
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}
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static void __init shmobile_smp_apmu_setup_boot(void)
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{
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/* install boot code shared by all CPUs */
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shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
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}
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void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
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struct rcar_apmu_config *apmu_config,
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int num)
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{
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shmobile_smp_apmu_setup_boot();
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apmu_parse_cfg(apmu_init_cpu, apmu_config, num);
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}
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int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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/* For this particular CPU register boot vector */
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shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_apmu), 0);
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return apmu_wrap(cpu, apmu_power_on);
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}
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static void __init shmobile_smp_apmu_prepare_cpus_dt(unsigned int max_cpus)
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{
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shmobile_smp_apmu_setup_boot();
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apmu_parse_dt(apmu_init_cpu);
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rcar_gen2_pm_init();
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}
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static struct smp_operations apmu_smp_ops __initdata = {
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.smp_prepare_cpus = shmobile_smp_apmu_prepare_cpus_dt,
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.smp_boot_secondary = shmobile_smp_apmu_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_can_disable = shmobile_smp_cpu_can_disable,
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.cpu_die = shmobile_smp_apmu_cpu_die,
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.cpu_kill = shmobile_smp_apmu_cpu_kill,
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#endif
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};
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CPU_METHOD_OF_DECLARE(shmobile_smp_apmu, "renesas,apmu", &apmu_smp_ops);
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#endif /* CONFIG_SMP */
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#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_SUSPEND)
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/* nicked from arch/arm/mach-exynos/hotplug.c */
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static inline void cpu_enter_lowpower_a15(void)
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{
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unsigned int v;
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asm volatile(
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" mrc p15, 0, %0, c1, c0, 0\n"
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" bic %0, %0, %1\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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: "=&r" (v)
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: "Ir" (CR_C)
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: "cc");
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flush_cache_louis();
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asm volatile(
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/*
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* Turn off coherency
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*/
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" mrc p15, 0, %0, c1, c0, 1\n"
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" bic %0, %0, %1\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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: "=&r" (v)
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: "Ir" (0x40)
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: "cc");
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isb();
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dsb();
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}
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static void shmobile_smp_apmu_cpu_shutdown(unsigned int cpu)
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{
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/* Select next sleep mode using the APMU */
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apmu_wrap(cpu, apmu_power_off);
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/* Do ARM specific CPU shutdown */
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cpu_enter_lowpower_a15();
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}
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static inline void cpu_leave_lowpower(void)
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{
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unsigned int v;
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asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
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" orr %0, %0, %1\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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" mrc p15, 0, %0, c1, c0, 1\n"
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" orr %0, %0, %2\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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: "=&r" (v)
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: "Ir" (CR_C), "Ir" (0x40)
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: "cc");
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}
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#endif
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#if defined(CONFIG_HOTPLUG_CPU)
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void shmobile_smp_apmu_cpu_die(unsigned int cpu)
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{
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/* For this particular CPU deregister boot vector */
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shmobile_smp_hook(cpu, 0, 0);
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/* Shutdown CPU core */
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shmobile_smp_apmu_cpu_shutdown(cpu);
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/* jump to shared mach-shmobile sleep / reset code */
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shmobile_smp_sleep();
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}
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int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
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{
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return apmu_wrap(cpu, apmu_power_off_poll);
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}
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#endif
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#if defined(CONFIG_SUSPEND)
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static int shmobile_smp_apmu_do_suspend(unsigned long cpu)
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{
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shmobile_smp_hook(cpu, __pa_symbol(cpu_resume), 0);
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shmobile_smp_apmu_cpu_shutdown(cpu);
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cpu_do_idle(); /* WFI selects Core Standby */
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return 1;
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}
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static int shmobile_smp_apmu_enter_suspend(suspend_state_t state)
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{
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cpu_suspend(smp_processor_id(), shmobile_smp_apmu_do_suspend);
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cpu_leave_lowpower();
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return 0;
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}
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void __init shmobile_smp_apmu_suspend_init(void)
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{
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shmobile_suspend_ops.enter = shmobile_smp_apmu_enter_suspend;
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}
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#endif
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