369 lines
8.7 KiB
C
369 lines
8.7 KiB
C
/*
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* Broadcom STB CPU SMP and hotplug support for ARM
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*
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* Copyright (C) 2013-2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/printk.h>
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#include <linux/regmap.h>
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#include <linux/smp.h>
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#include <linux/mfd/syscon.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/mach-types.h>
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#include <asm/smp_plat.h>
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enum {
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ZONE_MAN_CLKEN_MASK = BIT(0),
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ZONE_MAN_RESET_CNTL_MASK = BIT(1),
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ZONE_MAN_MEM_PWR_MASK = BIT(4),
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ZONE_RESERVED_1_MASK = BIT(5),
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ZONE_MAN_ISO_CNTL_MASK = BIT(6),
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ZONE_MANUAL_CONTROL_MASK = BIT(7),
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ZONE_PWR_DN_REQ_MASK = BIT(9),
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ZONE_PWR_UP_REQ_MASK = BIT(10),
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ZONE_BLK_RST_ASSERT_MASK = BIT(12),
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ZONE_PWR_OFF_STATE_MASK = BIT(25),
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ZONE_PWR_ON_STATE_MASK = BIT(26),
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ZONE_DPG_PWR_STATE_MASK = BIT(28),
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ZONE_MEM_PWR_STATE_MASK = BIT(29),
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ZONE_RESET_STATE_MASK = BIT(31),
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CPU0_PWR_ZONE_CTRL_REG = 1,
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CPU_RESET_CONFIG_REG = 2,
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};
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static void __iomem *cpubiuctrl_block;
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static void __iomem *hif_cont_block;
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static u32 cpu0_pwr_zone_ctrl_reg;
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static u32 cpu_rst_cfg_reg;
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static u32 hif_cont_reg;
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#ifdef CONFIG_HOTPLUG_CPU
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/*
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* We must quiesce a dying CPU before it can be killed by the boot CPU. Because
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* one or more cache may be disabled, we must flush to ensure coherency. We
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* cannot use traditionl completion structures or spinlocks as they rely on
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* coherency.
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*/
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static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
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static int per_cpu_sw_state_rd(u32 cpu)
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{
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sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
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return per_cpu(per_cpu_sw_state, cpu);
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}
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static void per_cpu_sw_state_wr(u32 cpu, int val)
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{
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dmb();
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per_cpu(per_cpu_sw_state, cpu) = val;
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sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
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}
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#else
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static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
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#endif
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static void __iomem *pwr_ctrl_get_base(u32 cpu)
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{
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void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
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base += (cpu_logical_map(cpu) * 4);
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return base;
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}
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static u32 pwr_ctrl_rd(u32 cpu)
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{
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void __iomem *base = pwr_ctrl_get_base(cpu);
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return readl_relaxed(base);
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}
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static void pwr_ctrl_set(unsigned int cpu, u32 val, u32 mask)
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{
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void __iomem *base = pwr_ctrl_get_base(cpu);
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writel((readl(base) & mask) | val, base);
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}
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static void pwr_ctrl_clr(unsigned int cpu, u32 val, u32 mask)
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{
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void __iomem *base = pwr_ctrl_get_base(cpu);
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writel((readl(base) & mask) & ~val, base);
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}
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#define POLL_TMOUT_MS 500
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static int pwr_ctrl_wait_tmout(unsigned int cpu, u32 set, u32 mask)
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{
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const unsigned long timeo = jiffies + msecs_to_jiffies(POLL_TMOUT_MS);
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u32 tmp;
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do {
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tmp = pwr_ctrl_rd(cpu) & mask;
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if (!set == !tmp)
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return 0;
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} while (time_before(jiffies, timeo));
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tmp = pwr_ctrl_rd(cpu) & mask;
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if (!set == !tmp)
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return 0;
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return -ETIMEDOUT;
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}
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static void cpu_rst_cfg_set(u32 cpu, int set)
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{
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u32 val;
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val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
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if (set)
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val |= BIT(cpu_logical_map(cpu));
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else
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val &= ~BIT(cpu_logical_map(cpu));
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writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
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}
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static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
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{
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const int reg_ofs = cpu_logical_map(cpu) * 8;
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writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
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writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
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}
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static void brcmstb_cpu_boot(u32 cpu)
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{
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/* Mark this CPU as "up" */
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per_cpu_sw_state_wr(cpu, 1);
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/*
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* Set the reset vector to point to the secondary_startup
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* routine
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*/
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cpu_set_boot_addr(cpu, __pa_symbol(secondary_startup));
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/* Unhalt the cpu */
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cpu_rst_cfg_set(cpu, 0);
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}
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static void brcmstb_cpu_power_on(u32 cpu)
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{
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/*
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* The secondary cores power was cut, so we must go through
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* power-on initialization.
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*/
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pwr_ctrl_set(cpu, ZONE_MAN_ISO_CNTL_MASK, 0xffffff00);
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pwr_ctrl_set(cpu, ZONE_MANUAL_CONTROL_MASK, -1);
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pwr_ctrl_set(cpu, ZONE_RESERVED_1_MASK, -1);
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pwr_ctrl_set(cpu, ZONE_MAN_MEM_PWR_MASK, -1);
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if (pwr_ctrl_wait_tmout(cpu, 1, ZONE_MEM_PWR_STATE_MASK))
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panic("ZONE_MEM_PWR_STATE_MASK set timeout");
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pwr_ctrl_set(cpu, ZONE_MAN_CLKEN_MASK, -1);
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if (pwr_ctrl_wait_tmout(cpu, 1, ZONE_DPG_PWR_STATE_MASK))
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panic("ZONE_DPG_PWR_STATE_MASK set timeout");
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pwr_ctrl_clr(cpu, ZONE_MAN_ISO_CNTL_MASK, -1);
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pwr_ctrl_set(cpu, ZONE_MAN_RESET_CNTL_MASK, -1);
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}
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static int brcmstb_cpu_get_power_state(u32 cpu)
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{
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int tmp = pwr_ctrl_rd(cpu);
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return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static void brcmstb_cpu_die(u32 cpu)
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{
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v7_exit_coherency_flush(all);
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per_cpu_sw_state_wr(cpu, 0);
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/* Sit and wait to die */
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wfi();
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/* We should never get here... */
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while (1)
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;
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}
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static int brcmstb_cpu_kill(u32 cpu)
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{
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/*
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* Ordinarily, the hardware forbids power-down of CPU0 (which is good
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* because it is the boot CPU), but this is not true when using BPCM
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* manual mode. Consequently, we must avoid turning off CPU0 here to
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* ensure that TI2C master reset will work.
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*/
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if (cpu == 0) {
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pr_warn("SMP: refusing to power off CPU0\n");
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return 1;
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}
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while (per_cpu_sw_state_rd(cpu))
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;
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pwr_ctrl_set(cpu, ZONE_MANUAL_CONTROL_MASK, -1);
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pwr_ctrl_clr(cpu, ZONE_MAN_RESET_CNTL_MASK, -1);
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pwr_ctrl_clr(cpu, ZONE_MAN_CLKEN_MASK, -1);
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pwr_ctrl_set(cpu, ZONE_MAN_ISO_CNTL_MASK, -1);
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pwr_ctrl_clr(cpu, ZONE_MAN_MEM_PWR_MASK, -1);
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if (pwr_ctrl_wait_tmout(cpu, 0, ZONE_MEM_PWR_STATE_MASK))
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panic("ZONE_MEM_PWR_STATE_MASK clear timeout");
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pwr_ctrl_clr(cpu, ZONE_RESERVED_1_MASK, -1);
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if (pwr_ctrl_wait_tmout(cpu, 0, ZONE_DPG_PWR_STATE_MASK))
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panic("ZONE_DPG_PWR_STATE_MASK clear timeout");
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/* Flush pipeline before resetting CPU */
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mb();
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/* Assert reset on the CPU */
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cpu_rst_cfg_set(cpu, 1);
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return 1;
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}
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#endif /* CONFIG_HOTPLUG_CPU */
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static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
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{
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int rc = 0;
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char *name;
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struct device_node *syscon_np = NULL;
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name = "syscon-cpu";
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syscon_np = of_parse_phandle(np, name, 0);
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if (!syscon_np) {
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pr_err("can't find phandle %s\n", name);
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rc = -EINVAL;
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goto cleanup;
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}
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cpubiuctrl_block = of_iomap(syscon_np, 0);
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if (!cpubiuctrl_block) {
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pr_err("iomap failed for cpubiuctrl_block\n");
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rc = -EINVAL;
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goto cleanup;
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}
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rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
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&cpu0_pwr_zone_ctrl_reg);
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if (rc) {
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pr_err("failed to read 1st entry from %s property (%d)\n", name,
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rc);
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rc = -EINVAL;
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goto cleanup;
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}
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rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
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&cpu_rst_cfg_reg);
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if (rc) {
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pr_err("failed to read 2nd entry from %s property (%d)\n", name,
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rc);
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rc = -EINVAL;
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goto cleanup;
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}
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cleanup:
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of_node_put(syscon_np);
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return rc;
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}
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static int __init setup_hifcont_regs(struct device_node *np)
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{
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int rc = 0;
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char *name;
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struct device_node *syscon_np = NULL;
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name = "syscon-cont";
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syscon_np = of_parse_phandle(np, name, 0);
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if (!syscon_np) {
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pr_err("can't find phandle %s\n", name);
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rc = -EINVAL;
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goto cleanup;
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}
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hif_cont_block = of_iomap(syscon_np, 0);
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if (!hif_cont_block) {
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pr_err("iomap failed for hif_cont_block\n");
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rc = -EINVAL;
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goto cleanup;
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}
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/* Offset is at top of hif_cont_block */
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hif_cont_reg = 0;
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cleanup:
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of_node_put(syscon_np);
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return rc;
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}
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static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
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{
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int rc;
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struct device_node *np;
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char *name;
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name = "brcm,brcmstb-smpboot";
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np = of_find_compatible_node(NULL, NULL, name);
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if (!np) {
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pr_err("can't find compatible node %s\n", name);
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return;
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}
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rc = setup_hifcpubiuctrl_regs(np);
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if (rc)
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return;
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rc = setup_hifcont_regs(np);
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if (rc)
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return;
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}
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static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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/* Missing the brcm,brcmstb-smpboot DT node? */
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if (!cpubiuctrl_block || !hif_cont_block)
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return -ENODEV;
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/* Bring up power to the core if necessary */
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if (brcmstb_cpu_get_power_state(cpu) == 0)
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brcmstb_cpu_power_on(cpu);
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brcmstb_cpu_boot(cpu);
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return 0;
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}
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static const struct smp_operations brcmstb_smp_ops __initconst = {
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.smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
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.smp_boot_secondary = brcmstb_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_kill = brcmstb_cpu_kill,
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.cpu_die = brcmstb_cpu_die,
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#endif
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};
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CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);
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