391 lines
8.5 KiB
Plaintext
391 lines
8.5 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
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/*
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* Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
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*/
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#include <dt-bindings/clock/suniv-ccu.h>
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#include <dt-bindings/reset/suniv-ccu.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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lradc: lradc@1c23400 {
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compatible = "allwinner,sun4i-a10-lradc-keys";
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reg = <0x01c23400 0x400>;
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interrupts = <22>;
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status = "disabled";
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: clk-24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: clk-32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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fake100M: clk-100M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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clock-output-names = "fake-100M";
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};
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};
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cpus {
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#address-cells = <0>;
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#size-cells = <0>;
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cpu {
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compatible = "arm,arm926ej-s";
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device_type = "cpu";
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};
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};
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de: display-engine {
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compatible = "allwinner,suniv-display-engine";
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allwinner,pipelines = <&fe0>;
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status = "disabled";
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram-controller@1c00000 {
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compatible = "allwinner,sun4i-a10-sram-controller";
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reg = <0x01c00000 0x30>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_d: sram@10000 {
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compatible = "mmio-sram";
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reg = <0x00010000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00010000 0x1000>;
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otg_sram: sram-section@0 {
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compatible = "allwinner,sun4i-a10-sram-d";
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reg = <0x0000 0x1000>;
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status = "disabled";
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};
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};
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};
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spi0: spi@1c05000 {
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compatible = "allwinner,suniv-spi",
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"allwinner,sun8i-h3-spi";
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reg = <0x01c05000 0x1000>;
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interrupts = <10>;
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clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
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clock-names = "ahb", "mod";
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resets = <&ccu RST_BUS_SPI0>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@1c06000 {
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compatible = "allwinner,suniv-spi",
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"allwinner,sun8i-h3-spi";
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reg = <0x01c06000 0x1000>;
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interrupts = <11>;
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clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
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clock-names = "ahb", "mod";
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resets = <&ccu RST_BUS_SPI1>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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tcon0: lcd-controller@1c0c000 {
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compatible = "allwinner,suniv-tcon";
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reg = <0x01c0c000 0x1000>;
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interrupts = <29>;
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clocks = <&ccu CLK_BUS_LCD>,
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<&ccu CLK_TCON>,
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<&osc24M>; /* Still unknown */
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clock-names = "ahb",
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"tcon-ch0",
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"tcon-ch1";
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clock-output-names = "tcon-pixel-clock";
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resets = <&ccu RST_BUS_LCD>;
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reset-names = "lcd";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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tcon0_in_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_out_tcon0>;
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};
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};
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tcon0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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};
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};
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,suniv-mmc",
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"allwinner,sun7i-a20-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC0>,
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<&ccu CLK_MMC0>,
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<&ccu CLK_MMC0_OUTPUT>,
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<&ccu CLK_MMC0_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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interrupts = <23>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@1c10000 {
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compatible = "allwinner,suniv-mmc",
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"allwinner,sun7i-a20-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC1>,
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<&ccu CLK_MMC1>,
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<&ccu CLK_MMC1_OUTPUT>,
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<&ccu CLK_MMC1_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <24>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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ccu: clock@1c20000 {
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compatible = "allwinner,suniv-ccu";
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc32k>;
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clock-names = "hosc", "losc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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intc: interrupt-controller@1c20400 {
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compatible = "allwinner,suniv-ic";
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reg = <0x01c20400 0x400>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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pio: pinctrl@1c20800 {
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compatible = "allwinner,suniv-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <38>, <39>, <40>;
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clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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#gpio-cells = <3>;
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spi0_pins_a: spi0-pins-pc {
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pins = "PC0", "PC1", "PC2", "PC3";
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function = "spi0";
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};
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lcd_rgb666_pins: lcd-rgb666-pins {
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pins = "PD0", "PD1", "PD2", "PD3", "PD4",
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"PD5", "PD6", "PD7", "PD8", "PD9",
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"PD10", "PD11", "PD12", "PD13", "PD14",
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"PD15", "PD16", "PD17", "PD18", "PD19",
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"PD20", "PD21";
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function = "lcd";
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};
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uart0_pins_a: uart-pins-pe {
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pins = "PE0", "PE1";
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function = "uart0";
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};
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
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function = "mmc0";
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};
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};
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timer@1c20c00 {
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compatible = "allwinner,suniv-timer";
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reg = <0x01c20c00 0x90>;
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interrupts = <13>;
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clocks = <&osc24M>;
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};
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wdt: watchdog@1c20ca0 {
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compatible = "allwinner,sun6i-a31-wdt";
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reg = <0x01c20ca0 0x20>;
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};
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uart0: serial@1c25000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c25000 0x400>;
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interrupts = <1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART0>;
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resets = <&ccu RST_BUS_UART0>;
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status = "disabled";
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};
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uart1: serial@1c25400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c25400 0x400>;
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interrupts = <2>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART1>;
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resets = <&ccu RST_BUS_UART1>;
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status = "disabled";
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};
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uart2: serial@1c25800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c25800 0x400>;
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interrupts = <3>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART2>;
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resets = <&ccu RST_BUS_UART2>;
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status = "disabled";
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};
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usb_otg: usb@1c13000 {
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compatible = "allwinner,suniv-musb";
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reg = <0x01c13000 0x0400>;
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clocks = <&ccu CLK_BUS_OTG>;
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resets = <&ccu RST_BUS_OTG>;
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interrupts = <26>;
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interrupt-names = "mc";
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phys = <&usbphy 0>;
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phy-names = "usb";
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extcon = <&usbphy 0>;
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allwinner,sram = <&otg_sram 1>;
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status = "disabled";
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};
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usbphy: phy@1c13400 {
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compatible = "allwinner,suniv-usb-phy";
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reg = <0x01c13400 0x10>;
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reg-names = "phy_ctrl";
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clocks = <&ccu CLK_USB_PHY0>;
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clock-names = "usb0_phy";
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resets = <&ccu RST_USB_PHY0>;
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reset-names = "usb0_reset";
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#phy-cells = <1>;
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status = "disabled";
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};
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fe0: display-frontend@1e00000 {
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compatible = "allwinner,suniv-display-frontend";
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reg = <0x01e00000 0x20000>;
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interrupts = <30>;
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clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
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<&ccu CLK_DRAM_DE_FE>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&ccu RST_BUS_DE_FE>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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fe0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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fe0_out_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_in_fe0>;
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};
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};
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};
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};
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be0: display-backend@1e60000 {
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compatible = "allwinner,suniv-display-backend";
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reg = <0x01e60000 0x10000>;
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reg-names = "be";
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interrupts = <31>;
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clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_DRAM_DE_BE>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&ccu RST_BUS_DE_BE>;
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reset-names = "be";
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assigned-clocks = <&ccu CLK_DE_BE>;
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assigned-clock-rates = <300000000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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be0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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be0_in_fe0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&fe0_out_be0>;
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};
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};
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be0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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be0_out_tcon0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&tcon0_in_be0>;
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};
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};
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};
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};
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};
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};
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