141 lines
4.1 KiB
Plaintext
141 lines
4.1 KiB
Plaintext
MediaTek T-PHY binding
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--------------------------
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T-phy controller supports physical layer functionality for a number of
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controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
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Required properties (controller (parent) node):
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- compatible : should be one of
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"mediatek,generic-tphy-v1"
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"mediatek,generic-tphy-v2"
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"mediatek,mt2701-u3phy" (deprecated)
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"mediatek,mt2712-u3phy" (deprecated)
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"mediatek,mt8173-u3phy";
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make use of "mediatek,generic-tphy-v1" on mt2701 instead and
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"mediatek,generic-tphy-v2" on mt2712 instead.
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- clocks : (deprecated, use port's clocks instead) a list of phandle +
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clock-specifier pairs, one for each entry in clock-names
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- clock-names : (deprecated, use port's one instead) must contain
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"u3phya_ref": for reference clock of usb3.0 analog phy.
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Required nodes : a sub-node is required for each port the controller
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provides. Address range information including the usual
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'reg' property is used inside these nodes to describe
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the controller's topology.
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Optional properties (controller (parent) node):
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- reg : offset and length of register shared by multiple ports,
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exclude port's private register. It is needed on mt2701
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and mt8173, but not on mt2712.
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Required properties (port (child) node):
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- reg : address and length of the register set for the port.
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- clocks : a list of phandle + clock-specifier pairs, one for each
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entry in clock-names
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- clock-names : must contain
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"ref": 48M reference clock for HighSpeed analog phy; and 26M
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reference clock for SuperSpeed analog phy, sometimes is
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24M, 25M or 27M, depended on platform.
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- #phy-cells : should be 1 (See second example)
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cell after port phandle is phy type from:
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- PHY_TYPE_USB2
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- PHY_TYPE_USB3
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- PHY_TYPE_PCIE
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- PHY_TYPE_SATA
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Example:
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u3phy: usb-phy@11290000 {
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compatible = "mediatek,mt8173-u3phy";
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reg = <0 0x11290000 0 0x800>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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u2port0: usb-phy@11290800 {
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reg = <0 0x11290800 0 0x100>;
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clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
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clock-names = "ref";
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#phy-cells = <1>;
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};
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u3port0: usb-phy@11290900 {
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reg = <0 0x11290800 0 0x700>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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};
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u2port1: usb-phy@11291000 {
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reg = <0 0x11291000 0 0x100>;
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clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
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clock-names = "ref";
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#phy-cells = <1>;
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};
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};
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Specifying phy control of devices
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---------------------------------
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Device nodes should specify the configuration required in their "phys"
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property, containing a phandle to the phy port node and a device type;
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phy-names for each port are optional.
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Example:
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#include <dt-bindings/phy/phy.h>
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usb30: usb@11270000 {
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...
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phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
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phy-names = "usb2-0", "usb3-0";
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...
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};
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Layout differences of banks between mt8173/mt2701 and mt2712
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-------------------------------------------------------------
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mt8173 and mt2701:
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port offset bank
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shared 0x0000 SPLLC
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0x0100 FMREG
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u2 port0 0x0800 U2PHY_COM
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u3 port0 0x0900 U3PHYD
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0x0a00 U3PHYD_BANK2
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0x0b00 U3PHYA
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0x0c00 U3PHYA_DA
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u2 port1 0x1000 U2PHY_COM
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u3 port1 0x1100 U3PHYD
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0x1200 U3PHYD_BANK2
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0x1300 U3PHYA
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0x1400 U3PHYA_DA
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u2 port2 0x1800 U2PHY_COM
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...
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mt2712:
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port offset bank
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u2 port0 0x0000 MISC
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0x0100 FMREG
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0x0300 U2PHY_COM
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u3 port0 0x0700 SPLLC
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0x0800 CHIP
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0x0900 U3PHYD
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0x0a00 U3PHYD_BANK2
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0x0b00 U3PHYA
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0x0c00 U3PHYA_DA
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u2 port1 0x1000 MISC
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0x1100 FMREG
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0x1300 U2PHY_COM
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u3 port1 0x1700 SPLLC
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0x1800 CHIP
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0x1900 U3PHYD
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0x1a00 U3PHYD_BANK2
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0x1b00 U3PHYA
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0x1c00 U3PHYA_DA
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u2 port2 0x2000 MISC
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...
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SPLLC shared by u3 ports and FMREG shared by u2 ports on
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mt8173/mt2701 are put back into each port; a new bank MISC for
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u2 ports and CHIP for u3 ports are added on mt2712.
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