734 lines
14 KiB
Plaintext
734 lines
14 KiB
Plaintext
Device tree binding for NVIDIA Tegra XUSB pad controller
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========================================================
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The Tegra XUSB pad controller manages a set of I/O lanes (with differential
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signals) which connect directly to pins/pads on the SoC package. Each lane
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is controlled by a HW block referred to as a "pad" in the Tegra hardware
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documentation. Each such "pad" may control either one or multiple lanes,
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and thus contains any logic common to all its lanes. Each lane can be
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separately configured and powered up.
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Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
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super-speed USB. Other lanes are for various types of low-speed, full-speed
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or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
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contains a software-configurable mux that sits between the I/O controller
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ports (e.g. PCIe) and the lanes.
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In addition to per-lane configuration, USB 3.0 ports may require additional
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settings on a per-board basis.
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Pads will be represented as children of the top-level XUSB pad controller
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device tree node. Each lane exposed by the pad will be represented by its
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own subnode and can be referenced by users of the lane using the standard
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PHY bindings, as described by the phy-bindings.txt file in this directory.
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The Tegra hardware documentation refers to the connection between the XUSB
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pad controller and the XUSB controller as "ports". This is confusing since
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"port" is typically used to denote the physical USB receptacle. The device
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tree binding in this document uses the term "port" to refer to the logical
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abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
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for the USB signal, the VBUS power supply, the USB 2.0 companion port for
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USB 3.0 receptacles, ...).
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Required properties:
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--------------------
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- compatible: Must be:
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- Tegra124: "nvidia,tegra124-xusb-padctl"
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- Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
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- Tegra210: "nvidia,tegra210-xusb-padctl"
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- reg: Physical base address and length of the controller's registers.
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- resets: Must contain an entry for each entry in reset-names.
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- reset-names: Must include the following entries:
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- "padctl"
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Pad nodes:
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==========
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A required child node named "pads" contains a list of subnodes, one for each
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of the pads exposed by the XUSB pad controller. Each pad may need additional
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resources that can be referenced in its pad node.
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The "status" property is used to enable or disable the use of a pad. If set
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to "disabled", the pad will not be used on the given board. In order to use
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the pad and any of its lanes, this property must be set to "okay".
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For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
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and sata. No extra resources are required for operation of these pads.
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For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
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a description of the properties of each pad.
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UTMI pad:
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---------
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Required properties:
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names: Must contain the following entries:
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- "trk": phandle and specifier referring to the USB2 tracking clock
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HSIC pad:
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---------
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Required properties:
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names: Must contain the following entries:
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- "trk": phandle and specifier referring to the HSIC tracking clock
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PCIe pad:
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---------
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Required properties:
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names: Must contain the following entries:
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- "pll": phandle and specifier referring to the PLLE
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- resets: Must contain an entry for each entry in reset-names.
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- reset-names: Must contain the following entries:
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- "phy": reset for the PCIe UPHY block
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SATA pad:
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---------
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Required properties:
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- resets: Must contain an entry for each entry in reset-names.
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- reset-names: Must contain the following entries:
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- "phy": reset for the SATA UPHY block
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PHY nodes:
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==========
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Each pad node has a child named "lanes" that contains one or more children of
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its own, each representing one of the lanes controlled by the pad.
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Required properties:
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--------------------
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- status: Defines the operation status of the PHY. Valid values are:
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- "disabled": the PHY is disabled
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- "okay": the PHY is enabled
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- #phy-cells: Should be 0. Since each lane represents a single PHY, there is
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no need for an additional specifier.
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- nvidia,function: The output function of the PHY. See below for a list of
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valid functions per SoC generation.
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For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
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- usb2: usb2-0, usb2-1, usb2-2
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- functions: "snps", "xusb", "uart"
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- ulpi: ulpi-0
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- functions: "snps", "xusb"
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- hsic: hsic-0, hsic-1
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- functions: "snps", "xusb"
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- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
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- functions: "pcie", "usb3-ss"
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- sata: sata-0
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- functions: "usb3-ss", "sata"
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For Tegra210, the list of valid PHY nodes is given below:
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- usb2: usb2-0, usb2-1, usb2-2, usb2-3
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- functions: "snps", "xusb", "uart"
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- hsic: hsic-0, hsic-1
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- functions: "snps", "xusb"
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- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
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- functions: "pcie-x1", "usb3-ss", "pcie-x4"
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- sata: sata-0
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- functions: "usb3-ss", "sata"
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Port nodes:
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===========
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A required child node named "ports" contains a list of all the ports exposed
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by the XUSB pad controller. Per-port configuration is only required for USB.
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USB2 ports:
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-----------
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Required properties:
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- status: Defines the operation status of the port. Valid values are:
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- "disabled": the port is disabled
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- "okay": the port is enabled
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- mode: A string that determines the mode in which to run the port. Valid
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values are:
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- "host": for USB host mode
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- "device": for USB device mode
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- "otg": for USB OTG mode
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Optional properties:
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- nvidia,internal: A boolean property whose presence determines that a port
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is internal. In the absence of this property the port is considered to be
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external.
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- vbus-supply: phandle to a regulator supplying the VBUS voltage.
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ULPI ports:
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-----------
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Optional properties:
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- status: Defines the operation status of the port. Valid values are:
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- "disabled": the port is disabled
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- "okay": the port is enabled
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- nvidia,internal: A boolean property whose presence determines that a port
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is internal. In the absence of this property the port is considered to be
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external.
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- vbus-supply: phandle to a regulator supplying the VBUS voltage.
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HSIC ports:
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-----------
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Required properties:
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- status: Defines the operation status of the port. Valid values are:
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- "disabled": the port is disabled
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- "okay": the port is enabled
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Optional properties:
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- vbus-supply: phandle to a regulator supplying the VBUS voltage.
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Super-speed USB ports:
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----------------------
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Required properties:
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- status: Defines the operation status of the port. Valid values are:
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- "disabled": the port is disabled
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- "okay": the port is enabled
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- nvidia,usb2-companion: A single cell that specifies the physical port number
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to map this super-speed USB port to. The range of valid port numbers varies
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with the SoC generation:
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- 0-2: for Tegra124 and Tegra132
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- 0-3: for Tegra210
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Optional properties:
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- nvidia,internal: A boolean property whose presence determines that a port
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is internal. In the absence of this property the port is considered to be
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external.
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For Tegra124 and Tegra132, the XUSB pad controller exposes the following
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ports:
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- 3x USB2: usb2-0, usb2-1, usb2-2
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- 1x ULPI: ulpi-0
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- 2x HSIC: hsic-0, hsic-1
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- 2x super-speed USB: usb3-0, usb3-1
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For Tegra210, the XUSB pad controller exposes the following ports:
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- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
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- 2x HSIC: hsic-0, hsic-1
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- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
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Examples:
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=========
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Tegra124 and Tegra132:
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----------------------
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SoC include:
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padctl@7009f000 {
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/* for Tegra124 */
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compatible = "nvidia,tegra124-xusb-padctl";
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/* for Tegra132 */
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compatible = "nvidia,tegra132-xusb-padctl",
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"nvidia,tegra124-xusb-padctl";
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reg = <0x0 0x7009f000 0x0 0x1000>;
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resets = <&tegra_car 142>;
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reset-names = "padctl";
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pads {
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usb2 {
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status = "disabled";
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lanes {
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usb2-0 {
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status = "disabled";
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#phy-cells = <0>;
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};
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usb2-1 {
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status = "disabled";
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#phy-cells = <0>;
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};
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usb2-2 {
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status = "disabled";
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#phy-cells = <0>;
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};
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};
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};
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ulpi {
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status = "disabled";
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lanes {
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ulpi-0 {
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status = "disabled";
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#phy-cells = <0>;
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};
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};
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};
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hsic {
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status = "disabled";
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lanes {
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hsic-0 {
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status = "disabled";
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#phy-cells = <0>;
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};
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hsic-1 {
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status = "disabled";
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#phy-cells = <0>;
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};
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};
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};
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pcie {
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status = "disabled";
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lanes {
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pcie-0 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-1 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-2 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-3 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-4 {
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status = "disabled";
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#phy-cells = <0>;
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};
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};
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};
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sata {
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status = "disabled";
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lanes {
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sata-0 {
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status = "disabled";
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#phy-cells = <0>;
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};
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};
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};
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};
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ports {
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usb2-0 {
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status = "disabled";
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};
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usb2-1 {
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status = "disabled";
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};
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usb2-2 {
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status = "disabled";
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};
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ulpi-0 {
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status = "disabled";
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};
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hsic-0 {
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status = "disabled";
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};
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hsic-1 {
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status = "disabled";
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};
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usb3-0 {
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status = "disabled";
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};
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usb3-1 {
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status = "disabled";
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};
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};
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};
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Board file:
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padctl@7009f000 {
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status = "okay";
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pads {
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usb2 {
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status = "okay";
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lanes {
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usb2-0 {
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nvidia,function = "xusb";
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status = "okay";
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};
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usb2-1 {
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nvidia,function = "xusb";
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status = "okay";
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};
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usb2-2 {
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nvidia,function = "xusb";
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status = "okay";
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};
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};
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};
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pcie {
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status = "okay";
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lanes {
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pcie-0 {
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nvidia,function = "usb3-ss";
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status = "okay";
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};
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pcie-2 {
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nvidia,function = "pcie";
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status = "okay";
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};
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pcie-4 {
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nvidia,function = "pcie";
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status = "okay";
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};
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};
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};
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sata {
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status = "okay";
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lanes {
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sata-0 {
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nvidia,function = "sata";
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status = "okay";
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};
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};
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};
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};
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ports {
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/* Micro A/B */
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usb2-0 {
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status = "okay";
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mode = "otg";
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};
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/* Mini PCIe */
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usb2-1 {
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status = "okay";
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mode = "host";
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};
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/* USB3 */
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usb2-2 {
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status = "okay";
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mode = "host";
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vbus-supply = <&vdd_usb3_vbus>;
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};
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usb3-0 {
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nvidia,port = <2>;
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status = "okay";
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};
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};
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};
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Tegra210:
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---------
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SoC include:
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padctl@7009f000 {
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compatible = "nvidia,tegra210-xusb-padctl";
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reg = <0x0 0x7009f000 0x0 0x1000>;
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resets = <&tegra_car 142>;
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reset-names = "padctl";
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status = "disabled";
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pads {
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usb2 {
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clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
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clock-names = "trk";
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status = "disabled";
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lanes {
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usb2-0 {
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status = "disabled";
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#phy-cells = <0>;
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};
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usb2-1 {
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status = "disabled";
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#phy-cells = <0>;
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};
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usb2-2 {
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status = "disabled";
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#phy-cells = <0>;
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};
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usb2-3 {
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status = "disabled";
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#phy-cells = <0>;
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};
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};
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};
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hsic {
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clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
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clock-names = "trk";
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status = "disabled";
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lanes {
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hsic-0 {
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status = "disabled";
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#phy-cells = <0>;
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};
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hsic-1 {
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status = "disabled";
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#phy-cells = <0>;
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};
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};
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};
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pcie {
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clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
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clock-names = "pll";
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resets = <&tegra_car 205>;
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reset-names = "phy";
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status = "disabled";
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lanes {
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pcie-0 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-1 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-2 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-3 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-4 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-5 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-6 {
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status = "disabled";
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#phy-cells = <0>;
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};
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};
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};
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sata {
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clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
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clock-names = "pll";
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resets = <&tegra_car 204>;
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reset-names = "phy";
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status = "disabled";
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lanes {
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sata-0 {
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status = "disabled";
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#phy-cells = <0>;
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};
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};
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};
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};
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ports {
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usb2-0 {
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status = "disabled";
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};
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usb2-1 {
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status = "disabled";
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};
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usb2-2 {
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status = "disabled";
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};
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usb2-3 {
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status = "disabled";
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};
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hsic-0 {
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status = "disabled";
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};
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hsic-1 {
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status = "disabled";
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};
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usb3-0 {
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status = "disabled";
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};
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usb3-1 {
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status = "disabled";
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};
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usb3-2 {
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status = "disabled";
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};
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usb3-3 {
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status = "disabled";
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|
};
|
|
};
|
|
};
|
|
|
|
Board file:
|
|
|
|
padctl@7009f000 {
|
|
status = "okay";
|
|
|
|
pads {
|
|
usb2 {
|
|
status = "okay";
|
|
|
|
lanes {
|
|
usb2-0 {
|
|
nvidia,function = "xusb";
|
|
status = "okay";
|
|
};
|
|
|
|
usb2-1 {
|
|
nvidia,function = "xusb";
|
|
status = "okay";
|
|
};
|
|
|
|
usb2-2 {
|
|
nvidia,function = "xusb";
|
|
status = "okay";
|
|
};
|
|
|
|
usb2-3 {
|
|
nvidia,function = "xusb";
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
pcie {
|
|
status = "okay";
|
|
|
|
lanes {
|
|
pcie-0 {
|
|
nvidia,function = "pcie-x1";
|
|
status = "okay";
|
|
};
|
|
|
|
pcie-1 {
|
|
nvidia,function = "pcie-x4";
|
|
status = "okay";
|
|
};
|
|
|
|
pcie-2 {
|
|
nvidia,function = "pcie-x4";
|
|
status = "okay";
|
|
};
|
|
|
|
pcie-3 {
|
|
nvidia,function = "pcie-x4";
|
|
status = "okay";
|
|
};
|
|
|
|
pcie-4 {
|
|
nvidia,function = "pcie-x4";
|
|
status = "okay";
|
|
};
|
|
|
|
pcie-5 {
|
|
nvidia,function = "usb3-ss";
|
|
status = "okay";
|
|
};
|
|
|
|
pcie-6 {
|
|
nvidia,function = "usb3-ss";
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
sata {
|
|
status = "okay";
|
|
|
|
lanes {
|
|
sata-0 {
|
|
nvidia,function = "sata";
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ports {
|
|
usb2-0 {
|
|
status = "okay";
|
|
mode = "otg";
|
|
};
|
|
|
|
usb2-1 {
|
|
status = "okay";
|
|
vbus-supply = <&vdd_5v0_rtl>;
|
|
mode = "host";
|
|
};
|
|
|
|
usb2-2 {
|
|
status = "okay";
|
|
vbus-supply = <&vdd_usb_vbus>;
|
|
mode = "host";
|
|
};
|
|
|
|
usb2-3 {
|
|
status = "okay";
|
|
mode = "host";
|
|
};
|
|
|
|
usb3-0 {
|
|
status = "okay";
|
|
nvidia,lanes = "pcie-6";
|
|
nvidia,port = <1>;
|
|
};
|
|
|
|
usb3-1 {
|
|
status = "okay";
|
|
nvidia,lanes = "pcie-5";
|
|
nvidia,port = <2>;
|
|
};
|
|
};
|
|
};
|