56 lines
2.0 KiB
Plaintext
56 lines
2.0 KiB
Plaintext
XILINX AXI ETHERNET Device Tree Bindings
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--------------------------------------------------------
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Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
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provides connectivity to an external ethernet PHY supporting different
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interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
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segments of memory for buffering TX and RX, as well as the capability of
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offloading TX/RX checksum calculation off the processor.
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Management configuration is done through the AXI interface, while payload is
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sent and received through means of an AXI DMA controller. This driver
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includes the DMA driver code, so this driver is incompatible with AXI DMA
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driver.
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For more details about mdio please refer phy.txt file in the same directory.
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Required properties:
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- compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
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"xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
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- reg : Address and length of the IO space.
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- interrupts : Should be a list of two interrupt, TX and RX.
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- phy-handle : Should point to the external phy device.
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See ethernet.txt file in the same directory.
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- xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware
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Optional properties:
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- phy-mode : See ethernet.txt
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- xlnx,phy-type : Deprecated, do not use, but still accepted in preference
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to phy-mode.
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- xlnx,txcsum : 0 or empty for disabling TX checksum offload,
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1 to enable partial TX checksum offload,
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2 to enable full TX checksum offload
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- xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload
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Example:
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axi_ethernet_eth: ethernet@40c00000 {
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compatible = "xlnx,axi-ethernet-1.00.a";
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device_type = "network";
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interrupt-parent = <µblaze_0_axi_intc>;
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interrupts = <2 0>;
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phy-mode = "mii";
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reg = <0x40c00000 0x40000>;
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xlnx,rxcsum = <0x2>;
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xlnx,rxmem = <0x800>;
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xlnx,txcsum = <0x2>;
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phy-handle = <&phy0>;
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axi_ethernetlite_0_mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: phy@0 {
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device_type = "ethernet-phy";
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reg = <1>;
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};
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};
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};
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