47 lines
1.8 KiB
Plaintext
47 lines
1.8 KiB
Plaintext
* Texas Instruments - dp83867 Giga bit ethernet phy
|
|
|
|
Required properties:
|
|
- reg - The ID number for the phy, usually a small integer
|
|
- ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
|
|
for applicable values. Required only if interface type is
|
|
PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID
|
|
- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
|
|
for applicable values. Required only if interface type is
|
|
PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID
|
|
- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
|
|
for applicable values
|
|
|
|
Optional property:
|
|
- ti,min-output-impedance - MAC Interface Impedance control to set
|
|
the programmable output impedance to
|
|
minimum value (35 ohms).
|
|
- ti,max-output-impedance - MAC Interface Impedance control to set
|
|
the programmable output impedance to
|
|
maximum value (70 ohms).
|
|
- ti,dp83867-rxctrl-strap-quirk - This denotes the fact that the
|
|
board has RX_DV/RX_CTRL pin strapped in
|
|
mode 1 or 2. To ensure PHY operation,
|
|
there are specific actions that
|
|
software needs to take when this pin is
|
|
strapped in these modes. See data manual
|
|
for details.
|
|
|
|
Note: ti,min-output-impedance and ti,max-output-impedance are mutually
|
|
exclusive. When both properties are present ti,max-output-impedance
|
|
takes precedence.
|
|
|
|
Default child nodes are standard Ethernet PHY device
|
|
nodes as described in Documentation/devicetree/bindings/net/phy.txt
|
|
|
|
Example:
|
|
|
|
ethernet-phy@0 {
|
|
reg = <0>;
|
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
|
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
|
|
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
|
};
|
|
|
|
Datasheet can be found:
|
|
http://www.ti.com/product/DP83867IR/datasheet
|