116 lines
3.9 KiB
Plaintext
116 lines
3.9 KiB
Plaintext
Xilinx AXI VDMA engine, it does transfers between memory and video devices.
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It can be configured to have one channel or two channels. If configured
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as two channels, one is to transmit to the video device and another is
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to receive from the video device.
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Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
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target devices. It can be configured to have one channel or two channels.
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If configured as two channels, one is to transmit to the device and another
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is to receive from the device.
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Xilinx AXI CDMA engine, it does transfers between memory-mapped source
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address and a memory-mapped destination address.
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Required properties:
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- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or
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"xlnx,axi-cdma-1.00.a""
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- #dma-cells: Should be <1>, see "dmas" property below
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- reg: Should contain VDMA registers location and length.
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- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
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- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
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- dma-channel child node: Should have at least one channel and can have up to
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two channels per device. This node specifies the properties of each
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DMA channel (see child node properties below).
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- clocks: Input clock specifier. Refer to common clock bindings.
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- clock-names: List of input clocks
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For VDMA:
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Required elements: "s_axi_lite_aclk"
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Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",
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"m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
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For CDMA:
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Required elements: "s_axi_lite_aclk", "m_axi_aclk"
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FOR AXIDMA:
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Required elements: "s_axi_lite_aclk"
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Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
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"m_axi_sg_aclk"
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Required properties for VDMA:
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- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
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Optional properties:
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- xlnx,include-sg: Tells configured for Scatter-mode in
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the hardware.
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Optional properties for AXI DMA:
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- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
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Optional properties for VDMA:
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- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
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It takes following values:
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{1}, flush both channels
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{2}, flush mm2s channel
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{3}, flush s2mm channel
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Required child node properties:
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- compatible:
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For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or
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"xlnx,axi-vdma-s2mm-channel".
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For CDMA: It should be "xlnx,axi-cdma-channel".
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For AXIDMA: It should be either "xlnx,axi-dma-mm2s-channel" or
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"xlnx,axi-dma-s2mm-channel".
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- interrupts: Should contain per channel VDMA interrupts.
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- xlnx,datawidth: Should contain the stream data width, take values
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{32,64...1024}.
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Optional child node properties:
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- xlnx,include-dre: Tells hardware is configured for Data
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Realignment Engine.
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Optional child node properties for VDMA:
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- xlnx,genlock-mode: Tells Genlock synchronization is
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enabled/disabled in hardware.
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Optional child node properties for AXI DMA:
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-dma-channels: Number of dma channels in child node.
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Example:
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++++++++
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axi_vdma_0: axivdma@40030000 {
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compatible = "xlnx,axi-vdma-1.00.a";
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#dma_cells = <1>;
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reg = < 0x40030000 0x10000 >;
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dma-ranges = <0x00000000 0x00000000 0x40000000>;
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xlnx,num-fstores = <0x8>;
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xlnx,flush-fsync = <0x1>;
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xlnx,addrwidth = <0x20>;
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clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
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clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
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"m_axis_mm2s_aclk", "s_axis_s2mm_aclk";
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dma-channel@40030000 {
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compatible = "xlnx,axi-vdma-mm2s-channel";
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interrupts = < 0 54 4 >;
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xlnx,datawidth = <0x40>;
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} ;
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dma-channel@40030030 {
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compatible = "xlnx,axi-vdma-s2mm-channel";
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interrupts = < 0 53 4 >;
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xlnx,datawidth = <0x40>;
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} ;
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} ;
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* DMA client
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Required properties:
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- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
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where Channel ID is '0' for write/tx and '1' for read/rx
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channel.
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- dma-names: a list of DMA channel names, one per "dmas" entry
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Example:
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++++++++
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vdmatest_0: vdmatest@0 {
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compatible ="xlnx,axi-vdma-test-1.00.a";
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dmas = <&axi_vdma_0 0
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&axi_vdma_0 1>;
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dma-names = "vdma0", "vdma1";
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} ;
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