209 lines
8.0 KiB
Plaintext
209 lines
8.0 KiB
Plaintext
* Rockchip rk3399 DMC(Dynamic Memory Controller) device
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Required properties:
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- compatible: Must be "rockchip,rk3399-dmc".
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- devfreq-events: Node to get DDR loading, Refer to
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Documentation/devicetree/bindings/devfreq/
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rockchip-dfi.txt
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- interrupts: The interrupt number to the CPU. The interrupt
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specifier format depends on the interrupt controller.
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It should be DCF interrupts, when DDR dvfs finish,
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it will happen.
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- clocks: Phandles for clock specified in "clock-names" property
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- clock-names : The name of clock used by the DFI, must be
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"pclk_ddr_mon";
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- operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt
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for details.
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- center-supply: DMC supply node.
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- status: Marks the node enabled/disabled.
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Following properties are ddr timing:
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- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/ddr.h,
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it select ddr3 cl-trp-trcd type, default value
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"DDR3_DEFAULT".it must selected according to
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"Speed Bin" in ddr3 datasheet, DO NOT use
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smaller "Speed Bin" than ddr3 exactly is.
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- rockchip,pd_idle : Config the PD_IDLE value, defined the power-down
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idle period, memories are places into power-down
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mode if bus is idle for PD_IDLE DFI clocks.
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- rockchip,sr_idle : Configure the SR_IDLE value, defined the
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selfrefresh idle period, memories are places
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into self-refresh mode if bus is idle for
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SR_IDLE*1024 DFI clocks (DFI clocks freq is
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half of dram's clocks), defaule value is "0".
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- rockchip,sr_mc_gate_idle : Defined the self-refresh with memory and
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controller clock gating idle period, memories
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are places into self-refresh mode and memory
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controller clock arg gating if bus is idle for
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sr_mc_gate_idle*1024 DFI clocks.
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- rockchip,srpd_lite_idle : Defined the self-refresh power down idle
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period, memories are places into self-refresh
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power down mode if bus is idle for
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srpd_lite_idle*1024 DFI clocks. This parameter
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is for LPDDR4 only.
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- rockchip,standby_idle : Defined the standby idle period, memories are
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places into self-refresh than controller, pi,
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phy and dram clock will gating if bus is idle
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for standby_idle * DFI clocks.
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- rockchip,dram_dll_disb_freq : It's defined the DDR3 dll bypass frequency in
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MHz, when ddr freq less than DRAM_DLL_DISB_FREQ,
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ddr3 dll will bypssed note: if dll was bypassed,
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the odt also stop working.
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- rockchip,phy_dll_disb_freq : Defined the PHY dll bypass frequency in
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MHz (Mega Hz), when ddr freq less than
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DRAM_DLL_DISB_FREQ, phy dll will bypssed.
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note: phy dll and phy odt are independent.
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- rockchip,ddr3_odt_disb_freq : When dram type is DDR3, this parameter defined
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the odt disable frequency in MHz (Mega Hz),
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when ddr frequency less then ddr3_odt_disb_freq,
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the odt on dram side and controller side are
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both disabled.
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- rockchip,ddr3_drv : When dram type is DDR3, this parameter define
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the dram side driver stength in ohm, default
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value is DDR3_DS_40ohm.
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- rockchip,ddr3_odt : When dram type is DDR3, this parameter define
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the dram side ODT stength in ohm, default value
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is DDR3_ODT_120ohm.
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- rockchip,phy_ddr3_ca_drv : When dram type is DDR3, this parameter define
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the phy side CA line(incluing command line,
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address line and clock line) driver strength.
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Default value is PHY_DRV_ODT_40.
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- rockchip,phy_ddr3_dq_drv : When dram type is DDR3, this parameter define
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the phy side DQ line(incluing DQS/DQ/DM line)
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driver strength. default value is PHY_DRV_ODT_40.
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- rockchip,phy_ddr3_odt : When dram type is DDR3, this parameter define the
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phy side odt strength, default value is
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PHY_DRV_ODT_240.
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- rockchip,lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined
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then odt disable frequency in MHz (Mega Hz),
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when ddr frequency less then ddr3_odt_disb_freq,
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the odt on dram side and controller side are
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both disabled.
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- rockchip,lpddr3_drv : When dram type is LPDDR3, this parameter define
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the dram side driver stength in ohm, default
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value is LP3_DS_34ohm.
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- rockchip,lpddr3_odt : When dram type is LPDDR3, this parameter define
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the dram side ODT stength in ohm, default value
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is LP3_ODT_240ohm.
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- rockchip,phy_lpddr3_ca_drv : When dram type is LPDDR3, this parameter define
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the phy side CA line(incluing command line,
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address line and clock line) driver strength.
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default value is PHY_DRV_ODT_40.
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- rockchip,phy_lpddr3_dq_drv : When dram type is LPDDR3, this parameter define
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the phy side DQ line(incluing DQS/DQ/DM line)
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driver strength. default value is
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PHY_DRV_ODT_40.
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- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
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the phy side odt strength, default value is
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PHY_DRV_ODT_240.
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- rockchip,lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter
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defined the odt disable frequency in
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MHz (Mega Hz), when ddr frequency less then
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ddr3_odt_disb_freq, the odt on dram side and
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controller side are both disabled.
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- rockchip,lpddr4_drv : When dram type is LPDDR4, this parameter define
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the dram side driver stength in ohm, default
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value is LP4_PDDS_60ohm.
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- rockchip,lpddr4_dq_odt : When dram type is LPDDR4, this parameter define
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the dram side ODT on dqs/dq line stength in ohm,
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default value is LP4_DQ_ODT_40ohm.
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- rockchip,lpddr4_ca_odt : When dram type is LPDDR4, this parameter define
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the dram side ODT on ca line stength in ohm,
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default value is LP4_CA_ODT_40ohm.
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- rockchip,phy_lpddr4_ca_drv : When dram type is LPDDR4, this parameter define
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the phy side CA line(incluing command address
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line) driver strength. default value is
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PHY_DRV_ODT_40.
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- rockchip,phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define
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the phy side clock line and cs line driver
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strength. default value is PHY_DRV_ODT_80.
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- rockchip,phy_lpddr4_dq_drv : When dram type is LPDDR4, this parameter define
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the phy side DQ line(incluing DQS/DQ/DM line)
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driver strength. default value is PHY_DRV_ODT_80.
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- rockchip,phy_lpddr4_odt : When dram type is LPDDR4, this parameter define
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the phy side odt strength, default value is
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PHY_DRV_ODT_60.
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Example:
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dmc_opp_table: dmc_opp_table {
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compatible = "operating-points-v2";
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opp00 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <900000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <666000000>;
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opp-microvolt = <900000>;
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};
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};
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dmc: dmc {
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compatible = "rockchip,rk3399-dmc";
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devfreq-events = <&dfi>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_DDRCLK>;
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clock-names = "dmc_clk";
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operating-points-v2 = <&dmc_opp_table>;
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center-supply = <&ppvar_centerlogic>;
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upthreshold = <15>;
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downdifferential = <10>;
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rockchip,ddr3_speed_bin = <21>;
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rockchip,pd_idle = <0x40>;
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rockchip,sr_idle = <0x2>;
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rockchip,sr_mc_gate_idle = <0x3>;
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rockchip,srpd_lite_idle = <0x4>;
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rockchip,standby_idle = <0x2000>;
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rockchip,dram_dll_dis_freq = <300>;
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rockchip,phy_dll_dis_freq = <125>;
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rockchip,auto_pd_dis_freq = <666>;
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rockchip,ddr3_odt_dis_freq = <333>;
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rockchip,ddr3_drv = <DDR3_DS_40ohm>;
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rockchip,ddr3_odt = <DDR3_ODT_120ohm>;
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rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;
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rockchip,lpddr3_odt_dis_freq = <333>;
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rockchip,lpddr3_drv = <LP3_DS_34ohm>;
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rockchip,lpddr3_odt = <LP3_ODT_240ohm>;
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rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;
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rockchip,lpddr4_odt_dis_freq = <333>;
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rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;
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rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
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rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
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rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
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rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
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rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
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};
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