552 lines
15 KiB
C
552 lines
15 KiB
C
/*
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* This driver supports the digital controls for the internal codec
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* found in Allwinner's A33 SoCs.
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*
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* (C) Copyright 2010-2016
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* Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
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* huangxin <huangxin@Reuuimllatech.com>
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* Mylène Josserand <mylene.josserand@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dapm.h>
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#define SUN8I_SYSCLK_CTL 0x00c
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#define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11
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#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL 9
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#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC 8
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#define SUN8I_SYSCLK_CTL_SYSCLK_ENA 3
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#define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0
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#define SUN8I_MOD_CLK_ENA 0x010
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#define SUN8I_MOD_CLK_ENA_AIF1 15
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#define SUN8I_MOD_CLK_ENA_DAC 2
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#define SUN8I_MOD_RST_CTL 0x014
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#define SUN8I_MOD_RST_CTL_AIF1 15
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#define SUN8I_MOD_RST_CTL_DAC 2
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#define SUN8I_SYS_SR_CTRL 0x018
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#define SUN8I_SYS_SR_CTRL_AIF1_FS 12
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#define SUN8I_SYS_SR_CTRL_AIF2_FS 8
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#define SUN8I_AIF1CLK_CTRL 0x040
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#define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15
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#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV 14
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#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV 13
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#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9
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#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6
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#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16 (1 << 6)
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#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4
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#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4)
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#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2
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#define SUN8I_AIF1_DACDAT_CTRL 0x048
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#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15
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#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14
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#define SUN8I_DAC_DIG_CTRL 0x120
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#define SUN8I_DAC_DIG_CTRL_ENDA 15
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#define SUN8I_DAC_MXR_SRC 0x130
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#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15
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#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14
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#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13
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#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL 12
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#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11
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#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10
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#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9
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#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8
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#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12)
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#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8)
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#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4)
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#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6)
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#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9)
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struct sun8i_codec {
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struct device *dev;
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struct regmap *regmap;
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struct clk *clk_module;
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struct clk *clk_bus;
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};
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static int sun8i_codec_runtime_resume(struct device *dev)
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{
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struct sun8i_codec *scodec = dev_get_drvdata(dev);
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int ret;
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ret = clk_prepare_enable(scodec->clk_module);
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if (ret) {
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dev_err(dev, "Failed to enable the module clock\n");
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return ret;
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}
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ret = clk_prepare_enable(scodec->clk_bus);
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if (ret) {
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dev_err(dev, "Failed to enable the bus clock\n");
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goto err_disable_modclk;
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}
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regcache_cache_only(scodec->regmap, false);
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ret = regcache_sync(scodec->regmap);
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if (ret) {
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dev_err(dev, "Failed to sync regmap cache\n");
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goto err_disable_clk;
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}
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return 0;
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err_disable_clk:
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clk_disable_unprepare(scodec->clk_bus);
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err_disable_modclk:
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clk_disable_unprepare(scodec->clk_module);
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return ret;
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}
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static int sun8i_codec_runtime_suspend(struct device *dev)
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{
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struct sun8i_codec *scodec = dev_get_drvdata(dev);
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regcache_cache_only(scodec->regmap, true);
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regcache_mark_dirty(scodec->regmap);
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clk_disable_unprepare(scodec->clk_module);
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clk_disable_unprepare(scodec->clk_bus);
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return 0;
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}
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static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
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{
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unsigned int rate = params_rate(params);
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switch (rate) {
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case 8000:
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case 7350:
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return 0x0;
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case 11025:
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return 0x1;
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case 12000:
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return 0x2;
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case 16000:
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return 0x3;
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case 22050:
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return 0x4;
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case 24000:
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return 0x5;
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case 32000:
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return 0x6;
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case 44100:
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return 0x7;
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case 48000:
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return 0x8;
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case 96000:
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return 0x9;
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case 192000:
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return 0xa;
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default:
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return -EINVAL;
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}
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}
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static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
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u32 value;
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/* clock masters */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS: /* Codec slave, DAI master */
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value = 0x1;
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break;
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case SND_SOC_DAIFMT_CBM_CFM: /* Codec Master, DAI slave */
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value = 0x0;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
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BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD),
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value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD);
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/* clock inversion */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF: /* Normal */
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value = 0x0;
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break;
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case SND_SOC_DAIFMT_IB_IF: /* Inversion */
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value = 0x1;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
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BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV),
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value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV);
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/*
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* It appears that the DAI and the codec don't share the same
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* polarity for the LRCK signal when they mean 'normal' and
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* 'inverted' in the datasheet.
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*
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* Since the DAI here is our regular i2s driver that have been
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* tested with way more codecs than just this one, it means
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* that the codec probably gets it backward, and we have to
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* invert the value here.
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*/
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regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
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BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV),
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!value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);
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/* DAI format */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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value = 0x0;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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value = 0x1;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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value = 0x2;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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case SND_SOC_DAIFMT_DSP_B:
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value = 0x3;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
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BIT(SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT),
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value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT);
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return 0;
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}
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struct sun8i_codec_clk_div {
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u8 div;
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u8 val;
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};
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static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = {
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{ .div = 1, .val = 0 },
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{ .div = 2, .val = 1 },
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{ .div = 4, .val = 2 },
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{ .div = 6, .val = 3 },
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{ .div = 8, .val = 4 },
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{ .div = 12, .val = 5 },
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{ .div = 16, .val = 6 },
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{ .div = 24, .val = 7 },
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{ .div = 32, .val = 8 },
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{ .div = 48, .val = 9 },
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{ .div = 64, .val = 10 },
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{ .div = 96, .val = 11 },
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{ .div = 128, .val = 12 },
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{ .div = 192, .val = 13 },
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};
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static u8 sun8i_codec_get_bclk_div(struct sun8i_codec *scodec,
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unsigned int rate,
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unsigned int word_size)
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{
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unsigned long clk_rate = clk_get_rate(scodec->clk_module);
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unsigned int div = clk_rate / rate / word_size / 2;
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unsigned int best_val = 0, best_diff = ~0;
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int i;
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for (i = 0; i < ARRAY_SIZE(sun8i_codec_bclk_div); i++) {
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const struct sun8i_codec_clk_div *bdiv = &sun8i_codec_bclk_div[i];
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unsigned int diff = abs(bdiv->div - div);
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if (diff < best_diff) {
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best_diff = diff;
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best_val = bdiv->val;
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}
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}
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return best_val;
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}
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static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
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int sample_rate;
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u8 bclk_div;
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/*
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* The CPU DAI handles only a sample of 16 bits. Configure the
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* codec to handle this type of sample resolution.
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*/
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regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
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SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK,
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SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16);
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bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), 16);
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regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
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SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK,
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bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);
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regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
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SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK,
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SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16);
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sample_rate = sun8i_codec_get_hw_rate(params);
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if (sample_rate < 0)
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return sample_rate;
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regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
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SUN8I_SYS_SR_CTRL_AIF1_FS_MASK,
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sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);
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regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
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SUN8I_SYS_SR_CTRL_AIF2_FS_MASK,
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sample_rate << SUN8I_SYS_SR_CTRL_AIF2_FS);
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return 0;
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}
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static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
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SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch",
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SUN8I_DAC_MXR_SRC,
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SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L,
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SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0),
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SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch",
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SUN8I_DAC_MXR_SRC,
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SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L,
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SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0),
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SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
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SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL,
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SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0),
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SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
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SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL,
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SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0),
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};
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static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
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/* Digital parts of the DACs */
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SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA,
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0, NULL, 0),
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/* Analog DAC AIF */
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SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0,
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SUN8I_AIF1_DACDAT_CTRL,
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SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0),
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SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right", "Playback", 0,
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SUN8I_AIF1_DACDAT_CTRL,
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SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
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/* DAC Mixers */
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SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
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sun8i_dac_mixer_controls),
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SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
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sun8i_dac_mixer_controls),
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/* Clocks */
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SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA,
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SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA,
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SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL,
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SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL,
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SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("AIF1 PLL", SUN8I_SYSCLK_CTL,
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SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL, 0, NULL, 0),
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/* Inversion as 0=AIF1, 1=AIF2 */
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SND_SOC_DAPM_SUPPLY("SYSCLK AIF1", SUN8I_SYSCLK_CTL,
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SUN8I_SYSCLK_CTL_SYSCLK_SRC, 1, NULL, 0),
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/* Module reset */
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SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL,
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SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL,
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SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0),
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};
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static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
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/* Clock Routes */
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{ "AIF1", NULL, "SYSCLK AIF1" },
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{ "AIF1 PLL", NULL, "AIF1" },
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{ "RST AIF1", NULL, "AIF1 PLL" },
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{ "MODCLK AFI1", NULL, "RST AIF1" },
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{ "DAC", NULL, "MODCLK AFI1" },
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{ "RST DAC", NULL, "SYSCLK" },
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{ "MODCLK DAC", NULL, "RST DAC" },
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{ "DAC", NULL, "MODCLK DAC" },
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/* DAC Routes */
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{ "AIF1 Slot 0 Right", NULL, "DAC" },
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{ "AIF1 Slot 0 Left", NULL, "DAC" },
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/* DAC Mixer Routes */
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{ "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
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"AIF1 Slot 0 Left"},
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{ "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
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"AIF1 Slot 0 Right"},
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};
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static const struct snd_soc_dai_ops sun8i_codec_dai_ops = {
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.hw_params = sun8i_codec_hw_params,
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.set_fmt = sun8i_set_fmt,
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};
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static struct snd_soc_dai_driver sun8i_codec_dai = {
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.name = "sun8i",
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/* playback capabilities */
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.playback = {
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.stream_name = "Playback",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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/* pcm operations */
|
|
.ops = &sun8i_codec_dai_ops,
|
|
};
|
|
|
|
static const struct snd_soc_codec_driver sun8i_soc_codec = {
|
|
.component_driver = {
|
|
.dapm_widgets = sun8i_codec_dapm_widgets,
|
|
.num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets),
|
|
.dapm_routes = sun8i_codec_dapm_routes,
|
|
.num_dapm_routes = ARRAY_SIZE(sun8i_codec_dapm_routes),
|
|
},
|
|
};
|
|
|
|
static const struct regmap_config sun8i_codec_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = SUN8I_DAC_MXR_SRC,
|
|
|
|
.cache_type = REGCACHE_FLAT,
|
|
};
|
|
|
|
static int sun8i_codec_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res_base;
|
|
struct sun8i_codec *scodec;
|
|
void __iomem *base;
|
|
int ret;
|
|
|
|
scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
|
|
if (!scodec)
|
|
return -ENOMEM;
|
|
|
|
scodec->dev = &pdev->dev;
|
|
|
|
scodec->clk_module = devm_clk_get(&pdev->dev, "mod");
|
|
if (IS_ERR(scodec->clk_module)) {
|
|
dev_err(&pdev->dev, "Failed to get the module clock\n");
|
|
return PTR_ERR(scodec->clk_module);
|
|
}
|
|
|
|
scodec->clk_bus = devm_clk_get(&pdev->dev, "bus");
|
|
if (IS_ERR(scodec->clk_bus)) {
|
|
dev_err(&pdev->dev, "Failed to get the bus clock\n");
|
|
return PTR_ERR(scodec->clk_bus);
|
|
}
|
|
|
|
res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
base = devm_ioremap_resource(&pdev->dev, res_base);
|
|
if (IS_ERR(base)) {
|
|
dev_err(&pdev->dev, "Failed to map the registers\n");
|
|
return PTR_ERR(base);
|
|
}
|
|
|
|
scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
|
|
&sun8i_codec_regmap_config);
|
|
if (IS_ERR(scodec->regmap)) {
|
|
dev_err(&pdev->dev, "Failed to create our regmap\n");
|
|
return PTR_ERR(scodec->regmap);
|
|
}
|
|
|
|
platform_set_drvdata(pdev, scodec);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
if (!pm_runtime_enabled(&pdev->dev)) {
|
|
ret = sun8i_codec_runtime_resume(&pdev->dev);
|
|
if (ret)
|
|
goto err_pm_disable;
|
|
}
|
|
|
|
ret = snd_soc_register_codec(&pdev->dev, &sun8i_soc_codec,
|
|
&sun8i_codec_dai, 1);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register codec\n");
|
|
goto err_suspend;
|
|
}
|
|
|
|
return ret;
|
|
|
|
err_suspend:
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
sun8i_codec_runtime_suspend(&pdev->dev);
|
|
|
|
err_pm_disable:
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sun8i_codec_remove(struct platform_device *pdev)
|
|
{
|
|
struct snd_soc_card *card = platform_get_drvdata(pdev);
|
|
struct sun8i_codec *scodec = snd_soc_card_get_drvdata(card);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
sun8i_codec_runtime_suspend(&pdev->dev);
|
|
|
|
snd_soc_unregister_codec(&pdev->dev);
|
|
clk_disable_unprepare(scodec->clk_module);
|
|
clk_disable_unprepare(scodec->clk_bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id sun8i_codec_of_match[] = {
|
|
{ .compatible = "allwinner,sun8i-a33-codec" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
|
|
|
|
static const struct dev_pm_ops sun8i_codec_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(sun8i_codec_runtime_suspend,
|
|
sun8i_codec_runtime_resume, NULL)
|
|
};
|
|
|
|
static struct platform_driver sun8i_codec_driver = {
|
|
.driver = {
|
|
.name = "sun8i-codec",
|
|
.of_match_table = sun8i_codec_of_match,
|
|
.pm = &sun8i_codec_pm_ops,
|
|
},
|
|
.probe = sun8i_codec_probe,
|
|
.remove = sun8i_codec_remove,
|
|
};
|
|
module_platform_driver(sun8i_codec_driver);
|
|
|
|
MODULE_DESCRIPTION("Allwinner A33 (sun8i) codec driver");
|
|
MODULE_AUTHOR("Mylène Josserand <mylene.josserand@free-electrons.com>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:sun8i-codec");
|