408 lines
10 KiB
C
408 lines
10 KiB
C
/*
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* linux/drivers/video/savagefb.h -- S3 Savage Framebuffer Driver
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*
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* Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*/
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#ifndef __SAVAGEFB_H__
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#define __SAVAGEFB_H__
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/mutex.h>
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#include <video/vga.h>
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#include "../edid.h"
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#ifdef SAVAGEFB_DEBUG
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# define DBG(x) printk (KERN_DEBUG "savagefb: %s\n", (x));
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#else
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# define DBG(x)
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# define SavagePrintRegs(...)
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#endif
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#define PCI_CHIP_SAVAGE4 0x8a22
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#define PCI_CHIP_SAVAGE3D 0x8a20
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#define PCI_CHIP_SAVAGE3D_MV 0x8a21
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#define PCI_CHIP_SAVAGE2000 0x9102
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#define PCI_CHIP_SAVAGE_MX_MV 0x8c10
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#define PCI_CHIP_SAVAGE_MX 0x8c11
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#define PCI_CHIP_SAVAGE_IX_MV 0x8c12
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#define PCI_CHIP_SAVAGE_IX 0x8c13
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#define PCI_CHIP_PROSAVAGE_PM 0x8a25
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#define PCI_CHIP_PROSAVAGE_KM 0x8a26
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#define PCI_CHIP_S3TWISTER_P 0x8d01
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#define PCI_CHIP_S3TWISTER_K 0x8d02
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#define PCI_CHIP_PROSAVAGE_DDR 0x8d03
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#define PCI_CHIP_PROSAVAGE_DDRK 0x8d04
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#define PCI_CHIP_SUPSAV_MX128 0x8c22
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#define PCI_CHIP_SUPSAV_MX64 0x8c24
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#define PCI_CHIP_SUPSAV_MX64C 0x8c26
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#define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a
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#define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b
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#define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c
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#define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d
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#define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e
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#define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f
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#define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
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#define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
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#define S3_SAVAGE4_SERIES(chip) ((chip>=S3_SAVAGE4) && (chip<=S3_PROSAVAGEDDR))
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#define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
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#define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) || (chip==S3_PROSAVAGEDDR))
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/* Chip tags. These are used to group the adapters into
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* related families.
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*/
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typedef enum {
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S3_UNKNOWN = 0,
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S3_SAVAGE3D,
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S3_SAVAGE_MX,
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S3_SAVAGE4,
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S3_PROSAVAGE,
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S3_TWISTER,
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S3_PROSAVAGEDDR,
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S3_SUPERSAVAGE,
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S3_SAVAGE2000,
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S3_LAST
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} savage_chipset;
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#define BIOS_BSIZE 1024
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#define BIOS_BASE 0xc0000
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#define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */
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#define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000
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#define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */
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#define SAVAGE_NEWMMIO_VGABASE 0x8000
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#define BASE_FREQ 14318
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#define HALF_BASE_FREQ 7159
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#define FIFO_CONTROL_REG 0x8200
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#define MIU_CONTROL_REG 0x8204
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#define STREAMS_TIMEOUT_REG 0x8208
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#define MISC_TIMEOUT_REG 0x820c
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#define MONO_PAT_0 0xa4e8
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#define MONO_PAT_1 0xa4ec
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#define MAXFIFO 0x7f00
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#define BCI_CMD_NOP 0x40000000
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#define BCI_CMD_SETREG 0x96000000
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#define BCI_CMD_RECT 0x48000000
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#define BCI_CMD_RECT_XP 0x01000000
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#define BCI_CMD_RECT_YP 0x02000000
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#define BCI_CMD_SEND_COLOR 0x00008000
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#define BCI_CMD_DEST_GBD 0x00000000
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#define BCI_CMD_SRC_GBD 0x00000020
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#define BCI_CMD_SRC_SOLID 0x00000000
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#define BCI_CMD_SRC_MONO 0x00000060
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#define BCI_CMD_CLIP_NEW 0x00006000
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#define BCI_CMD_CLIP_LR 0x00004000
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#define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF)
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#define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF)
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#define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF)
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#define BCI_W_H(w, h) (((h) << 16) | ((w) & 0xFFF))
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#define BCI_X_Y(x, y) (((y) << 16) | ((x) & 0xFFF))
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#define BCI_GBD1 0xE0
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#define BCI_GBD2 0xE1
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#define BCI_BUFFER_OFFSET 0x10000
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#define BCI_SIZE 0x4000
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#define BCI_SEND(dw) writel(dw, par->bci_base + par->bci_ptr++)
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#define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF)
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#define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16))
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#define BCI_CMD_SEND_COLOR 0x00008000
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#define DISP_CRT 1
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#define DISP_LCD 2
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#define DISP_DFP 3
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struct xtimings {
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unsigned int Clock;
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unsigned int HDisplay;
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unsigned int HSyncStart;
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unsigned int HSyncEnd;
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unsigned int HTotal;
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unsigned int HAdjusted;
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unsigned int VDisplay;
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unsigned int VSyncStart;
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unsigned int VSyncEnd;
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unsigned int VTotal;
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unsigned int sync;
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int dblscan;
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int interlaced;
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};
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struct savage_reg {
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unsigned char MiscOutReg; /* Misc */
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unsigned char CRTC[25]; /* Crtc Controller */
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unsigned char Sequencer[5]; /* Video Sequencer */
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unsigned char Graphics[9]; /* Video Graphics */
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unsigned char Attribute[21]; /* Video Attribute */
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unsigned int mode, refresh;
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unsigned char SR08, SR0E, SR0F;
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unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR29, SR30;
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unsigned char SR54[8];
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unsigned char Clock;
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unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C;
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unsigned char CR40, CR41, CR42, CR43, CR45;
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unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E;
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unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F;
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unsigned char CR86, CR88;
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unsigned char CR90, CR91, CRB0;
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unsigned int STREAMS[22]; /* yuck, streams regs */
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unsigned int MMPR0, MMPR1, MMPR2, MMPR3;
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};
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/* --------------------------------------------------------------------- */
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#define NR_PALETTE 256
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struct savagefb_par;
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struct savagefb_i2c_chan {
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struct savagefb_par *par;
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struct i2c_adapter adapter;
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struct i2c_algo_bit_data algo;
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volatile u8 __iomem *ioaddr;
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u32 reg;
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};
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struct savagefb_par {
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struct pci_dev *pcidev;
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savage_chipset chip;
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struct savagefb_i2c_chan chan;
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struct savage_reg state;
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struct savage_reg save;
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struct savage_reg initial;
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struct vgastate vgastate;
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struct mutex open_lock;
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unsigned char *edid;
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u32 pseudo_palette[16];
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u32 open_count;
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int paletteEnabled;
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int pm_state;
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int display_type;
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int dvi;
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int crtonly;
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int dacSpeedBpp;
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int maxClock;
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int minClock;
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int numClocks;
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int clock[4];
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int MCLK, REFCLK, LCDclk;
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struct {
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void __iomem *vbase;
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u32 pbase;
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u32 len;
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int wc_cookie;
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} video;
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struct {
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void __iomem *vbase;
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u32 pbase;
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u32 len;
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} mmio;
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volatile u32 __iomem *bci_base;
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unsigned int bci_ptr;
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u32 cob_offset;
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u32 cob_size;
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int cob_index;
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void (*SavageWaitIdle) (struct savagefb_par *par);
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void (*SavageWaitFifo) (struct savagefb_par *par, int space);
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int HorizScaleFactor;
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/* Panels size */
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int SavagePanelWidth;
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int SavagePanelHeight;
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struct {
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u16 red, green, blue, transp;
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} palette[NR_PALETTE];
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int depth;
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int vwidth;
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};
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#define BCI_BD_BW_DISABLE 0x10000000
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#define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16))
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#define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF))
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/* IO functions */
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static inline u8 savage_in8(u32 addr, struct savagefb_par *par)
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{
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return readb(par->mmio.vbase + addr);
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}
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static inline u16 savage_in16(u32 addr, struct savagefb_par *par)
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{
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return readw(par->mmio.vbase + addr);
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}
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static inline u32 savage_in32(u32 addr, struct savagefb_par *par)
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{
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return readl(par->mmio.vbase + addr);
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}
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static inline void savage_out8(u32 addr, u8 val, struct savagefb_par *par)
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{
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writeb(val, par->mmio.vbase + addr);
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}
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static inline void savage_out16(u32 addr, u16 val, struct savagefb_par *par)
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{
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writew(val, par->mmio.vbase + addr);
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}
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static inline void savage_out32(u32 addr, u32 val, struct savagefb_par *par)
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{
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writel(val, par->mmio.vbase + addr);
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}
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static inline u8 vga_in8(int addr, struct savagefb_par *par)
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{
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return savage_in8(0x8000 + addr, par);
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}
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static inline u16 vga_in16(int addr, struct savagefb_par *par)
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{
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return savage_in16(0x8000 + addr, par);
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}
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static inline u8 vga_in32(int addr, struct savagefb_par *par)
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{
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return savage_in32(0x8000 + addr, par);
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}
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static inline void vga_out8(int addr, u8 val, struct savagefb_par *par)
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{
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savage_out8(0x8000 + addr, val, par);
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}
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static inline void vga_out16(int addr, u16 val, struct savagefb_par *par)
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{
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savage_out16(0x8000 + addr, val, par);
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}
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static inline void vga_out32(int addr, u32 val, struct savagefb_par *par)
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{
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savage_out32(0x8000 + addr, val, par);
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}
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static inline u8 VGArCR (u8 index, struct savagefb_par *par)
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{
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vga_out8(0x3d4, index, par);
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return vga_in8(0x3d5, par);
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}
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static inline u8 VGArGR (u8 index, struct savagefb_par *par)
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{
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vga_out8(0x3ce, index, par);
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return vga_in8(0x3cf, par);
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}
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static inline u8 VGArSEQ (u8 index, struct savagefb_par *par)
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{
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vga_out8(0x3c4, index, par);
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return vga_in8(0x3c5, par);
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}
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static inline void VGAwCR(u8 index, u8 val, struct savagefb_par *par)
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{
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vga_out8(0x3d4, index, par);
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vga_out8(0x3d5, val, par);
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}
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static inline void VGAwGR(u8 index, u8 val, struct savagefb_par *par)
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{
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vga_out8(0x3ce, index, par);
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vga_out8(0x3cf, val, par);
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}
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static inline void VGAwSEQ(u8 index, u8 val, struct savagefb_par *par)
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{
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vga_out8(0x3c4, index, par);
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vga_out8 (0x3c5, val, par);
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}
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static inline void VGAenablePalette(struct savagefb_par *par)
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{
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vga_in8(0x3da, par);
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vga_out8(0x3c0, 0x00, par);
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par->paletteEnabled = 1;
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}
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static inline void VGAdisablePalette(struct savagefb_par *par)
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{
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vga_in8(0x3da, par);
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vga_out8(0x3c0, 0x20, par);
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par->paletteEnabled = 0;
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}
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static inline void VGAwATTR(u8 index, u8 value, struct savagefb_par *par)
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{
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if (par->paletteEnabled)
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index &= ~0x20;
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else
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index |= 0x20;
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vga_in8(0x3da, par);
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vga_out8(0x3c0, index, par);
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vga_out8 (0x3c0, value, par);
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}
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static inline void VGAwMISC(u8 value, struct savagefb_par *par)
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{
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vga_out8(0x3c2, value, par);
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}
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#ifndef CONFIG_FB_SAVAGE_ACCEL
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#define savagefb_set_clip(x)
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#endif
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static inline void VerticalRetraceWait(struct savagefb_par *par)
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{
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vga_out8(0x3d4, 0x17, par);
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if (vga_in8(0x3d5, par) & 0x80) {
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while ((vga_in8(0x3da, par) & 0x08) == 0x08);
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while ((vga_in8(0x3da, par) & 0x08) == 0x00);
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}
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}
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extern int savagefb_probe_i2c_connector(struct fb_info *info,
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u8 **out_edid);
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extern void savagefb_create_i2c_busses(struct fb_info *info);
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extern void savagefb_delete_i2c_busses(struct fb_info *info);
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extern int savagefb_sync(struct fb_info *info);
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extern void savagefb_copyarea(struct fb_info *info,
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const struct fb_copyarea *region);
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extern void savagefb_fillrect(struct fb_info *info,
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const struct fb_fillrect *rect);
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extern void savagefb_imageblit(struct fb_info *info,
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const struct fb_image *image);
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#endif /* __SAVAGEFB_H__ */
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