920 lines
22 KiB
C
920 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Driver for SA11x0 serial ports
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*
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* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
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*
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*/
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#if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/platform_data/sa11x0-serial.h>
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#include <linux/platform_device.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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/* We've been assigned a range on the "Low-density serial ports" major */
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#define SERIAL_SA1100_MAJOR 204
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#define MINOR_START 5
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#define NR_PORTS 3
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#define SA1100_ISR_PASS_LIMIT 256
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/*
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* Convert from ignore_status_mask or read_status_mask to UTSR[01]
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*/
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#define SM_TO_UTSR0(x) ((x) & 0xff)
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#define SM_TO_UTSR1(x) ((x) >> 8)
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#define UTSR0_TO_SM(x) ((x))
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#define UTSR1_TO_SM(x) ((x) << 8)
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#define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
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#define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
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#define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
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#define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
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#define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
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#define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
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#define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
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#define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
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#define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
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#define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
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#define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
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#define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
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#define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
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#define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
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/*
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* This is the size of our serial port register set.
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*/
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#define UART_PORT_SIZE 0x24
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/*
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* This determines how often we check the modem status signals
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* for any change. They generally aren't connected to an IRQ
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* so we have to poll them. We also check immediately before
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* filling the TX fifo incase CTS has been dropped.
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*/
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#define MCTRL_TIMEOUT (250*HZ/1000)
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struct sa1100_port {
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struct uart_port port;
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struct timer_list timer;
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unsigned int old_status;
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};
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/*
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* Handle any change of modem status signal since we were last called.
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*/
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static void sa1100_mctrl_check(struct sa1100_port *sport)
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{
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unsigned int status, changed;
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status = sport->port.ops->get_mctrl(&sport->port);
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changed = status ^ sport->old_status;
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if (changed == 0)
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return;
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sport->old_status = status;
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if (changed & TIOCM_RI)
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sport->port.icount.rng++;
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if (changed & TIOCM_DSR)
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sport->port.icount.dsr++;
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if (changed & TIOCM_CAR)
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uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
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if (changed & TIOCM_CTS)
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uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
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wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
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}
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/*
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* This is our per-port timeout handler, for checking the
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* modem status signals.
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*/
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static void sa1100_timeout(struct timer_list *t)
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{
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struct sa1100_port *sport = from_timer(sport, t, timer);
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unsigned long flags;
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if (sport->port.state) {
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spin_lock_irqsave(&sport->port.lock, flags);
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sa1100_mctrl_check(sport);
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spin_unlock_irqrestore(&sport->port.lock, flags);
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mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
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}
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}
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/*
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* interrupts disabled on entry
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*/
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static void sa1100_stop_tx(struct uart_port *port)
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{
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struct sa1100_port *sport =
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container_of(port, struct sa1100_port, port);
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u32 utcr3;
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utcr3 = UART_GET_UTCR3(sport);
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UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE);
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sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS);
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}
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/*
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* port locked and interrupts disabled
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*/
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static void sa1100_start_tx(struct uart_port *port)
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{
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struct sa1100_port *sport =
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container_of(port, struct sa1100_port, port);
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u32 utcr3;
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utcr3 = UART_GET_UTCR3(sport);
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sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS);
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UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE);
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}
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/*
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* Interrupts enabled
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*/
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static void sa1100_stop_rx(struct uart_port *port)
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{
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struct sa1100_port *sport =
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container_of(port, struct sa1100_port, port);
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u32 utcr3;
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utcr3 = UART_GET_UTCR3(sport);
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UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE);
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}
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/*
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* Set the modem control timer to fire immediately.
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*/
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static void sa1100_enable_ms(struct uart_port *port)
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{
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struct sa1100_port *sport =
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container_of(port, struct sa1100_port, port);
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mod_timer(&sport->timer, jiffies);
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}
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static void
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sa1100_rx_chars(struct sa1100_port *sport)
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{
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unsigned int status, ch, flg;
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status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
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UTSR0_TO_SM(UART_GET_UTSR0(sport));
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while (status & UTSR1_TO_SM(UTSR1_RNE)) {
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ch = UART_GET_CHAR(sport);
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sport->port.icount.rx++;
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flg = TTY_NORMAL;
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/*
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* note that the error handling code is
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* out of the main execution path
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*/
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if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) {
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if (status & UTSR1_TO_SM(UTSR1_PRE))
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sport->port.icount.parity++;
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else if (status & UTSR1_TO_SM(UTSR1_FRE))
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sport->port.icount.frame++;
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if (status & UTSR1_TO_SM(UTSR1_ROR))
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sport->port.icount.overrun++;
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status &= sport->port.read_status_mask;
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if (status & UTSR1_TO_SM(UTSR1_PRE))
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flg = TTY_PARITY;
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else if (status & UTSR1_TO_SM(UTSR1_FRE))
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flg = TTY_FRAME;
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#ifdef SUPPORT_SYSRQ
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sport->port.sysrq = 0;
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#endif
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}
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if (uart_handle_sysrq_char(&sport->port, ch))
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goto ignore_char;
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uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg);
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ignore_char:
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status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
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UTSR0_TO_SM(UART_GET_UTSR0(sport));
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}
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spin_unlock(&sport->port.lock);
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tty_flip_buffer_push(&sport->port.state->port);
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spin_lock(&sport->port.lock);
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}
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static void sa1100_tx_chars(struct sa1100_port *sport)
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{
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struct circ_buf *xmit = &sport->port.state->xmit;
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if (sport->port.x_char) {
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UART_PUT_CHAR(sport, sport->port.x_char);
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sport->port.icount.tx++;
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sport->port.x_char = 0;
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return;
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}
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/*
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* Check the modem control lines before
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* transmitting anything.
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*/
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sa1100_mctrl_check(sport);
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if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
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sa1100_stop_tx(&sport->port);
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return;
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}
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/*
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* Tried using FIFO (not checking TNF) for fifo fill:
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* still had the '4 bytes repeated' problem.
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*/
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while (UART_GET_UTSR1(sport) & UTSR1_TNF) {
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UART_PUT_CHAR(sport, xmit->buf[xmit->tail]);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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sport->port.icount.tx++;
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if (uart_circ_empty(xmit))
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break;
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(&sport->port);
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if (uart_circ_empty(xmit))
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sa1100_stop_tx(&sport->port);
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}
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static irqreturn_t sa1100_int(int irq, void *dev_id)
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{
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struct sa1100_port *sport = dev_id;
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unsigned int status, pass_counter = 0;
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spin_lock(&sport->port.lock);
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status = UART_GET_UTSR0(sport);
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status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
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do {
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if (status & (UTSR0_RFS | UTSR0_RID)) {
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/* Clear the receiver idle bit, if set */
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if (status & UTSR0_RID)
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UART_PUT_UTSR0(sport, UTSR0_RID);
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sa1100_rx_chars(sport);
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}
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/* Clear the relevant break bits */
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if (status & (UTSR0_RBB | UTSR0_REB))
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UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
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if (status & UTSR0_RBB)
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sport->port.icount.brk++;
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if (status & UTSR0_REB)
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uart_handle_break(&sport->port);
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if (status & UTSR0_TFS)
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sa1100_tx_chars(sport);
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if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
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break;
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status = UART_GET_UTSR0(sport);
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status &= SM_TO_UTSR0(sport->port.read_status_mask) |
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~UTSR0_TFS;
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} while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
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spin_unlock(&sport->port.lock);
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return IRQ_HANDLED;
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}
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/*
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* Return TIOCSER_TEMT when transmitter is not busy.
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*/
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static unsigned int sa1100_tx_empty(struct uart_port *port)
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{
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struct sa1100_port *sport =
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container_of(port, struct sa1100_port, port);
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return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT;
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}
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static unsigned int sa1100_get_mctrl(struct uart_port *port)
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{
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return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
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}
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static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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}
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/*
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* Interrupts always disabled.
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*/
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static void sa1100_break_ctl(struct uart_port *port, int break_state)
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{
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struct sa1100_port *sport =
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container_of(port, struct sa1100_port, port);
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unsigned long flags;
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unsigned int utcr3;
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spin_lock_irqsave(&sport->port.lock, flags);
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utcr3 = UART_GET_UTCR3(sport);
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if (break_state == -1)
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utcr3 |= UTCR3_BRK;
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else
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utcr3 &= ~UTCR3_BRK;
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UART_PUT_UTCR3(sport, utcr3);
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spin_unlock_irqrestore(&sport->port.lock, flags);
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}
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static int sa1100_startup(struct uart_port *port)
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{
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struct sa1100_port *sport =
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container_of(port, struct sa1100_port, port);
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int retval;
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/*
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* Allocate the IRQ
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*/
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retval = request_irq(sport->port.irq, sa1100_int, 0,
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"sa11x0-uart", sport);
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if (retval)
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return retval;
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/*
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* Finally, clear and enable interrupts
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*/
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UART_PUT_UTSR0(sport, -1);
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UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE);
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/*
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* Enable modem status interrupts
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*/
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spin_lock_irq(&sport->port.lock);
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sa1100_enable_ms(&sport->port);
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spin_unlock_irq(&sport->port.lock);
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return 0;
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}
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static void sa1100_shutdown(struct uart_port *port)
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{
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struct sa1100_port *sport =
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container_of(port, struct sa1100_port, port);
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/*
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* Stop our timer.
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*/
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del_timer_sync(&sport->timer);
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/*
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* Free the interrupt
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*/
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free_irq(sport->port.irq, sport);
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/*
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* Disable all interrupts, port and break condition.
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*/
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UART_PUT_UTCR3(sport, 0);
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}
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static void
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sa1100_set_termios(struct uart_port *port, struct ktermios *termios,
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struct ktermios *old)
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{
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struct sa1100_port *sport =
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container_of(port, struct sa1100_port, port);
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unsigned long flags;
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unsigned int utcr0, old_utcr3, baud, quot;
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unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
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/*
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* We only support CS7 and CS8.
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*/
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while ((termios->c_cflag & CSIZE) != CS7 &&
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(termios->c_cflag & CSIZE) != CS8) {
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termios->c_cflag &= ~CSIZE;
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termios->c_cflag |= old_csize;
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old_csize = CS8;
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}
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if ((termios->c_cflag & CSIZE) == CS8)
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utcr0 = UTCR0_DSS;
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else
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utcr0 = 0;
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if (termios->c_cflag & CSTOPB)
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utcr0 |= UTCR0_SBS;
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if (termios->c_cflag & PARENB) {
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utcr0 |= UTCR0_PE;
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if (!(termios->c_cflag & PARODD))
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utcr0 |= UTCR0_OES;
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}
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/*
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* Ask the core to calculate the divisor for us.
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*/
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baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
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quot = uart_get_divisor(port, baud);
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spin_lock_irqsave(&sport->port.lock, flags);
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sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
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sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
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if (termios->c_iflag & INPCK)
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sport->port.read_status_mask |=
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UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
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if (termios->c_iflag & (BRKINT | PARMRK))
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sport->port.read_status_mask |=
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UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
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/*
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* Characters to ignore
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*/
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sport->port.ignore_status_mask = 0;
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if (termios->c_iflag & IGNPAR)
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sport->port.ignore_status_mask |=
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UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
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if (termios->c_iflag & IGNBRK) {
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sport->port.ignore_status_mask |=
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UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
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/*
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* If we're ignoring parity and break indicators,
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* ignore overruns too (for real raw support).
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*/
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if (termios->c_iflag & IGNPAR)
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sport->port.ignore_status_mask |=
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UTSR1_TO_SM(UTSR1_ROR);
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}
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del_timer_sync(&sport->timer);
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/*
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* Update the per-port timeout.
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*/
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uart_update_timeout(port, termios->c_cflag, baud);
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/*
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* disable interrupts and drain transmitter
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*/
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old_utcr3 = UART_GET_UTCR3(sport);
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UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE));
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while (UART_GET_UTSR1(sport) & UTSR1_TBY)
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barrier();
|
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|
|
/* then, disable everything */
|
|
UART_PUT_UTCR3(sport, 0);
|
|
|
|
/* set the parity, stop bits and data size */
|
|
UART_PUT_UTCR0(sport, utcr0);
|
|
|
|
/* set the baud rate */
|
|
quot -= 1;
|
|
UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8));
|
|
UART_PUT_UTCR2(sport, (quot & 0xff));
|
|
|
|
UART_PUT_UTSR0(sport, -1);
|
|
|
|
UART_PUT_UTCR3(sport, old_utcr3);
|
|
|
|
if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
|
|
sa1100_enable_ms(&sport->port);
|
|
|
|
spin_unlock_irqrestore(&sport->port.lock, flags);
|
|
}
|
|
|
|
static const char *sa1100_type(struct uart_port *port)
|
|
{
|
|
struct sa1100_port *sport =
|
|
container_of(port, struct sa1100_port, port);
|
|
|
|
return sport->port.type == PORT_SA1100 ? "SA1100" : NULL;
|
|
}
|
|
|
|
/*
|
|
* Release the memory region(s) being used by 'port'.
|
|
*/
|
|
static void sa1100_release_port(struct uart_port *port)
|
|
{
|
|
struct sa1100_port *sport =
|
|
container_of(port, struct sa1100_port, port);
|
|
|
|
release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
|
|
}
|
|
|
|
/*
|
|
* Request the memory region(s) being used by 'port'.
|
|
*/
|
|
static int sa1100_request_port(struct uart_port *port)
|
|
{
|
|
struct sa1100_port *sport =
|
|
container_of(port, struct sa1100_port, port);
|
|
|
|
return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
|
|
"sa11x0-uart") != NULL ? 0 : -EBUSY;
|
|
}
|
|
|
|
/*
|
|
* Configure/autoconfigure the port.
|
|
*/
|
|
static void sa1100_config_port(struct uart_port *port, int flags)
|
|
{
|
|
struct sa1100_port *sport =
|
|
container_of(port, struct sa1100_port, port);
|
|
|
|
if (flags & UART_CONFIG_TYPE &&
|
|
sa1100_request_port(&sport->port) == 0)
|
|
sport->port.type = PORT_SA1100;
|
|
}
|
|
|
|
/*
|
|
* Verify the new serial_struct (for TIOCSSERIAL).
|
|
* The only change we allow are to the flags and type, and
|
|
* even then only between PORT_SA1100 and PORT_UNKNOWN
|
|
*/
|
|
static int
|
|
sa1100_verify_port(struct uart_port *port, struct serial_struct *ser)
|
|
{
|
|
struct sa1100_port *sport =
|
|
container_of(port, struct sa1100_port, port);
|
|
int ret = 0;
|
|
|
|
if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100)
|
|
ret = -EINVAL;
|
|
if (sport->port.irq != ser->irq)
|
|
ret = -EINVAL;
|
|
if (ser->io_type != SERIAL_IO_MEM)
|
|
ret = -EINVAL;
|
|
if (sport->port.uartclk / 16 != ser->baud_base)
|
|
ret = -EINVAL;
|
|
if ((void *)sport->port.mapbase != ser->iomem_base)
|
|
ret = -EINVAL;
|
|
if (sport->port.iobase != ser->port)
|
|
ret = -EINVAL;
|
|
if (ser->hub6 != 0)
|
|
ret = -EINVAL;
|
|
return ret;
|
|
}
|
|
|
|
static struct uart_ops sa1100_pops = {
|
|
.tx_empty = sa1100_tx_empty,
|
|
.set_mctrl = sa1100_set_mctrl,
|
|
.get_mctrl = sa1100_get_mctrl,
|
|
.stop_tx = sa1100_stop_tx,
|
|
.start_tx = sa1100_start_tx,
|
|
.stop_rx = sa1100_stop_rx,
|
|
.enable_ms = sa1100_enable_ms,
|
|
.break_ctl = sa1100_break_ctl,
|
|
.startup = sa1100_startup,
|
|
.shutdown = sa1100_shutdown,
|
|
.set_termios = sa1100_set_termios,
|
|
.type = sa1100_type,
|
|
.release_port = sa1100_release_port,
|
|
.request_port = sa1100_request_port,
|
|
.config_port = sa1100_config_port,
|
|
.verify_port = sa1100_verify_port,
|
|
};
|
|
|
|
static struct sa1100_port sa1100_ports[NR_PORTS];
|
|
|
|
/*
|
|
* Setup the SA1100 serial ports. Note that we don't include the IrDA
|
|
* port here since we have our own SIR/FIR driver (see drivers/net/irda)
|
|
*
|
|
* Note also that we support "console=ttySAx" where "x" is either 0 or 1.
|
|
* Which serial port this ends up being depends on the machine you're
|
|
* running this kernel on. I'm not convinced that this is a good idea,
|
|
* but that's the way it traditionally works.
|
|
*
|
|
* Note that NanoEngine UART3 becomes UART2, and UART2 is no longer
|
|
* used here.
|
|
*/
|
|
static void __init sa1100_init_ports(void)
|
|
{
|
|
static int first = 1;
|
|
int i;
|
|
|
|
if (!first)
|
|
return;
|
|
first = 0;
|
|
|
|
for (i = 0; i < NR_PORTS; i++) {
|
|
sa1100_ports[i].port.uartclk = 3686400;
|
|
sa1100_ports[i].port.ops = &sa1100_pops;
|
|
sa1100_ports[i].port.fifosize = 8;
|
|
sa1100_ports[i].port.line = i;
|
|
sa1100_ports[i].port.iotype = UPIO_MEM;
|
|
timer_setup(&sa1100_ports[i].timer, sa1100_timeout, 0);
|
|
}
|
|
|
|
/*
|
|
* make transmit lines outputs, so that when the port
|
|
* is closed, the output is in the MARK state.
|
|
*/
|
|
PPDR |= PPC_TXD1 | PPC_TXD3;
|
|
PPSR |= PPC_TXD1 | PPC_TXD3;
|
|
}
|
|
|
|
void sa1100_register_uart_fns(struct sa1100_port_fns *fns)
|
|
{
|
|
if (fns->get_mctrl)
|
|
sa1100_pops.get_mctrl = fns->get_mctrl;
|
|
if (fns->set_mctrl)
|
|
sa1100_pops.set_mctrl = fns->set_mctrl;
|
|
|
|
sa1100_pops.pm = fns->pm;
|
|
/*
|
|
* FIXME: fns->set_wake is unused - this should be called from
|
|
* the suspend() callback if device_may_wakeup(dev)) is set.
|
|
*/
|
|
}
|
|
|
|
void __init sa1100_register_uart(int idx, int port)
|
|
{
|
|
if (idx >= NR_PORTS) {
|
|
printk(KERN_ERR "%s: bad index number %d\n", __func__, idx);
|
|
return;
|
|
}
|
|
|
|
switch (port) {
|
|
case 1:
|
|
sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0;
|
|
sa1100_ports[idx].port.mapbase = _Ser1UTCR0;
|
|
sa1100_ports[idx].port.irq = IRQ_Ser1UART;
|
|
sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
|
|
break;
|
|
|
|
case 2:
|
|
sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0;
|
|
sa1100_ports[idx].port.mapbase = _Ser2UTCR0;
|
|
sa1100_ports[idx].port.irq = IRQ_Ser2ICP;
|
|
sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
|
|
break;
|
|
|
|
case 3:
|
|
sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0;
|
|
sa1100_ports[idx].port.mapbase = _Ser3UTCR0;
|
|
sa1100_ports[idx].port.irq = IRQ_Ser3UART;
|
|
sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
|
|
break;
|
|
|
|
default:
|
|
printk(KERN_ERR "%s: bad port number %d\n", __func__, port);
|
|
}
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_SERIAL_SA1100_CONSOLE
|
|
static void sa1100_console_putchar(struct uart_port *port, int ch)
|
|
{
|
|
struct sa1100_port *sport =
|
|
container_of(port, struct sa1100_port, port);
|
|
|
|
while (!(UART_GET_UTSR1(sport) & UTSR1_TNF))
|
|
barrier();
|
|
UART_PUT_CHAR(sport, ch);
|
|
}
|
|
|
|
/*
|
|
* Interrupts are disabled on entering
|
|
*/
|
|
static void
|
|
sa1100_console_write(struct console *co, const char *s, unsigned int count)
|
|
{
|
|
struct sa1100_port *sport = &sa1100_ports[co->index];
|
|
unsigned int old_utcr3, status;
|
|
|
|
/*
|
|
* First, save UTCR3 and then disable interrupts
|
|
*/
|
|
old_utcr3 = UART_GET_UTCR3(sport);
|
|
UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) |
|
|
UTCR3_TXE);
|
|
|
|
uart_console_write(&sport->port, s, count, sa1100_console_putchar);
|
|
|
|
/*
|
|
* Finally, wait for transmitter to become empty
|
|
* and restore UTCR3
|
|
*/
|
|
do {
|
|
status = UART_GET_UTSR1(sport);
|
|
} while (status & UTSR1_TBY);
|
|
UART_PUT_UTCR3(sport, old_utcr3);
|
|
}
|
|
|
|
/*
|
|
* If the port was already initialised (eg, by a boot loader),
|
|
* try to determine the current setup.
|
|
*/
|
|
static void __init
|
|
sa1100_console_get_options(struct sa1100_port *sport, int *baud,
|
|
int *parity, int *bits)
|
|
{
|
|
unsigned int utcr3;
|
|
|
|
utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE);
|
|
if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) {
|
|
/* ok, the port was enabled */
|
|
unsigned int utcr0, quot;
|
|
|
|
utcr0 = UART_GET_UTCR0(sport);
|
|
|
|
*parity = 'n';
|
|
if (utcr0 & UTCR0_PE) {
|
|
if (utcr0 & UTCR0_OES)
|
|
*parity = 'e';
|
|
else
|
|
*parity = 'o';
|
|
}
|
|
|
|
if (utcr0 & UTCR0_DSS)
|
|
*bits = 8;
|
|
else
|
|
*bits = 7;
|
|
|
|
quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8;
|
|
quot &= 0xfff;
|
|
*baud = sport->port.uartclk / (16 * (quot + 1));
|
|
}
|
|
}
|
|
|
|
static int __init
|
|
sa1100_console_setup(struct console *co, char *options)
|
|
{
|
|
struct sa1100_port *sport;
|
|
int baud = 9600;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
|
|
/*
|
|
* Check whether an invalid uart number has been specified, and
|
|
* if so, search for the first available port that does have
|
|
* console support.
|
|
*/
|
|
if (co->index == -1 || co->index >= NR_PORTS)
|
|
co->index = 0;
|
|
sport = &sa1100_ports[co->index];
|
|
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
else
|
|
sa1100_console_get_options(sport, &baud, &parity, &bits);
|
|
|
|
return uart_set_options(&sport->port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct uart_driver sa1100_reg;
|
|
static struct console sa1100_console = {
|
|
.name = "ttySA",
|
|
.write = sa1100_console_write,
|
|
.device = uart_console_device,
|
|
.setup = sa1100_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
.data = &sa1100_reg,
|
|
};
|
|
|
|
static int __init sa1100_rs_console_init(void)
|
|
{
|
|
sa1100_init_ports();
|
|
register_console(&sa1100_console);
|
|
return 0;
|
|
}
|
|
console_initcall(sa1100_rs_console_init);
|
|
|
|
#define SA1100_CONSOLE &sa1100_console
|
|
#else
|
|
#define SA1100_CONSOLE NULL
|
|
#endif
|
|
|
|
static struct uart_driver sa1100_reg = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = "ttySA",
|
|
.dev_name = "ttySA",
|
|
.major = SERIAL_SA1100_MAJOR,
|
|
.minor = MINOR_START,
|
|
.nr = NR_PORTS,
|
|
.cons = SA1100_CONSOLE,
|
|
};
|
|
|
|
static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
struct sa1100_port *sport = platform_get_drvdata(dev);
|
|
|
|
if (sport)
|
|
uart_suspend_port(&sa1100_reg, &sport->port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sa1100_serial_resume(struct platform_device *dev)
|
|
{
|
|
struct sa1100_port *sport = platform_get_drvdata(dev);
|
|
|
|
if (sport)
|
|
uart_resume_port(&sa1100_reg, &sport->port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sa1100_serial_probe(struct platform_device *dev)
|
|
{
|
|
struct resource *res = dev->resource;
|
|
int i;
|
|
|
|
for (i = 0; i < dev->num_resources; i++, res++)
|
|
if (res->flags & IORESOURCE_MEM)
|
|
break;
|
|
|
|
if (i < dev->num_resources) {
|
|
for (i = 0; i < NR_PORTS; i++) {
|
|
if (sa1100_ports[i].port.mapbase != res->start)
|
|
continue;
|
|
|
|
sa1100_ports[i].port.dev = &dev->dev;
|
|
uart_add_one_port(&sa1100_reg, &sa1100_ports[i].port);
|
|
platform_set_drvdata(dev, &sa1100_ports[i]);
|
|
break;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sa1100_serial_remove(struct platform_device *pdev)
|
|
{
|
|
struct sa1100_port *sport = platform_get_drvdata(pdev);
|
|
|
|
if (sport)
|
|
uart_remove_one_port(&sa1100_reg, &sport->port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver sa11x0_serial_driver = {
|
|
.probe = sa1100_serial_probe,
|
|
.remove = sa1100_serial_remove,
|
|
.suspend = sa1100_serial_suspend,
|
|
.resume = sa1100_serial_resume,
|
|
.driver = {
|
|
.name = "sa11x0-uart",
|
|
},
|
|
};
|
|
|
|
static int __init sa1100_serial_init(void)
|
|
{
|
|
int ret;
|
|
|
|
printk(KERN_INFO "Serial: SA11x0 driver\n");
|
|
|
|
sa1100_init_ports();
|
|
|
|
ret = uart_register_driver(&sa1100_reg);
|
|
if (ret == 0) {
|
|
ret = platform_driver_register(&sa11x0_serial_driver);
|
|
if (ret)
|
|
uart_unregister_driver(&sa1100_reg);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static void __exit sa1100_serial_exit(void)
|
|
{
|
|
platform_driver_unregister(&sa11x0_serial_driver);
|
|
uart_unregister_driver(&sa1100_reg);
|
|
}
|
|
|
|
module_init(sa1100_serial_init);
|
|
module_exit(sa1100_serial_exit);
|
|
|
|
MODULE_AUTHOR("Deep Blue Solutions Ltd");
|
|
MODULE_DESCRIPTION("SA1100 generic serial port driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR);
|
|
MODULE_ALIAS("platform:sa11x0-uart");
|