262 lines
9.3 KiB
C
262 lines
9.3 KiB
C
/*
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* DRA752 bandgap registers, bitfields and temperature definitions
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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* Contact:
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* Eduardo Valentin <eduardo.valentin@ti.com>
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* Tero Kristo <t-kristo@ti.com>
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*
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* This is an auto generated file.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __DRA752_BANDGAP_H
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#define __DRA752_BANDGAP_H
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/**
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* *** DRA752 ***
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*
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* Below, in sequence, are the Register definitions,
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* the bitfields and the temperature definitions for DRA752.
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*/
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/**
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* DRA752 register definitions
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*
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* Registers are defined as offsets. The offsets are
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* relative to FUSE_OPP_BGAP_GPU on DRA752.
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* DRA752_BANDGAP_BASE 0x4a0021e0
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*
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* Register below are grouped by domain (not necessarily in offset order)
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*/
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/* DRA752.common register offsets */
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#define DRA752_BANDGAP_CTRL_1_OFFSET 0x1a0
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#define DRA752_BANDGAP_STATUS_1_OFFSET 0x1c8
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#define DRA752_BANDGAP_CTRL_2_OFFSET 0x39c
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#define DRA752_BANDGAP_STATUS_2_OFFSET 0x3b8
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/* DRA752.core register offsets */
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#define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8
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#define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154
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#define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac
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#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET 0x1c4
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#define DRA752_DTEMP_CORE_0_OFFSET 0x208
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#define DRA752_DTEMP_CORE_1_OFFSET 0x20c
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#define DRA752_DTEMP_CORE_2_OFFSET 0x210
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#define DRA752_DTEMP_CORE_3_OFFSET 0x214
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#define DRA752_DTEMP_CORE_4_OFFSET 0x218
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/* DRA752.iva register offsets */
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#define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388
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#define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398
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#define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4
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#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET 0x3b4
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#define DRA752_DTEMP_IVA_0_OFFSET 0x3d0
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#define DRA752_DTEMP_IVA_1_OFFSET 0x3d4
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#define DRA752_DTEMP_IVA_2_OFFSET 0x3d8
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#define DRA752_DTEMP_IVA_3_OFFSET 0x3dc
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#define DRA752_DTEMP_IVA_4_OFFSET 0x3e0
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/* DRA752.mpu register offsets */
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#define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4
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#define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c
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#define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4
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#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET 0x1bc
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#define DRA752_DTEMP_MPU_0_OFFSET 0x1e0
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#define DRA752_DTEMP_MPU_1_OFFSET 0x1e4
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#define DRA752_DTEMP_MPU_2_OFFSET 0x1e8
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#define DRA752_DTEMP_MPU_3_OFFSET 0x1ec
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#define DRA752_DTEMP_MPU_4_OFFSET 0x1f0
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/* DRA752.dspeve register offsets */
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#define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384
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#define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394
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#define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0
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#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET 0x3b0
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#define DRA752_DTEMP_DSPEVE_0_OFFSET 0x3bc
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#define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0
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#define DRA752_DTEMP_DSPEVE_2_OFFSET 0x3c4
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#define DRA752_DTEMP_DSPEVE_3_OFFSET 0x3c8
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#define DRA752_DTEMP_DSPEVE_4_OFFSET 0x3cc
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/* DRA752.gpu register offsets */
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#define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0
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#define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150
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#define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8
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#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET 0x1c0
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#define DRA752_DTEMP_GPU_0_OFFSET 0x1f4
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#define DRA752_DTEMP_GPU_1_OFFSET 0x1f8
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#define DRA752_DTEMP_GPU_2_OFFSET 0x1fc
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#define DRA752_DTEMP_GPU_3_OFFSET 0x200
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#define DRA752_DTEMP_GPU_4_OFFSET 0x204
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/**
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* Register bitfields for DRA752
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*
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* All the macros bellow define the required bits for
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* controlling temperature on DRA752. Bit defines are
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* grouped by register.
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*/
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/* DRA752.BANDGAP_STATUS_1 */
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#define DRA752_BANDGAP_STATUS_1_ALERT_MASK BIT(31)
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#define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5)
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#define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4)
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#define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3)
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#define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK BIT(2)
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#define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK BIT(1)
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#define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK BIT(0)
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/* DRA752.BANDGAP_CTRL_2 */
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#define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22)
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#define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21)
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#define DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK BIT(19)
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#define DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK BIT(18)
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#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK BIT(16)
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#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK BIT(15)
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#define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3)
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#define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2)
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#define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1)
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#define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK BIT(0)
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/* DRA752.BANDGAP_STATUS_2 */
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#define DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK BIT(3)
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#define DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK BIT(2)
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#define DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK BIT(1)
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#define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0)
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/* DRA752.BANDGAP_CTRL_1 */
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#define DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK (0x3 << 30)
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#define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK (0x7 << 27)
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#define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23)
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#define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22)
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#define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21)
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#define DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK BIT(20)
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#define DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK BIT(19)
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#define DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK BIT(18)
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#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK BIT(17)
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#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK BIT(16)
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#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK BIT(15)
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#define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5)
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#define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4)
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#define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3)
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#define DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK BIT(2)
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#define DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK BIT(1)
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#define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK BIT(0)
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/* DRA752.TEMP_SENSOR */
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#define DRA752_TEMP_SENSOR_TMPSOFF_MASK BIT(11)
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#define DRA752_TEMP_SENSOR_EOCZ_MASK BIT(10)
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#define DRA752_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
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/* DRA752.BANDGAP_THRESHOLD */
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#define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16)
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#define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0)
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/* DRA752.BANDGAP_CUMUL_DTEMP_CORE */
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#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_MASK (0xffffffff << 0)
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/* DRA752.BANDGAP_CUMUL_DTEMP_IVA */
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#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_MASK (0xffffffff << 0)
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/* DRA752.BANDGAP_CUMUL_DTEMP_MPU */
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#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_MASK (0xffffffff << 0)
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/* DRA752.BANDGAP_CUMUL_DTEMP_DSPEVE */
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#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_MASK (0xffffffff << 0)
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/* DRA752.BANDGAP_CUMUL_DTEMP_GPU */
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#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_MASK (0xffffffff << 0)
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/**
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* Temperature limits and thresholds for DRA752
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*
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* All the macros bellow are definitions for handling the
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* ADC conversions and representation of temperature limits
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* and thresholds for DRA752. Definitions are grouped
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* by temperature domain.
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*/
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/* DRA752.common temperature definitions */
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/* ADC conversion table limits */
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#define DRA752_ADC_START_VALUE 540
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#define DRA752_ADC_END_VALUE 945
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/* DRA752.GPU temperature definitions */
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/* bandgap clock limits */
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#define DRA752_GPU_MAX_FREQ 1500000
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#define DRA752_GPU_MIN_FREQ 1000000
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/* sensor limits */
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#define DRA752_GPU_MIN_TEMP -40000
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#define DRA752_GPU_MAX_TEMP 125000
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#define DRA752_GPU_HYST_VAL 5000
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/* interrupts thresholds */
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#define DRA752_GPU_T_HOT 800
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#define DRA752_GPU_T_COLD 795
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/* DRA752.MPU temperature definitions */
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/* bandgap clock limits */
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#define DRA752_MPU_MAX_FREQ 1500000
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#define DRA752_MPU_MIN_FREQ 1000000
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/* sensor limits */
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#define DRA752_MPU_MIN_TEMP -40000
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#define DRA752_MPU_MAX_TEMP 125000
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#define DRA752_MPU_HYST_VAL 5000
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/* interrupts thresholds */
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#define DRA752_MPU_T_HOT 800
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#define DRA752_MPU_T_COLD 795
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/* DRA752.CORE temperature definitions */
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/* bandgap clock limits */
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#define DRA752_CORE_MAX_FREQ 1500000
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#define DRA752_CORE_MIN_FREQ 1000000
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/* sensor limits */
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#define DRA752_CORE_MIN_TEMP -40000
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#define DRA752_CORE_MAX_TEMP 125000
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#define DRA752_CORE_HYST_VAL 5000
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/* interrupts thresholds */
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#define DRA752_CORE_T_HOT 800
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#define DRA752_CORE_T_COLD 795
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/* DRA752.DSPEVE temperature definitions */
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/* bandgap clock limits */
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#define DRA752_DSPEVE_MAX_FREQ 1500000
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#define DRA752_DSPEVE_MIN_FREQ 1000000
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/* sensor limits */
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#define DRA752_DSPEVE_MIN_TEMP -40000
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#define DRA752_DSPEVE_MAX_TEMP 125000
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#define DRA752_DSPEVE_HYST_VAL 5000
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/* interrupts thresholds */
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#define DRA752_DSPEVE_T_HOT 800
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#define DRA752_DSPEVE_T_COLD 795
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/* DRA752.IVA temperature definitions */
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/* bandgap clock limits */
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#define DRA752_IVA_MAX_FREQ 1500000
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#define DRA752_IVA_MIN_FREQ 1000000
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/* sensor limits */
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#define DRA752_IVA_MIN_TEMP -40000
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#define DRA752_IVA_MAX_TEMP 125000
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#define DRA752_IVA_HYST_VAL 5000
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/* interrupts thresholds */
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#define DRA752_IVA_T_HOT 800
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#define DRA752_IVA_T_COLD 795
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#endif /* __DRA752_BANDGAP_H */
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