607 lines
18 KiB
C
607 lines
18 KiB
C
/*
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* This file is part of the Chelsio FCoE driver for Linux.
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*
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* Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __CSIO_HW_H__
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#define __CSIO_HW_H__
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/device.h>
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#include <linux/workqueue.h>
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#include <linux/compiler.h>
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#include <linux/cdev.h>
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#include <linux/list.h>
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#include <linux/mempool.h>
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#include <linux/io.h>
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#include <linux/spinlock_types.h>
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#include <scsi/scsi_device.h>
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#include <scsi/scsi_transport_fc.h>
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#include "t4_hw.h"
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#include "csio_hw_chip.h"
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#include "csio_wr.h"
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#include "csio_mb.h"
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#include "csio_scsi.h"
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#include "csio_defs.h"
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#include "t4_regs.h"
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#include "t4_msg.h"
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/*
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* An error value used by host. Should not clash with FW defined return values.
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*/
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#define FW_HOSTERROR 255
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#define CSIO_HW_NAME "Chelsio FCoE Adapter"
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#define CSIO_MAX_PFN 8
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#define CSIO_MAX_PPORTS 4
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#define CSIO_MAX_LUN 0xFFFF
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#define CSIO_MAX_QUEUE 2048
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#define CSIO_MAX_CMD_PER_LUN 32
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#define CSIO_MAX_DDP_BUF_SIZE (1024 * 1024)
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#define CSIO_MAX_SECTOR_SIZE 128
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#define CSIO_MIN_T6_FW 0x01102D00 /* FW 1.16.45.0 */
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/* Interrupts */
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#define CSIO_EXTRA_MSI_IQS 2 /* Extra iqs for INTX/MSI mode
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* (Forward intr iq + fw iq) */
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#define CSIO_EXTRA_VECS 2 /* non-data + FW evt */
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#define CSIO_MAX_SCSI_CPU 128
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#define CSIO_MAX_SCSI_QSETS (CSIO_MAX_SCSI_CPU * CSIO_MAX_PPORTS)
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#define CSIO_MAX_MSIX_VECS (CSIO_MAX_SCSI_QSETS + CSIO_EXTRA_VECS)
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/* Queues */
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enum {
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CSIO_INTR_WRSIZE = 128,
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CSIO_INTR_IQSIZE = ((CSIO_MAX_MSIX_VECS + 1) * CSIO_INTR_WRSIZE),
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CSIO_FWEVT_WRSIZE = 128,
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CSIO_FWEVT_IQLEN = 128,
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CSIO_FWEVT_FLBUFS = 64,
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CSIO_FWEVT_IQSIZE = (CSIO_FWEVT_WRSIZE * CSIO_FWEVT_IQLEN),
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CSIO_HW_NIQ = 1,
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CSIO_HW_NFLQ = 1,
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CSIO_HW_NEQ = 1,
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CSIO_HW_NINTXQ = 1,
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};
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struct csio_msix_entries {
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void *dev_id; /* Priv object associated w/ this msix*/
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char desc[24]; /* Description of this vector */
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};
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struct csio_scsi_qset {
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int iq_idx; /* Ingress index */
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int eq_idx; /* Egress index */
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uint32_t intr_idx; /* MSIX Vector index */
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};
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struct csio_scsi_cpu_info {
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int16_t max_cpus;
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};
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extern int csio_dbg_level;
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extern unsigned int csio_port_mask;
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extern int csio_msi;
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#define CSIO_VENDOR_ID 0x1425
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#define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00
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#define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF
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#define CSIO_GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | \
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EDC0_F | EDC1_F | LE_F | TP_F | MA_F | \
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PM_TX_F | PM_RX_F | ULP_RX_F | \
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CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
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/*
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* Hard parameters used to initialize the card in the absence of a
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* configuration file.
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*/
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enum {
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/* General */
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CSIO_SGE_DBFIFO_INT_THRESH = 10,
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CSIO_SGE_RX_DMA_OFFSET = 2,
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CSIO_SGE_FLBUF_SIZE1 = 65536,
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CSIO_SGE_FLBUF_SIZE2 = 1536,
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CSIO_SGE_FLBUF_SIZE3 = 9024,
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CSIO_SGE_FLBUF_SIZE4 = 9216,
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CSIO_SGE_FLBUF_SIZE5 = 2048,
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CSIO_SGE_FLBUF_SIZE6 = 128,
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CSIO_SGE_FLBUF_SIZE7 = 8192,
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CSIO_SGE_FLBUF_SIZE8 = 16384,
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CSIO_SGE_TIMER_VAL_0 = 5,
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CSIO_SGE_TIMER_VAL_1 = 10,
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CSIO_SGE_TIMER_VAL_2 = 20,
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CSIO_SGE_TIMER_VAL_3 = 50,
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CSIO_SGE_TIMER_VAL_4 = 100,
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CSIO_SGE_TIMER_VAL_5 = 200,
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CSIO_SGE_INT_CNT_VAL_0 = 1,
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CSIO_SGE_INT_CNT_VAL_1 = 4,
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CSIO_SGE_INT_CNT_VAL_2 = 8,
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CSIO_SGE_INT_CNT_VAL_3 = 16,
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};
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/* Slowpath events */
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enum csio_evt {
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CSIO_EVT_FW = 0, /* FW event */
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CSIO_EVT_MBX, /* MBX event */
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CSIO_EVT_SCN, /* State change notification */
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CSIO_EVT_DEV_LOSS, /* Device loss event */
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CSIO_EVT_MAX, /* Max supported event */
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};
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#define CSIO_EVT_MSG_SIZE 512
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#define CSIO_EVTQ_SIZE 512
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/* Event msg */
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struct csio_evt_msg {
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struct list_head list; /* evt queue*/
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enum csio_evt type;
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uint8_t data[CSIO_EVT_MSG_SIZE];
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};
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enum {
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SERNUM_LEN = 16, /* Serial # length */
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EC_LEN = 16, /* E/C length */
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ID_LEN = 16, /* ID length */
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};
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enum {
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SF_SIZE = SF_SEC_SIZE * 16, /* serial flash size */
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};
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/* serial flash and firmware constants */
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enum {
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SF_ATTEMPTS = 10, /* max retries for SF operations */
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/* flash command opcodes */
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SF_PROG_PAGE = 2, /* program page */
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SF_WR_DISABLE = 4, /* disable writes */
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SF_RD_STATUS = 5, /* read status register */
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SF_WR_ENABLE = 6, /* enable writes */
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SF_RD_DATA_FAST = 0xb, /* read flash */
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SF_RD_ID = 0x9f, /* read ID */
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SF_ERASE_SECTOR = 0xd8, /* erase sector */
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};
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/* Management module */
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enum {
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CSIO_MGMT_EQ_WRSIZE = 512,
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CSIO_MGMT_IQ_WRSIZE = 128,
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CSIO_MGMT_EQLEN = 64,
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CSIO_MGMT_IQLEN = 64,
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};
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#define CSIO_MGMT_EQSIZE (CSIO_MGMT_EQLEN * CSIO_MGMT_EQ_WRSIZE)
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#define CSIO_MGMT_IQSIZE (CSIO_MGMT_IQLEN * CSIO_MGMT_IQ_WRSIZE)
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/* mgmt module stats */
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struct csio_mgmtm_stats {
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uint32_t n_abort_req; /* Total abort request */
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uint32_t n_abort_rsp; /* Total abort response */
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uint32_t n_close_req; /* Total close request */
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uint32_t n_close_rsp; /* Total close response */
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uint32_t n_err; /* Total Errors */
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uint32_t n_drop; /* Total request dropped */
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uint32_t n_active; /* Count of active_q */
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uint32_t n_cbfn; /* Count of cbfn_q */
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};
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/* MGMT module */
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struct csio_mgmtm {
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struct csio_hw *hw; /* Pointer to HW moduel */
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int eq_idx; /* Egress queue index */
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int iq_idx; /* Ingress queue index */
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int msi_vec; /* MSI vector */
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struct list_head active_q; /* Outstanding ELS/CT */
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struct list_head abort_q; /* Outstanding abort req */
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struct list_head cbfn_q; /* Completion queue */
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struct list_head mgmt_req_freelist; /* Free poll of reqs */
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/* ELSCT request freelist*/
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struct timer_list mgmt_timer; /* MGMT timer */
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struct csio_mgmtm_stats stats; /* ELS/CT stats */
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};
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struct csio_adap_desc {
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char model_no[16];
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char description[32];
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};
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struct pci_params {
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uint16_t vendor_id;
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uint16_t device_id;
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int vpd_cap_addr;
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uint16_t speed;
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uint8_t width;
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};
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/* User configurable hw parameters */
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struct csio_hw_params {
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uint32_t sf_size; /* serial flash
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* size in bytes
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*/
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uint32_t sf_nsec; /* # of flash sectors */
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struct pci_params pci;
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uint32_t log_level; /* Module-level for
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* debug log.
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*/
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};
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struct csio_vpd {
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uint32_t cclk;
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uint8_t ec[EC_LEN + 1];
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uint8_t sn[SERNUM_LEN + 1];
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uint8_t id[ID_LEN + 1];
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};
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struct csio_pport {
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uint16_t pcap;
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uint8_t portid;
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uint8_t link_status;
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uint16_t link_speed;
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uint8_t mac[6];
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uint8_t mod_type;
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uint8_t rsvd1;
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uint8_t rsvd2;
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uint8_t rsvd3;
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};
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/* fcoe resource information */
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struct csio_fcoe_res_info {
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uint16_t e_d_tov;
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uint16_t r_a_tov_seq;
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uint16_t r_a_tov_els;
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uint16_t r_r_tov;
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uint32_t max_xchgs;
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uint32_t max_ssns;
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uint32_t used_xchgs;
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uint32_t used_ssns;
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uint32_t max_fcfs;
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uint32_t max_vnps;
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uint32_t used_fcfs;
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uint32_t used_vnps;
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};
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/* HW State machine Events */
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enum csio_hw_ev {
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CSIO_HWE_CFG = (uint32_t)1, /* Starts off the State machine */
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CSIO_HWE_INIT, /* Config done, start Init */
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CSIO_HWE_INIT_DONE, /* Init Mailboxes sent, HW ready */
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CSIO_HWE_FATAL, /* Fatal error during initialization */
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CSIO_HWE_PCIERR_DETECTED,/* PCI error recovery detetced */
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CSIO_HWE_PCIERR_SLOT_RESET, /* Slot reset after PCI recoviery */
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CSIO_HWE_PCIERR_RESUME, /* Resume after PCI error recovery */
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CSIO_HWE_QUIESCED, /* HBA quiesced */
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CSIO_HWE_HBA_RESET, /* HBA reset requested */
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CSIO_HWE_HBA_RESET_DONE, /* HBA reset completed */
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CSIO_HWE_FW_DLOAD, /* FW download requested */
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CSIO_HWE_PCI_REMOVE, /* PCI de-instantiation */
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CSIO_HWE_SUSPEND, /* HW suspend for Online(hot) replacement */
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CSIO_HWE_RESUME, /* HW resume for Online(hot) replacement */
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CSIO_HWE_MAX, /* Max HW event */
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};
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/* hw stats */
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struct csio_hw_stats {
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uint32_t n_evt_activeq; /* Number of event in active Q */
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uint32_t n_evt_freeq; /* Number of event in free Q */
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uint32_t n_evt_drop; /* Number of event droped */
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uint32_t n_evt_unexp; /* Number of unexpected events */
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uint32_t n_pcich_offline;/* Number of pci channel offline */
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uint32_t n_lnlkup_miss; /* Number of lnode lookup miss */
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uint32_t n_cpl_fw6_msg; /* Number of cpl fw6 message*/
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uint32_t n_cpl_fw6_pld; /* Number of cpl fw6 payload*/
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uint32_t n_cpl_unexp; /* Number of unexpected cpl */
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uint32_t n_mbint_unexp; /* Number of unexpected mbox */
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/* interrupt */
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uint32_t n_plint_unexp; /* Number of unexpected PL */
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/* interrupt */
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uint32_t n_plint_cnt; /* Number of PL interrupt */
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uint32_t n_int_stray; /* Number of stray interrupt */
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uint32_t n_err; /* Number of hw errors */
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uint32_t n_err_fatal; /* Number of fatal errors */
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uint32_t n_err_nomem; /* Number of memory alloc failure */
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uint32_t n_err_io; /* Number of IO failure */
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enum csio_hw_ev n_evt_sm[CSIO_HWE_MAX]; /* Number of sm events */
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uint64_t n_reset_start; /* Start time after the reset */
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uint32_t rsvd1;
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};
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/* Defines for hw->flags */
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#define CSIO_HWF_MASTER 0x00000001 /* This is the Master
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* function for the
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* card.
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*/
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#define CSIO_HWF_HW_INTR_ENABLED 0x00000002 /* Are HW Interrupt
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* enable bit set?
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*/
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#define CSIO_HWF_FWEVT_PENDING 0x00000004 /* FW events pending */
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#define CSIO_HWF_Q_MEM_ALLOCED 0x00000008 /* Queues have been
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* allocated memory.
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*/
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#define CSIO_HWF_Q_FW_ALLOCED 0x00000010 /* Queues have been
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* allocated in FW.
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*/
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#define CSIO_HWF_VPD_VALID 0x00000020 /* Valid VPD copied */
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#define CSIO_HWF_DEVID_CACHED 0X00000040 /* PCI vendor & device
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* id cached */
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#define CSIO_HWF_FWEVT_STOP 0x00000080 /* Stop processing
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* FW events
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*/
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#define CSIO_HWF_USING_SOFT_PARAMS 0x00000100 /* Using FW config
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* params
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*/
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#define CSIO_HWF_HOST_INTR_ENABLED 0x00000200 /* Are host interrupts
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* enabled?
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*/
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#define CSIO_HWF_ROOT_NO_RELAXED_ORDERING 0x00000400 /* Is PCIe relaxed
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* ordering enabled
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*/
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#define csio_is_hw_intr_enabled(__hw) \
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((__hw)->flags & CSIO_HWF_HW_INTR_ENABLED)
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#define csio_is_host_intr_enabled(__hw) \
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((__hw)->flags & CSIO_HWF_HOST_INTR_ENABLED)
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#define csio_is_hw_master(__hw) ((__hw)->flags & CSIO_HWF_MASTER)
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#define csio_is_valid_vpd(__hw) ((__hw)->flags & CSIO_HWF_VPD_VALID)
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#define csio_is_dev_id_cached(__hw) ((__hw)->flags & CSIO_HWF_DEVID_CACHED)
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#define csio_valid_vpd_copied(__hw) ((__hw)->flags |= CSIO_HWF_VPD_VALID)
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#define csio_dev_id_cached(__hw) ((__hw)->flags |= CSIO_HWF_DEVID_CACHED)
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/* Defines for intr_mode */
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enum csio_intr_mode {
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CSIO_IM_NONE = 0,
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CSIO_IM_INTX = 1,
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CSIO_IM_MSI = 2,
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CSIO_IM_MSIX = 3,
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};
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/* Master HW structure: One per function */
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struct csio_hw {
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struct csio_sm sm; /* State machine: should
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* be the 1st member.
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*/
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spinlock_t lock; /* Lock for hw */
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struct csio_scsim scsim; /* SCSI module*/
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struct csio_wrm wrm; /* Work request module*/
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struct pci_dev *pdev; /* PCI device */
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void __iomem *regstart; /* Virtual address of
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* register map
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*/
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/* SCSI queue sets */
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uint32_t num_sqsets; /* Number of SCSI
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* queue sets */
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uint32_t num_scsi_msix_cpus; /* Number of CPUs that
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* will be used
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* for ingress
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* processing.
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*/
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struct csio_scsi_qset sqset[CSIO_MAX_PPORTS][CSIO_MAX_SCSI_CPU];
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struct csio_scsi_cpu_info scsi_cpu_info[CSIO_MAX_PPORTS];
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uint32_t evtflag; /* Event flag */
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uint32_t flags; /* HW flags */
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struct csio_mgmtm mgmtm; /* management module */
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struct csio_mbm mbm; /* Mailbox module */
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/* Lnodes */
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uint32_t num_lns; /* Number of lnodes */
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struct csio_lnode *rln; /* Root lnode */
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struct list_head sln_head; /* Sibling node list
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* list
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*/
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int intr_iq_idx; /* Forward interrupt
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* queue.
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*/
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int fwevt_iq_idx; /* FW evt queue */
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struct work_struct evtq_work; /* Worker thread for
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* HW events.
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*/
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struct list_head evt_free_q; /* freelist of evt
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* elements
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*/
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struct list_head evt_active_q; /* active evt queue*/
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/* board related info */
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char name[32];
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char hw_ver[16];
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char model_desc[32];
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char drv_version[32];
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char fwrev_str[32];
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uint32_t optrom_ver;
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uint32_t fwrev;
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uint32_t tp_vers;
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char chip_ver;
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uint16_t chip_id; /* Tells T4/T5 chip */
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enum csio_dev_state fw_state;
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struct csio_vpd vpd;
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uint8_t pfn; /* Physical Function
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* number
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*/
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uint32_t port_vec; /* Port vector */
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uint8_t num_pports; /* Number of physical
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* ports.
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*/
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uint8_t rst_retries; /* Reset retries */
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uint8_t cur_evt; /* current s/m evt */
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uint8_t prev_evt; /* Previous s/m evt */
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uint32_t dev_num; /* device number */
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struct csio_pport pport[CSIO_MAX_PPORTS]; /* Ports (XGMACs) */
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struct csio_hw_params params; /* Hw parameters */
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struct dma_pool *scsi_dma_pool; /* DMA pool for SCSI */
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mempool_t *mb_mempool; /* Mailbox memory pool*/
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mempool_t *rnode_mempool; /* rnode memory pool */
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/* Interrupt */
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enum csio_intr_mode intr_mode; /* INTx, MSI, MSIX */
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uint32_t fwevt_intr_idx; /* FW evt MSIX/interrupt
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* index
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*/
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uint32_t nondata_intr_idx; /* nondata MSIX/intr
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* idx
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*/
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uint8_t cfg_neq; /* FW configured no of
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* egress queues
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*/
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uint8_t cfg_niq; /* FW configured no of
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* iq queues.
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*/
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struct csio_fcoe_res_info fres_info; /* Fcoe resource info */
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struct csio_hw_chip_ops *chip_ops; /* T4/T5 Chip specific
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* Operations
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*/
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/* MSIX vectors */
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struct csio_msix_entries msix_entries[CSIO_MAX_MSIX_VECS];
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struct dentry *debugfs_root; /* Debug FS */
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struct csio_hw_stats stats; /* Hw statistics */
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};
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/* Register access macros */
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#define csio_reg(_b, _r) ((_b) + (_r))
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#define csio_rd_reg8(_h, _r) readb(csio_reg((_h)->regstart, (_r)))
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#define csio_rd_reg16(_h, _r) readw(csio_reg((_h)->regstart, (_r)))
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#define csio_rd_reg32(_h, _r) readl(csio_reg((_h)->regstart, (_r)))
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#define csio_rd_reg64(_h, _r) readq(csio_reg((_h)->regstart, (_r)))
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#define csio_wr_reg8(_h, _v, _r) writeb((_v), \
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csio_reg((_h)->regstart, (_r)))
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#define csio_wr_reg16(_h, _v, _r) writew((_v), \
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csio_reg((_h)->regstart, (_r)))
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#define csio_wr_reg32(_h, _v, _r) writel((_v), \
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csio_reg((_h)->regstart, (_r)))
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#define csio_wr_reg64(_h, _v, _r) writeq((_v), \
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csio_reg((_h)->regstart, (_r)))
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void csio_set_reg_field(struct csio_hw *, uint32_t, uint32_t, uint32_t);
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|
|
|
/* Core clocks <==> uSecs */
|
|
static inline uint32_t
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csio_core_ticks_to_us(struct csio_hw *hw, uint32_t ticks)
|
|
{
|
|
/* add Core Clock / 2 to round ticks to nearest uS */
|
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return (ticks * 1000 + hw->vpd.cclk/2) / hw->vpd.cclk;
|
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}
|
|
|
|
static inline uint32_t
|
|
csio_us_to_core_ticks(struct csio_hw *hw, uint32_t us)
|
|
{
|
|
return (us * hw->vpd.cclk) / 1000;
|
|
}
|
|
|
|
/* Easy access macros */
|
|
#define csio_hw_to_wrm(hw) ((struct csio_wrm *)(&(hw)->wrm))
|
|
#define csio_hw_to_mbm(hw) ((struct csio_mbm *)(&(hw)->mbm))
|
|
#define csio_hw_to_scsim(hw) ((struct csio_scsim *)(&(hw)->scsim))
|
|
#define csio_hw_to_mgmtm(hw) ((struct csio_mgmtm *)(&(hw)->mgmtm))
|
|
|
|
#define CSIO_PCI_BUS(hw) ((hw)->pdev->bus->number)
|
|
#define CSIO_PCI_DEV(hw) (PCI_SLOT((hw)->pdev->devfn))
|
|
#define CSIO_PCI_FUNC(hw) (PCI_FUNC((hw)->pdev->devfn))
|
|
|
|
#define csio_set_fwevt_intr_idx(_h, _i) ((_h)->fwevt_intr_idx = (_i))
|
|
#define csio_get_fwevt_intr_idx(_h) ((_h)->fwevt_intr_idx)
|
|
#define csio_set_nondata_intr_idx(_h, _i) ((_h)->nondata_intr_idx = (_i))
|
|
#define csio_get_nondata_intr_idx(_h) ((_h)->nondata_intr_idx)
|
|
|
|
/* Printing/logging */
|
|
#define CSIO_DEVID(__dev) ((__dev)->dev_num)
|
|
#define CSIO_DEVID_LO(__dev) (CSIO_DEVID((__dev)) & 0xFFFF)
|
|
#define CSIO_DEVID_HI(__dev) ((CSIO_DEVID((__dev)) >> 16) & 0xFFFF)
|
|
|
|
#define csio_info(__hw, __fmt, ...) \
|
|
dev_info(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
|
|
|
|
#define csio_fatal(__hw, __fmt, ...) \
|
|
dev_crit(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
|
|
|
|
#define csio_err(__hw, __fmt, ...) \
|
|
dev_err(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
|
|
|
|
#define csio_warn(__hw, __fmt, ...) \
|
|
dev_warn(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
|
|
|
|
#ifdef __CSIO_DEBUG__
|
|
#define csio_dbg(__hw, __fmt, ...) \
|
|
csio_info((__hw), __fmt, ##__VA_ARGS__);
|
|
#else
|
|
#define csio_dbg(__hw, __fmt, ...)
|
|
#endif
|
|
|
|
int csio_hw_wait_op_done_val(struct csio_hw *, int, uint32_t, int,
|
|
int, int, uint32_t *);
|
|
void csio_hw_tp_wr_bits_indirect(struct csio_hw *, unsigned int,
|
|
unsigned int, unsigned int);
|
|
int csio_mgmt_req_lookup(struct csio_mgmtm *, struct csio_ioreq *);
|
|
void csio_hw_intr_disable(struct csio_hw *);
|
|
int csio_hw_slow_intr_handler(struct csio_hw *);
|
|
int csio_handle_intr_status(struct csio_hw *, unsigned int,
|
|
const struct intr_info *);
|
|
|
|
int csio_hw_start(struct csio_hw *);
|
|
int csio_hw_stop(struct csio_hw *);
|
|
int csio_hw_reset(struct csio_hw *);
|
|
int csio_is_hw_ready(struct csio_hw *);
|
|
int csio_is_hw_removing(struct csio_hw *);
|
|
|
|
int csio_fwevtq_handler(struct csio_hw *);
|
|
void csio_evtq_worker(struct work_struct *);
|
|
int csio_enqueue_evt(struct csio_hw *, enum csio_evt, void *, uint16_t);
|
|
void csio_evtq_flush(struct csio_hw *hw);
|
|
|
|
int csio_request_irqs(struct csio_hw *);
|
|
void csio_intr_enable(struct csio_hw *);
|
|
void csio_intr_disable(struct csio_hw *, bool);
|
|
void csio_hw_fatal_err(struct csio_hw *);
|
|
|
|
struct csio_lnode *csio_lnode_alloc(struct csio_hw *);
|
|
int csio_config_queues(struct csio_hw *);
|
|
|
|
int csio_hw_init(struct csio_hw *);
|
|
void csio_hw_exit(struct csio_hw *);
|
|
#endif /* ifndef __CSIO_HW_H__ */
|