259 lines
7.2 KiB
C
259 lines
7.2 KiB
C
/*
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* Driver for (BCM4706)? GBit MAC core on BCMA bus.
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*
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* Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/bcma/bcma.h>
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#include <linux/brcmphy.h>
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#include "bgmac.h"
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static bool bcma_mdio_wait_value(struct bcma_device *core, u16 reg, u32 mask,
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u32 value, int timeout)
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{
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u32 val;
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int i;
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for (i = 0; i < timeout / 10; i++) {
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val = bcma_read32(core, reg);
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if ((val & mask) == value)
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return true;
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udelay(10);
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}
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dev_err(&core->dev, "Timeout waiting for reg 0x%X\n", reg);
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return false;
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}
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/**************************************************
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* PHY ops
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**************************************************/
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static u16 bcma_mdio_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
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{
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struct bcma_device *core;
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u16 phy_access_addr;
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u16 phy_ctl_addr;
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u32 tmp;
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BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
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BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
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BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
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BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
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BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
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BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
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BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
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BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
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BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
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BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
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BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
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if (bgmac->bcma.core->id.id == BCMA_CORE_4706_MAC_GBIT) {
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core = bgmac->bcma.core->bus->drv_gmac_cmn.core;
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phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
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phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
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} else {
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core = bgmac->bcma.core;
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phy_access_addr = BGMAC_PHY_ACCESS;
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phy_ctl_addr = BGMAC_PHY_CNTL;
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}
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tmp = bcma_read32(core, phy_ctl_addr);
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tmp &= ~BGMAC_PC_EPA_MASK;
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tmp |= phyaddr;
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bcma_write32(core, phy_ctl_addr, tmp);
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tmp = BGMAC_PA_START;
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tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
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tmp |= reg << BGMAC_PA_REG_SHIFT;
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bcma_write32(core, phy_access_addr, tmp);
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if (!bcma_mdio_wait_value(core, phy_access_addr, BGMAC_PA_START, 0,
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1000)) {
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dev_err(&core->dev, "Reading PHY %d register 0x%X failed\n",
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phyaddr, reg);
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return 0xffff;
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}
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return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
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}
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/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
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static int bcma_mdio_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg,
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u16 value)
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{
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struct bcma_device *core;
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u16 phy_access_addr;
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u16 phy_ctl_addr;
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u32 tmp;
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if (bgmac->bcma.core->id.id == BCMA_CORE_4706_MAC_GBIT) {
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core = bgmac->bcma.core->bus->drv_gmac_cmn.core;
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phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
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phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
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} else {
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core = bgmac->bcma.core;
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phy_access_addr = BGMAC_PHY_ACCESS;
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phy_ctl_addr = BGMAC_PHY_CNTL;
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}
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tmp = bcma_read32(core, phy_ctl_addr);
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tmp &= ~BGMAC_PC_EPA_MASK;
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tmp |= phyaddr;
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bcma_write32(core, phy_ctl_addr, tmp);
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bcma_write32(bgmac->bcma.core, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
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if (bcma_read32(bgmac->bcma.core, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
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dev_warn(&core->dev, "Error setting MDIO int\n");
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tmp = BGMAC_PA_START;
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tmp |= BGMAC_PA_WRITE;
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tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
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tmp |= reg << BGMAC_PA_REG_SHIFT;
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tmp |= value;
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bcma_write32(core, phy_access_addr, tmp);
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if (!bcma_mdio_wait_value(core, phy_access_addr, BGMAC_PA_START, 0,
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1000)) {
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dev_err(&core->dev, "Writing to PHY %d register 0x%X failed\n",
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phyaddr, reg);
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return -ETIMEDOUT;
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}
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return 0;
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}
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/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
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static void bcma_mdio_phy_init(struct bgmac *bgmac)
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{
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struct bcma_chipinfo *ci = &bgmac->bcma.core->bus->chipinfo;
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u8 i;
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/* For some legacy hardware we do chipset-based PHY initialization here
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* without even detecting PHY ID. It's hacky and should be cleaned as
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* soon as someone can test it.
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*/
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if (ci->id == BCMA_CHIP_ID_BCM5356) {
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for (i = 0; i < 5; i++) {
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bcma_mdio_phy_write(bgmac, i, 0x1f, 0x008b);
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bcma_mdio_phy_write(bgmac, i, 0x15, 0x0100);
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bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000f);
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bcma_mdio_phy_write(bgmac, i, 0x12, 0x2aaa);
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bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000b);
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}
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return;
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}
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if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
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(ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
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(ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
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struct bcma_drv_cc *cc = &bgmac->bcma.core->bus->drv_cc;
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bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
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bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
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for (i = 0; i < 5; i++) {
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bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000f);
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bcma_mdio_phy_write(bgmac, i, 0x16, 0x5284);
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bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000b);
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bcma_mdio_phy_write(bgmac, i, 0x17, 0x0010);
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bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000f);
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bcma_mdio_phy_write(bgmac, i, 0x16, 0x5296);
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bcma_mdio_phy_write(bgmac, i, 0x17, 0x1073);
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bcma_mdio_phy_write(bgmac, i, 0x17, 0x9073);
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bcma_mdio_phy_write(bgmac, i, 0x16, 0x52b6);
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bcma_mdio_phy_write(bgmac, i, 0x17, 0x9273);
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bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000b);
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}
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return;
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}
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/* For all other hw do initialization using PHY subsystem. */
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if (bgmac->net_dev && bgmac->net_dev->phydev)
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phy_init_hw(bgmac->net_dev->phydev);
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}
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/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
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static int bcma_mdio_phy_reset(struct mii_bus *bus)
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{
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struct bgmac *bgmac = bus->priv;
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u8 phyaddr = bgmac->phyaddr;
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if (phyaddr == BGMAC_PHY_NOREGS)
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return 0;
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bcma_mdio_phy_write(bgmac, phyaddr, MII_BMCR, BMCR_RESET);
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udelay(100);
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if (bcma_mdio_phy_read(bgmac, phyaddr, MII_BMCR) & BMCR_RESET)
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dev_err(bgmac->dev, "PHY reset failed\n");
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bcma_mdio_phy_init(bgmac);
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return 0;
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}
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/**************************************************
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* MII
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**************************************************/
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static int bcma_mdio_mii_read(struct mii_bus *bus, int mii_id, int regnum)
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{
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return bcma_mdio_phy_read(bus->priv, mii_id, regnum);
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}
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static int bcma_mdio_mii_write(struct mii_bus *bus, int mii_id, int regnum,
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u16 value)
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{
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return bcma_mdio_phy_write(bus->priv, mii_id, regnum, value);
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}
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struct mii_bus *bcma_mdio_mii_register(struct bgmac *bgmac)
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{
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struct bcma_device *core = bgmac->bcma.core;
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struct mii_bus *mii_bus;
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int err;
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mii_bus = mdiobus_alloc();
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if (!mii_bus) {
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err = -ENOMEM;
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goto err;
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}
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mii_bus->name = "bcma_mdio mii bus";
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sprintf(mii_bus->id, "%s-%d-%d", "bcma_mdio", core->bus->num,
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core->core_unit);
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mii_bus->priv = bgmac;
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mii_bus->read = bcma_mdio_mii_read;
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mii_bus->write = bcma_mdio_mii_write;
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mii_bus->reset = bcma_mdio_phy_reset;
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mii_bus->parent = &core->dev;
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mii_bus->phy_mask = ~(1 << bgmac->phyaddr);
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err = mdiobus_register(mii_bus);
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if (err) {
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dev_err(&core->dev, "Registration of mii bus failed\n");
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goto err_free_bus;
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}
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return mii_bus;
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err_free_bus:
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mdiobus_free(mii_bus);
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err:
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return ERR_PTR(err);
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}
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EXPORT_SYMBOL_GPL(bcma_mdio_mii_register);
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void bcma_mdio_mii_unregister(struct mii_bus *mii_bus)
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{
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if (!mii_bus)
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return;
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mdiobus_unregister(mii_bus);
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mdiobus_free(mii_bus);
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}
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EXPORT_SYMBOL_GPL(bcma_mdio_mii_unregister);
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MODULE_AUTHOR("Rafał Miłecki");
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MODULE_LICENSE("GPL");
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