1190 lines
30 KiB
C
1190 lines
30 KiB
C
/*
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* Freescale QuadSPI driver.
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*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/errno.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/timer.h>
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#include <linux/jiffies.h>
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#include <linux/completion.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/spi-nor.h>
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#include <linux/mutex.h>
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#include <linux/pm_qos.h>
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#include <linux/sizes.h>
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/* Controller needs driver to swap endian */
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#define QUADSPI_QUIRK_SWAP_ENDIAN (1 << 0)
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/* Controller needs 4x internal clock */
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#define QUADSPI_QUIRK_4X_INT_CLK (1 << 1)
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/*
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* TKT253890, Controller needs driver to fill txfifo till 16 byte to
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* trigger data transfer even though extern data will not transferred.
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*/
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#define QUADSPI_QUIRK_TKT253890 (1 << 2)
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/* Controller cannot wake up from wait mode, TKT245618 */
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#define QUADSPI_QUIRK_TKT245618 (1 << 3)
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/* The registers */
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#define QUADSPI_MCR 0x00
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#define QUADSPI_MCR_RESERVED_SHIFT 16
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#define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
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#define QUADSPI_MCR_MDIS_SHIFT 14
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#define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
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#define QUADSPI_MCR_CLR_TXF_SHIFT 11
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#define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
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#define QUADSPI_MCR_CLR_RXF_SHIFT 10
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#define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
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#define QUADSPI_MCR_DDR_EN_SHIFT 7
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#define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
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#define QUADSPI_MCR_END_CFG_SHIFT 2
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#define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
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#define QUADSPI_MCR_SWRSTHD_SHIFT 1
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#define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
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#define QUADSPI_MCR_SWRSTSD_SHIFT 0
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#define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
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#define QUADSPI_IPCR 0x08
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#define QUADSPI_IPCR_SEQID_SHIFT 24
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#define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
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#define QUADSPI_BUF0CR 0x10
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#define QUADSPI_BUF1CR 0x14
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#define QUADSPI_BUF2CR 0x18
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#define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
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#define QUADSPI_BUF3CR 0x1c
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#define QUADSPI_BUF3CR_ALLMST_SHIFT 31
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#define QUADSPI_BUF3CR_ALLMST_MASK (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
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#define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
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#define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
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#define QUADSPI_BFGENCR 0x20
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#define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
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#define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
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#define QUADSPI_BFGENCR_SEQID_SHIFT 12
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#define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
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#define QUADSPI_BUF0IND 0x30
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#define QUADSPI_BUF1IND 0x34
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#define QUADSPI_BUF2IND 0x38
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#define QUADSPI_SFAR 0x100
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#define QUADSPI_SMPR 0x108
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#define QUADSPI_SMPR_DDRSMP_SHIFT 16
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#define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
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#define QUADSPI_SMPR_FSDLY_SHIFT 6
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#define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
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#define QUADSPI_SMPR_FSPHS_SHIFT 5
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#define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
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#define QUADSPI_SMPR_HSENA_SHIFT 0
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#define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
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#define QUADSPI_RBSR 0x10c
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#define QUADSPI_RBSR_RDBFL_SHIFT 8
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#define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
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#define QUADSPI_RBCT 0x110
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#define QUADSPI_RBCT_WMRK_MASK 0x1F
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#define QUADSPI_RBCT_RXBRD_SHIFT 8
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#define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
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#define QUADSPI_TBSR 0x150
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#define QUADSPI_TBDR 0x154
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#define QUADSPI_SR 0x15c
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#define QUADSPI_SR_IP_ACC_SHIFT 1
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#define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
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#define QUADSPI_SR_AHB_ACC_SHIFT 2
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#define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
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#define QUADSPI_FR 0x160
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#define QUADSPI_FR_TFF_MASK 0x1
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#define QUADSPI_SFA1AD 0x180
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#define QUADSPI_SFA2AD 0x184
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#define QUADSPI_SFB1AD 0x188
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#define QUADSPI_SFB2AD 0x18c
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#define QUADSPI_RBDR 0x200
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#define QUADSPI_LUTKEY 0x300
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#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
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#define QUADSPI_LCKCR 0x304
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#define QUADSPI_LCKER_LOCK 0x1
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#define QUADSPI_LCKER_UNLOCK 0x2
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#define QUADSPI_RSER 0x164
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#define QUADSPI_RSER_TFIE (0x1 << 0)
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#define QUADSPI_LUT_BASE 0x310
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/*
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* The definition of the LUT register shows below:
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*
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* ---------------------------------------------------
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* | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
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* ---------------------------------------------------
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*/
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#define OPRND0_SHIFT 0
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#define PAD0_SHIFT 8
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#define INSTR0_SHIFT 10
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#define OPRND1_SHIFT 16
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/* Instruction set for the LUT register. */
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#define LUT_STOP 0
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#define LUT_CMD 1
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#define LUT_ADDR 2
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#define LUT_DUMMY 3
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#define LUT_MODE 4
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#define LUT_MODE2 5
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#define LUT_MODE4 6
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#define LUT_FSL_READ 7
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#define LUT_FSL_WRITE 8
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#define LUT_JMP_ON_CS 9
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#define LUT_ADDR_DDR 10
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#define LUT_MODE_DDR 11
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#define LUT_MODE2_DDR 12
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#define LUT_MODE4_DDR 13
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#define LUT_FSL_READ_DDR 14
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#define LUT_FSL_WRITE_DDR 15
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#define LUT_DATA_LEARN 16
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/*
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* The PAD definitions for LUT register.
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*
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* The pad stands for the lines number of IO[0:3].
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* For example, the Quad read need four IO lines, so you should
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* set LUT_PAD4 which means we use four IO lines.
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*/
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#define LUT_PAD1 0
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#define LUT_PAD2 1
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#define LUT_PAD4 2
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/* Oprands for the LUT register. */
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#define ADDR24BIT 0x18
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#define ADDR32BIT 0x20
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/* Macros for constructing the LUT register. */
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#define LUT0(ins, pad, opr) \
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(((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
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((LUT_##ins) << INSTR0_SHIFT))
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#define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
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/* other macros for LUT register. */
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#define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
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#define QUADSPI_LUT_NUM 64
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/* SEQID -- we can have 16 seqids at most. */
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#define SEQID_READ 0
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#define SEQID_WREN 1
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#define SEQID_WRDI 2
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#define SEQID_RDSR 3
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#define SEQID_SE 4
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#define SEQID_CHIP_ERASE 5
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#define SEQID_PP 6
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#define SEQID_RDID 7
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#define SEQID_WRSR 8
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#define SEQID_RDCR 9
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#define SEQID_EN4B 10
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#define SEQID_BRWR 11
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#define QUADSPI_MIN_IOMAP SZ_4M
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enum fsl_qspi_devtype {
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FSL_QUADSPI_VYBRID,
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FSL_QUADSPI_IMX6SX,
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FSL_QUADSPI_IMX7D,
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FSL_QUADSPI_IMX6UL,
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FSL_QUADSPI_LS1021A,
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};
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struct fsl_qspi_devtype_data {
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enum fsl_qspi_devtype devtype;
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int rxfifo;
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int txfifo;
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int ahb_buf_size;
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int driver_data;
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};
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static const struct fsl_qspi_devtype_data vybrid_data = {
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.devtype = FSL_QUADSPI_VYBRID,
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.rxfifo = 128,
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.txfifo = 64,
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.ahb_buf_size = 1024,
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.driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
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};
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static const struct fsl_qspi_devtype_data imx6sx_data = {
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.devtype = FSL_QUADSPI_IMX6SX,
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.rxfifo = 128,
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.txfifo = 512,
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.ahb_buf_size = 1024,
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.driver_data = QUADSPI_QUIRK_4X_INT_CLK
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| QUADSPI_QUIRK_TKT245618,
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};
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static const struct fsl_qspi_devtype_data imx7d_data = {
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.devtype = FSL_QUADSPI_IMX7D,
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.rxfifo = 512,
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.txfifo = 512,
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.ahb_buf_size = 1024,
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.driver_data = QUADSPI_QUIRK_TKT253890
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| QUADSPI_QUIRK_4X_INT_CLK,
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};
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static const struct fsl_qspi_devtype_data imx6ul_data = {
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.devtype = FSL_QUADSPI_IMX6UL,
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.rxfifo = 128,
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.txfifo = 512,
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.ahb_buf_size = 1024,
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.driver_data = QUADSPI_QUIRK_TKT253890
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| QUADSPI_QUIRK_4X_INT_CLK,
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};
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static struct fsl_qspi_devtype_data ls1021a_data = {
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.devtype = FSL_QUADSPI_LS1021A,
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.rxfifo = 128,
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.txfifo = 64,
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.ahb_buf_size = 1024,
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.driver_data = 0,
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};
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#define FSL_QSPI_MAX_CHIP 4
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struct fsl_qspi {
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struct spi_nor nor[FSL_QSPI_MAX_CHIP];
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void __iomem *iobase;
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void __iomem *ahb_addr;
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u32 memmap_phy;
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u32 memmap_offs;
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u32 memmap_len;
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struct clk *clk, *clk_en;
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struct device *dev;
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struct completion c;
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const struct fsl_qspi_devtype_data *devtype_data;
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u32 nor_size;
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u32 nor_num;
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u32 clk_rate;
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unsigned int chip_base_addr; /* We may support two chips. */
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bool has_second_chip;
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bool big_endian;
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struct mutex lock;
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struct pm_qos_request pm_qos_req;
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};
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static inline int needs_swap_endian(struct fsl_qspi *q)
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{
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return q->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN;
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}
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static inline int needs_4x_clock(struct fsl_qspi *q)
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{
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return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
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}
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static inline int needs_fill_txfifo(struct fsl_qspi *q)
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{
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return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
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}
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static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
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{
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return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
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}
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/*
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* R/W functions for big- or little-endian registers:
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* The qSPI controller's endian is independent of the CPU core's endian.
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* So far, although the CPU core is little-endian but the qSPI have two
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* versions for big-endian and little-endian.
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*/
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static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
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{
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if (q->big_endian)
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iowrite32be(val, addr);
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else
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iowrite32(val, addr);
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}
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static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
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{
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if (q->big_endian)
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return ioread32be(addr);
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else
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return ioread32(addr);
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}
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/*
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* An IC bug makes us to re-arrange the 32-bit data.
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* The following chips, such as IMX6SLX, have fixed this bug.
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*/
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static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
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{
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return needs_swap_endian(q) ? __swab32(a) : a;
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}
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static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
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{
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qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
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qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
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}
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static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
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{
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qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
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qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
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}
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static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
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{
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struct fsl_qspi *q = dev_id;
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u32 reg;
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/* clear interrupt */
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reg = qspi_readl(q, q->iobase + QUADSPI_FR);
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qspi_writel(q, reg, q->iobase + QUADSPI_FR);
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if (reg & QUADSPI_FR_TFF_MASK)
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complete(&q->c);
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dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
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return IRQ_HANDLED;
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}
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static void fsl_qspi_init_lut(struct fsl_qspi *q)
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{
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void __iomem *base = q->iobase;
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int rxfifo = q->devtype_data->rxfifo;
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u32 lut_base;
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int i;
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struct spi_nor *nor = &q->nor[0];
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u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
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u8 read_op = nor->read_opcode;
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u8 read_dm = nor->read_dummy;
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fsl_qspi_unlock_lut(q);
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/* Clear all the LUT table */
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for (i = 0; i < QUADSPI_LUT_NUM; i++)
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qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
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/* Read */
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lut_base = SEQID_READ * 4;
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qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
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base + QUADSPI_LUT(lut_base));
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qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
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LUT1(FSL_READ, PAD4, rxfifo),
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base + QUADSPI_LUT(lut_base + 1));
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/* Write enable */
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lut_base = SEQID_WREN * 4;
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qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
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base + QUADSPI_LUT(lut_base));
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/* Page Program */
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lut_base = SEQID_PP * 4;
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qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
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LUT1(ADDR, PAD1, addrlen),
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base + QUADSPI_LUT(lut_base));
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qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
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base + QUADSPI_LUT(lut_base + 1));
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/* Read Status */
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lut_base = SEQID_RDSR * 4;
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qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
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LUT1(FSL_READ, PAD1, 0x1),
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base + QUADSPI_LUT(lut_base));
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/* Erase a sector */
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lut_base = SEQID_SE * 4;
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qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
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LUT1(ADDR, PAD1, addrlen),
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base + QUADSPI_LUT(lut_base));
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/* Erase the whole chip */
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lut_base = SEQID_CHIP_ERASE * 4;
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qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
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base + QUADSPI_LUT(lut_base));
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/* READ ID */
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lut_base = SEQID_RDID * 4;
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qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) |
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LUT1(FSL_READ, PAD1, 0x8),
|
|
base + QUADSPI_LUT(lut_base));
|
|
|
|
/* Write Register */
|
|
lut_base = SEQID_WRSR * 4;
|
|
qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) |
|
|
LUT1(FSL_WRITE, PAD1, 0x2),
|
|
base + QUADSPI_LUT(lut_base));
|
|
|
|
/* Read Configuration Register */
|
|
lut_base = SEQID_RDCR * 4;
|
|
qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) |
|
|
LUT1(FSL_READ, PAD1, 0x1),
|
|
base + QUADSPI_LUT(lut_base));
|
|
|
|
/* Write disable */
|
|
lut_base = SEQID_WRDI * 4;
|
|
qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
|
|
base + QUADSPI_LUT(lut_base));
|
|
|
|
/* Enter 4 Byte Mode (Micron) */
|
|
lut_base = SEQID_EN4B * 4;
|
|
qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
|
|
base + QUADSPI_LUT(lut_base));
|
|
|
|
/* Enter 4 Byte Mode (Spansion) */
|
|
lut_base = SEQID_BRWR * 4;
|
|
qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
|
|
base + QUADSPI_LUT(lut_base));
|
|
|
|
fsl_qspi_lock_lut(q);
|
|
}
|
|
|
|
/* Get the SEQID for the command */
|
|
static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
|
|
{
|
|
switch (cmd) {
|
|
case SPINOR_OP_READ_1_1_4:
|
|
return SEQID_READ;
|
|
case SPINOR_OP_WREN:
|
|
return SEQID_WREN;
|
|
case SPINOR_OP_WRDI:
|
|
return SEQID_WRDI;
|
|
case SPINOR_OP_RDSR:
|
|
return SEQID_RDSR;
|
|
case SPINOR_OP_SE:
|
|
return SEQID_SE;
|
|
case SPINOR_OP_CHIP_ERASE:
|
|
return SEQID_CHIP_ERASE;
|
|
case SPINOR_OP_PP:
|
|
return SEQID_PP;
|
|
case SPINOR_OP_RDID:
|
|
return SEQID_RDID;
|
|
case SPINOR_OP_WRSR:
|
|
return SEQID_WRSR;
|
|
case SPINOR_OP_RDCR:
|
|
return SEQID_RDCR;
|
|
case SPINOR_OP_EN4B:
|
|
return SEQID_EN4B;
|
|
case SPINOR_OP_BRWR:
|
|
return SEQID_BRWR;
|
|
default:
|
|
if (cmd == q->nor[0].erase_opcode)
|
|
return SEQID_SE;
|
|
dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
|
|
break;
|
|
}
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int
|
|
fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
|
|
{
|
|
void __iomem *base = q->iobase;
|
|
int seqid;
|
|
u32 reg, reg2;
|
|
int err;
|
|
|
|
init_completion(&q->c);
|
|
dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
|
|
q->chip_base_addr, addr, len, cmd);
|
|
|
|
/* save the reg */
|
|
reg = qspi_readl(q, base + QUADSPI_MCR);
|
|
|
|
qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
|
|
base + QUADSPI_SFAR);
|
|
qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
|
|
base + QUADSPI_RBCT);
|
|
qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
|
|
|
|
do {
|
|
reg2 = qspi_readl(q, base + QUADSPI_SR);
|
|
if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
|
|
udelay(1);
|
|
dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
|
|
continue;
|
|
}
|
|
break;
|
|
} while (1);
|
|
|
|
/* trigger the LUT now */
|
|
seqid = fsl_qspi_get_seqid(q, cmd);
|
|
qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
|
|
base + QUADSPI_IPCR);
|
|
|
|
/* Wait for the interrupt. */
|
|
if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
|
|
dev_err(q->dev,
|
|
"cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
|
|
cmd, addr, qspi_readl(q, base + QUADSPI_FR),
|
|
qspi_readl(q, base + QUADSPI_SR));
|
|
err = -ETIMEDOUT;
|
|
} else {
|
|
err = 0;
|
|
}
|
|
|
|
/* restore the MCR */
|
|
qspi_writel(q, reg, base + QUADSPI_MCR);
|
|
|
|
return err;
|
|
}
|
|
|
|
/* Read out the data from the QUADSPI_RBDR buffer registers. */
|
|
static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
|
|
{
|
|
u32 tmp;
|
|
int i = 0;
|
|
|
|
while (len > 0) {
|
|
tmp = qspi_readl(q, q->iobase + QUADSPI_RBDR + i * 4);
|
|
tmp = fsl_qspi_endian_xchg(q, tmp);
|
|
dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
|
|
q->chip_base_addr, tmp);
|
|
|
|
if (len >= 4) {
|
|
*((u32 *)rxbuf) = tmp;
|
|
rxbuf += 4;
|
|
} else {
|
|
memcpy(rxbuf, &tmp, len);
|
|
break;
|
|
}
|
|
|
|
len -= 4;
|
|
i++;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* If we have changed the content of the flash by writing or erasing,
|
|
* we need to invalidate the AHB buffer. If we do not do so, we may read out
|
|
* the wrong data. The spec tells us reset the AHB domain and Serial Flash
|
|
* domain at the same time.
|
|
*/
|
|
static inline void fsl_qspi_invalid(struct fsl_qspi *q)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
|
|
reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
|
|
qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
|
|
|
|
/*
|
|
* The minimum delay : 1 AHB + 2 SFCK clocks.
|
|
* Delay 1 us is enough.
|
|
*/
|
|
udelay(1);
|
|
|
|
reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
|
|
qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
|
|
}
|
|
|
|
static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
|
|
u8 opcode, unsigned int to, u32 *txbuf,
|
|
unsigned count)
|
|
{
|
|
int ret, i, j;
|
|
u32 tmp;
|
|
|
|
dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
|
|
q->chip_base_addr, to, count);
|
|
|
|
/* clear the TX FIFO. */
|
|
tmp = qspi_readl(q, q->iobase + QUADSPI_MCR);
|
|
qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
|
|
|
|
/* fill the TX data to the FIFO */
|
|
for (j = 0, i = ((count + 3) / 4); j < i; j++) {
|
|
tmp = fsl_qspi_endian_xchg(q, *txbuf);
|
|
qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
|
|
txbuf++;
|
|
}
|
|
|
|
/* fill the TXFIFO upto 16 bytes for i.MX7d */
|
|
if (needs_fill_txfifo(q))
|
|
for (; i < 4; i++)
|
|
qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
|
|
|
|
/* Trigger it */
|
|
ret = fsl_qspi_runcmd(q, opcode, to, count);
|
|
|
|
if (ret == 0)
|
|
return count;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
|
|
{
|
|
int nor_size = q->nor_size;
|
|
void __iomem *base = q->iobase;
|
|
|
|
qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
|
|
qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
|
|
qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
|
|
qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
|
|
}
|
|
|
|
/*
|
|
* There are two different ways to read out the data from the flash:
|
|
* the "IP Command Read" and the "AHB Command Read".
|
|
*
|
|
* The IC guy suggests we use the "AHB Command Read" which is faster
|
|
* then the "IP Command Read". (What's more is that there is a bug in
|
|
* the "IP Command Read" in the Vybrid.)
|
|
*
|
|
* After we set up the registers for the "AHB Command Read", we can use
|
|
* the memcpy to read the data directly. A "missed" access to the buffer
|
|
* causes the controller to clear the buffer, and use the sequence pointed
|
|
* by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
|
|
*/
|
|
static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
|
|
{
|
|
void __iomem *base = q->iobase;
|
|
int seqid;
|
|
|
|
/* AHB configuration for access buffer 0/1/2 .*/
|
|
qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
|
|
qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
|
|
qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
|
|
/*
|
|
* Set ADATSZ with the maximum AHB buffer size to improve the
|
|
* read performance.
|
|
*/
|
|
qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
|
|
((q->devtype_data->ahb_buf_size / 8)
|
|
<< QUADSPI_BUF3CR_ADATSZ_SHIFT),
|
|
base + QUADSPI_BUF3CR);
|
|
|
|
/* We only use the buffer3 */
|
|
qspi_writel(q, 0, base + QUADSPI_BUF0IND);
|
|
qspi_writel(q, 0, base + QUADSPI_BUF1IND);
|
|
qspi_writel(q, 0, base + QUADSPI_BUF2IND);
|
|
|
|
/* Set the default lut sequence for AHB Read. */
|
|
seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
|
|
qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
|
|
q->iobase + QUADSPI_BFGENCR);
|
|
}
|
|
|
|
/* This function was used to prepare and enable QSPI clock */
|
|
static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
|
|
{
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(q->clk_en);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = clk_prepare_enable(q->clk);
|
|
if (ret) {
|
|
clk_disable_unprepare(q->clk_en);
|
|
return ret;
|
|
}
|
|
|
|
if (needs_wakeup_wait_mode(q))
|
|
pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* This function was used to disable and unprepare QSPI clock */
|
|
static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
|
|
{
|
|
if (needs_wakeup_wait_mode(q))
|
|
pm_qos_remove_request(&q->pm_qos_req);
|
|
|
|
clk_disable_unprepare(q->clk);
|
|
clk_disable_unprepare(q->clk_en);
|
|
|
|
}
|
|
|
|
/* We use this function to do some basic init for spi_nor_scan(). */
|
|
static int fsl_qspi_nor_setup(struct fsl_qspi *q)
|
|
{
|
|
void __iomem *base = q->iobase;
|
|
u32 reg;
|
|
int ret;
|
|
|
|
/* disable and unprepare clock to avoid glitch pass to controller */
|
|
fsl_qspi_clk_disable_unprep(q);
|
|
|
|
/* the default frequency, we will change it in the future. */
|
|
ret = clk_set_rate(q->clk, 66000000);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = fsl_qspi_clk_prep_enable(q);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Reset the module */
|
|
qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
|
|
base + QUADSPI_MCR);
|
|
udelay(1);
|
|
|
|
/* Init the LUT table. */
|
|
fsl_qspi_init_lut(q);
|
|
|
|
/* Disable the module */
|
|
qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
|
|
base + QUADSPI_MCR);
|
|
|
|
reg = qspi_readl(q, base + QUADSPI_SMPR);
|
|
qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
|
|
| QUADSPI_SMPR_FSPHS_MASK
|
|
| QUADSPI_SMPR_HSENA_MASK
|
|
| QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
|
|
|
|
/* Enable the module */
|
|
qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
|
|
base + QUADSPI_MCR);
|
|
|
|
/* clear all interrupt status */
|
|
qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
|
|
|
|
/* enable the interrupt */
|
|
qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
|
|
{
|
|
unsigned long rate = q->clk_rate;
|
|
int ret;
|
|
|
|
if (needs_4x_clock(q))
|
|
rate *= 4;
|
|
|
|
/* disable and unprepare clock to avoid glitch pass to controller */
|
|
fsl_qspi_clk_disable_unprep(q);
|
|
|
|
ret = clk_set_rate(q->clk, rate);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = fsl_qspi_clk_prep_enable(q);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Init the LUT table again. */
|
|
fsl_qspi_init_lut(q);
|
|
|
|
/* Init for AHB read */
|
|
fsl_qspi_init_abh_read(q);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id fsl_qspi_dt_ids[] = {
|
|
{ .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
|
|
{ .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
|
|
{ .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
|
|
{ .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
|
|
{ .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
|
|
|
|
static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
|
|
{
|
|
q->chip_base_addr = q->nor_size * (nor - q->nor);
|
|
}
|
|
|
|
static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
|
|
{
|
|
int ret;
|
|
struct fsl_qspi *q = nor->priv;
|
|
|
|
ret = fsl_qspi_runcmd(q, opcode, 0, len);
|
|
if (ret)
|
|
return ret;
|
|
|
|
fsl_qspi_read_data(q, len, buf);
|
|
return 0;
|
|
}
|
|
|
|
static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
|
|
{
|
|
struct fsl_qspi *q = nor->priv;
|
|
int ret;
|
|
|
|
if (!buf) {
|
|
ret = fsl_qspi_runcmd(q, opcode, 0, 1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (opcode == SPINOR_OP_CHIP_ERASE)
|
|
fsl_qspi_invalid(q);
|
|
|
|
} else if (len > 0) {
|
|
ret = fsl_qspi_nor_write(q, nor, opcode, 0,
|
|
(u32 *)buf, len);
|
|
if (ret > 0)
|
|
return 0;
|
|
} else {
|
|
dev_err(q->dev, "invalid cmd %d\n", opcode);
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
|
|
size_t len, const u_char *buf)
|
|
{
|
|
struct fsl_qspi *q = nor->priv;
|
|
ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
|
|
(u32 *)buf, len);
|
|
|
|
/* invalid the data in the AHB buffer. */
|
|
fsl_qspi_invalid(q);
|
|
return ret;
|
|
}
|
|
|
|
static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
|
|
size_t len, u_char *buf)
|
|
{
|
|
struct fsl_qspi *q = nor->priv;
|
|
u8 cmd = nor->read_opcode;
|
|
|
|
/* if necessary,ioremap buffer before AHB read, */
|
|
if (!q->ahb_addr) {
|
|
q->memmap_offs = q->chip_base_addr + from;
|
|
q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
|
|
|
|
q->ahb_addr = ioremap_nocache(
|
|
q->memmap_phy + q->memmap_offs,
|
|
q->memmap_len);
|
|
if (!q->ahb_addr) {
|
|
dev_err(q->dev, "ioremap failed\n");
|
|
return -ENOMEM;
|
|
}
|
|
/* ioremap if the data requested is out of range */
|
|
} else if (q->chip_base_addr + from < q->memmap_offs
|
|
|| q->chip_base_addr + from + len >
|
|
q->memmap_offs + q->memmap_len) {
|
|
iounmap(q->ahb_addr);
|
|
|
|
q->memmap_offs = q->chip_base_addr + from;
|
|
q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
|
|
q->ahb_addr = ioremap_nocache(
|
|
q->memmap_phy + q->memmap_offs,
|
|
q->memmap_len);
|
|
if (!q->ahb_addr) {
|
|
dev_err(q->dev, "ioremap failed\n");
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
dev_dbg(q->dev, "cmd [%x],read from %p, len:%zd\n",
|
|
cmd, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
|
|
len);
|
|
|
|
/* Read out the data directly from the AHB buffer.*/
|
|
memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
|
|
len);
|
|
|
|
return len;
|
|
}
|
|
|
|
static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
|
|
{
|
|
struct fsl_qspi *q = nor->priv;
|
|
int ret;
|
|
|
|
dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
|
|
nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs);
|
|
|
|
ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
fsl_qspi_invalid(q);
|
|
return 0;
|
|
}
|
|
|
|
static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
|
|
{
|
|
struct fsl_qspi *q = nor->priv;
|
|
int ret;
|
|
|
|
mutex_lock(&q->lock);
|
|
|
|
ret = fsl_qspi_clk_prep_enable(q);
|
|
if (ret)
|
|
goto err_mutex;
|
|
|
|
fsl_qspi_set_base_addr(q, nor);
|
|
return 0;
|
|
|
|
err_mutex:
|
|
mutex_unlock(&q->lock);
|
|
return ret;
|
|
}
|
|
|
|
static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
|
|
{
|
|
struct fsl_qspi *q = nor->priv;
|
|
|
|
fsl_qspi_clk_disable_unprep(q);
|
|
mutex_unlock(&q->lock);
|
|
}
|
|
|
|
static int fsl_qspi_probe(struct platform_device *pdev)
|
|
{
|
|
const struct spi_nor_hwcaps hwcaps = {
|
|
.mask = SNOR_HWCAPS_READ_1_1_4 |
|
|
SNOR_HWCAPS_PP,
|
|
};
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct device *dev = &pdev->dev;
|
|
struct fsl_qspi *q;
|
|
struct resource *res;
|
|
struct spi_nor *nor;
|
|
struct mtd_info *mtd;
|
|
int ret, i = 0;
|
|
|
|
q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
|
|
if (!q)
|
|
return -ENOMEM;
|
|
|
|
q->nor_num = of_get_child_count(dev->of_node);
|
|
if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
|
|
return -ENODEV;
|
|
|
|
q->dev = dev;
|
|
q->devtype_data = of_device_get_match_data(dev);
|
|
if (!q->devtype_data)
|
|
return -ENODEV;
|
|
platform_set_drvdata(pdev, q);
|
|
|
|
/* find the resources */
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
|
|
q->iobase = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(q->iobase))
|
|
return PTR_ERR(q->iobase);
|
|
|
|
q->big_endian = of_property_read_bool(np, "big-endian");
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
|
"QuadSPI-memory");
|
|
if (!devm_request_mem_region(dev, res->start, resource_size(res),
|
|
res->name)) {
|
|
dev_err(dev, "can't request region for resource %pR\n", res);
|
|
return -EBUSY;
|
|
}
|
|
|
|
q->memmap_phy = res->start;
|
|
|
|
/* find the clocks */
|
|
q->clk_en = devm_clk_get(dev, "qspi_en");
|
|
if (IS_ERR(q->clk_en))
|
|
return PTR_ERR(q->clk_en);
|
|
|
|
q->clk = devm_clk_get(dev, "qspi");
|
|
if (IS_ERR(q->clk))
|
|
return PTR_ERR(q->clk);
|
|
|
|
ret = fsl_qspi_clk_prep_enable(q);
|
|
if (ret) {
|
|
dev_err(dev, "can not enable the clock\n");
|
|
goto clk_failed;
|
|
}
|
|
|
|
/* find the irq */
|
|
ret = platform_get_irq(pdev, 0);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to get the irq: %d\n", ret);
|
|
goto irq_failed;
|
|
}
|
|
|
|
ret = devm_request_irq(dev, ret,
|
|
fsl_qspi_irq_handler, 0, pdev->name, q);
|
|
if (ret) {
|
|
dev_err(dev, "failed to request irq: %d\n", ret);
|
|
goto irq_failed;
|
|
}
|
|
|
|
ret = fsl_qspi_nor_setup(q);
|
|
if (ret)
|
|
goto irq_failed;
|
|
|
|
if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
|
|
q->has_second_chip = true;
|
|
|
|
mutex_init(&q->lock);
|
|
|
|
/* iterate the subnodes. */
|
|
for_each_available_child_of_node(dev->of_node, np) {
|
|
/* skip the holes */
|
|
if (!q->has_second_chip)
|
|
i *= 2;
|
|
|
|
nor = &q->nor[i];
|
|
mtd = &nor->mtd;
|
|
|
|
nor->dev = dev;
|
|
spi_nor_set_flash_node(nor, np);
|
|
nor->priv = q;
|
|
|
|
/* fill the hooks */
|
|
nor->read_reg = fsl_qspi_read_reg;
|
|
nor->write_reg = fsl_qspi_write_reg;
|
|
nor->read = fsl_qspi_read;
|
|
nor->write = fsl_qspi_write;
|
|
nor->erase = fsl_qspi_erase;
|
|
|
|
nor->prepare = fsl_qspi_prep;
|
|
nor->unprepare = fsl_qspi_unprep;
|
|
|
|
ret = of_property_read_u32(np, "spi-max-frequency",
|
|
&q->clk_rate);
|
|
if (ret < 0)
|
|
goto mutex_failed;
|
|
|
|
/* set the chip address for READID */
|
|
fsl_qspi_set_base_addr(q, nor);
|
|
|
|
ret = spi_nor_scan(nor, NULL, &hwcaps);
|
|
if (ret)
|
|
goto mutex_failed;
|
|
|
|
ret = mtd_device_register(mtd, NULL, 0);
|
|
if (ret)
|
|
goto mutex_failed;
|
|
|
|
/* Set the correct NOR size now. */
|
|
if (q->nor_size == 0) {
|
|
q->nor_size = mtd->size;
|
|
|
|
/* Map the SPI NOR to accessiable address */
|
|
fsl_qspi_set_map_addr(q);
|
|
}
|
|
|
|
/*
|
|
* The TX FIFO is 64 bytes in the Vybrid, but the Page Program
|
|
* may writes 265 bytes per time. The write is working in the
|
|
* unit of the TX FIFO, not in the unit of the SPI NOR's page
|
|
* size.
|
|
*
|
|
* So shrink the spi_nor->page_size if it is larger then the
|
|
* TX FIFO.
|
|
*/
|
|
if (nor->page_size > q->devtype_data->txfifo)
|
|
nor->page_size = q->devtype_data->txfifo;
|
|
|
|
i++;
|
|
}
|
|
|
|
/* finish the rest init. */
|
|
ret = fsl_qspi_nor_setup_last(q);
|
|
if (ret)
|
|
goto last_init_failed;
|
|
|
|
fsl_qspi_clk_disable_unprep(q);
|
|
return 0;
|
|
|
|
last_init_failed:
|
|
for (i = 0; i < q->nor_num; i++) {
|
|
/* skip the holes */
|
|
if (!q->has_second_chip)
|
|
i *= 2;
|
|
mtd_device_unregister(&q->nor[i].mtd);
|
|
}
|
|
mutex_failed:
|
|
mutex_destroy(&q->lock);
|
|
irq_failed:
|
|
fsl_qspi_clk_disable_unprep(q);
|
|
clk_failed:
|
|
dev_err(dev, "Freescale QuadSPI probe failed\n");
|
|
return ret;
|
|
}
|
|
|
|
static int fsl_qspi_remove(struct platform_device *pdev)
|
|
{
|
|
struct fsl_qspi *q = platform_get_drvdata(pdev);
|
|
int i;
|
|
|
|
for (i = 0; i < q->nor_num; i++) {
|
|
/* skip the holes */
|
|
if (!q->has_second_chip)
|
|
i *= 2;
|
|
mtd_device_unregister(&q->nor[i].mtd);
|
|
}
|
|
|
|
/* disable the hardware */
|
|
qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
|
|
qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
|
|
|
|
mutex_destroy(&q->lock);
|
|
|
|
if (q->ahb_addr)
|
|
iounmap(q->ahb_addr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int fsl_qspi_resume(struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
struct fsl_qspi *q = platform_get_drvdata(pdev);
|
|
|
|
ret = fsl_qspi_clk_prep_enable(q);
|
|
if (ret)
|
|
return ret;
|
|
|
|
fsl_qspi_nor_setup(q);
|
|
fsl_qspi_set_map_addr(q);
|
|
fsl_qspi_nor_setup_last(q);
|
|
|
|
fsl_qspi_clk_disable_unprep(q);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver fsl_qspi_driver = {
|
|
.driver = {
|
|
.name = "fsl-quadspi",
|
|
.bus = &platform_bus_type,
|
|
.of_match_table = fsl_qspi_dt_ids,
|
|
},
|
|
.probe = fsl_qspi_probe,
|
|
.remove = fsl_qspi_remove,
|
|
.suspend = fsl_qspi_suspend,
|
|
.resume = fsl_qspi_resume,
|
|
};
|
|
module_platform_driver(fsl_qspi_driver);
|
|
|
|
MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
|
|
MODULE_AUTHOR("Freescale Semiconductor Inc.");
|
|
MODULE_LICENSE("GPL v2");
|