1297 lines
32 KiB
C
1297 lines
32 KiB
C
/* linux/drivers/mtd/nand/s3c2410.c
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*
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* Copyright © 2004-2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Samsung S3C2410/S3C2440/S3C2412 NAND driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define pr_fmt(fmt) "nand-s3c2410: " fmt
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#ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
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#define DEBUG
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#endif
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_data/mtd-nand-s3c2410.h>
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#define S3C2410_NFREG(x) (x)
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#define S3C2410_NFCONF S3C2410_NFREG(0x00)
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#define S3C2410_NFCMD S3C2410_NFREG(0x04)
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#define S3C2410_NFADDR S3C2410_NFREG(0x08)
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#define S3C2410_NFDATA S3C2410_NFREG(0x0C)
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#define S3C2410_NFSTAT S3C2410_NFREG(0x10)
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#define S3C2410_NFECC S3C2410_NFREG(0x14)
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#define S3C2440_NFCONT S3C2410_NFREG(0x04)
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#define S3C2440_NFCMD S3C2410_NFREG(0x08)
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#define S3C2440_NFADDR S3C2410_NFREG(0x0C)
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#define S3C2440_NFDATA S3C2410_NFREG(0x10)
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#define S3C2440_NFSTAT S3C2410_NFREG(0x20)
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#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
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#define S3C2412_NFSTAT S3C2410_NFREG(0x28)
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#define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
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#define S3C2410_NFCONF_EN (1<<15)
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#define S3C2410_NFCONF_INITECC (1<<12)
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#define S3C2410_NFCONF_nFCE (1<<11)
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#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
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#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
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#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
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#define S3C2410_NFSTAT_BUSY (1<<0)
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#define S3C2440_NFCONF_TACLS(x) ((x)<<12)
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#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
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#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
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#define S3C2440_NFCONT_INITECC (1<<4)
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#define S3C2440_NFCONT_nFCE (1<<1)
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#define S3C2440_NFCONT_ENABLE (1<<0)
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#define S3C2440_NFSTAT_READY (1<<0)
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#define S3C2412_NFCONF_NANDBOOT (1<<31)
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#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
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#define S3C2412_NFCONT_nFCE0 (1<<1)
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#define S3C2412_NFSTAT_READY (1<<0)
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/* new oob placement block for use with hardware ecc generation
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*/
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static int s3c2410_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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if (section)
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return -ERANGE;
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oobregion->offset = 0;
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oobregion->length = 3;
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return 0;
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}
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static int s3c2410_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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if (section)
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return -ERANGE;
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oobregion->offset = 8;
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oobregion->length = 8;
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return 0;
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}
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static const struct mtd_ooblayout_ops s3c2410_ooblayout_ops = {
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.ecc = s3c2410_ooblayout_ecc,
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.free = s3c2410_ooblayout_free,
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};
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/* controller and mtd information */
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struct s3c2410_nand_info;
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/**
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* struct s3c2410_nand_mtd - driver MTD structure
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* @mtd: The MTD instance to pass to the MTD layer.
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* @chip: The NAND chip information.
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* @set: The platform information supplied for this set of NAND chips.
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* @info: Link back to the hardware information.
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* @scan_res: The result from calling nand_scan_ident().
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*/
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struct s3c2410_nand_mtd {
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struct nand_chip chip;
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struct s3c2410_nand_set *set;
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struct s3c2410_nand_info *info;
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int scan_res;
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};
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enum s3c_cpu_type {
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TYPE_S3C2410,
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TYPE_S3C2412,
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TYPE_S3C2440,
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};
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enum s3c_nand_clk_state {
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CLOCK_DISABLE = 0,
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CLOCK_ENABLE,
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CLOCK_SUSPEND,
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};
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/* overview of the s3c2410 nand state */
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/**
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* struct s3c2410_nand_info - NAND controller state.
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* @mtds: An array of MTD instances on this controoler.
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* @platform: The platform data for this board.
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* @device: The platform device we bound to.
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* @clk: The clock resource for this controller.
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* @regs: The area mapped for the hardware registers.
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* @sel_reg: Pointer to the register controlling the NAND selection.
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* @sel_bit: The bit in @sel_reg to select the NAND chip.
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* @mtd_count: The number of MTDs created from this controller.
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* @save_sel: The contents of @sel_reg to be saved over suspend.
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* @clk_rate: The clock rate from @clk.
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* @clk_state: The current clock state.
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* @cpu_type: The exact type of this controller.
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*/
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struct s3c2410_nand_info {
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/* mtd info */
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struct nand_hw_control controller;
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struct s3c2410_nand_mtd *mtds;
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struct s3c2410_platform_nand *platform;
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/* device info */
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struct device *device;
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struct clk *clk;
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void __iomem *regs;
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void __iomem *sel_reg;
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int sel_bit;
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int mtd_count;
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unsigned long save_sel;
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unsigned long clk_rate;
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enum s3c_nand_clk_state clk_state;
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enum s3c_cpu_type cpu_type;
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#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
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struct notifier_block freq_transition;
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#endif
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};
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struct s3c24XX_nand_devtype_data {
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enum s3c_cpu_type type;
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};
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static const struct s3c24XX_nand_devtype_data s3c2410_nand_devtype_data = {
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.type = TYPE_S3C2410,
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};
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static const struct s3c24XX_nand_devtype_data s3c2412_nand_devtype_data = {
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.type = TYPE_S3C2412,
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};
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static const struct s3c24XX_nand_devtype_data s3c2440_nand_devtype_data = {
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.type = TYPE_S3C2440,
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};
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/* conversion functions */
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static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
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{
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return container_of(mtd_to_nand(mtd), struct s3c2410_nand_mtd,
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chip);
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}
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static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
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{
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return s3c2410_nand_mtd_toours(mtd)->info;
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}
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static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
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{
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return platform_get_drvdata(dev);
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}
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static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
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{
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return dev_get_platdata(&dev->dev);
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}
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static inline int allow_clk_suspend(struct s3c2410_nand_info *info)
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{
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#ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
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return 1;
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#else
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return 0;
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#endif
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}
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/**
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* s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock.
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* @info: The controller instance.
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* @new_state: State to which clock should be set.
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*/
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static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info,
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enum s3c_nand_clk_state new_state)
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{
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if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND)
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return;
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if (info->clk_state == CLOCK_ENABLE) {
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if (new_state != CLOCK_ENABLE)
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clk_disable_unprepare(info->clk);
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} else {
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if (new_state == CLOCK_ENABLE)
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clk_prepare_enable(info->clk);
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}
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info->clk_state = new_state;
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}
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/* timing calculations */
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#define NS_IN_KHZ 1000000
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/**
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* s3c_nand_calc_rate - calculate timing data.
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* @wanted: The cycle time in nanoseconds.
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* @clk: The clock rate in kHz.
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* @max: The maximum divider value.
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*
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* Calculate the timing value from the given parameters.
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*/
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static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
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{
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int result;
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result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ);
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pr_debug("result %d from %ld, %d\n", result, clk, wanted);
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if (result > max) {
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pr_err("%d ns is too big for current clock rate %ld\n",
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wanted, clk);
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return -1;
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}
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if (result < 1)
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result = 1;
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return result;
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}
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#define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
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/* controller setup */
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/**
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* s3c2410_nand_setrate - setup controller timing information.
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* @info: The controller instance.
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*
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* Given the information supplied by the platform, calculate and set
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* the necessary timing registers in the hardware to generate the
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* necessary timing cycles to the hardware.
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*/
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static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
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{
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struct s3c2410_platform_nand *plat = info->platform;
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int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
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int tacls, twrph0, twrph1;
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unsigned long clkrate = clk_get_rate(info->clk);
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unsigned long uninitialized_var(set), cfg, uninitialized_var(mask);
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unsigned long flags;
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/* calculate the timing information for the controller */
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info->clk_rate = clkrate;
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clkrate /= 1000; /* turn clock into kHz for ease of use */
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if (plat != NULL) {
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tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
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twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
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twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
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} else {
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/* default timings */
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tacls = tacls_max;
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twrph0 = 8;
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twrph1 = 8;
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}
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if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
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dev_err(info->device, "cannot get suitable timings\n");
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return -EINVAL;
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}
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dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
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tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate),
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twrph1, to_ns(twrph1, clkrate));
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switch (info->cpu_type) {
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case TYPE_S3C2410:
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mask = (S3C2410_NFCONF_TACLS(3) |
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S3C2410_NFCONF_TWRPH0(7) |
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S3C2410_NFCONF_TWRPH1(7));
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set = S3C2410_NFCONF_EN;
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set |= S3C2410_NFCONF_TACLS(tacls - 1);
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set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
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set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
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break;
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case TYPE_S3C2440:
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case TYPE_S3C2412:
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mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) |
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S3C2440_NFCONF_TWRPH0(7) |
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S3C2440_NFCONF_TWRPH1(7));
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set = S3C2440_NFCONF_TACLS(tacls - 1);
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set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
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set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
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break;
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default:
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BUG();
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}
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local_irq_save(flags);
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cfg = readl(info->regs + S3C2410_NFCONF);
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cfg &= ~mask;
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cfg |= set;
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writel(cfg, info->regs + S3C2410_NFCONF);
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local_irq_restore(flags);
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dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
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return 0;
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}
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/**
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* s3c2410_nand_inithw - basic hardware initialisation
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* @info: The hardware state.
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*
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* Do the basic initialisation of the hardware, using s3c2410_nand_setrate()
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* to setup the hardware access speeds and set the controller to be enabled.
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*/
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static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
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{
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int ret;
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ret = s3c2410_nand_setrate(info);
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if (ret < 0)
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return ret;
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switch (info->cpu_type) {
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case TYPE_S3C2410:
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default:
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break;
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case TYPE_S3C2440:
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case TYPE_S3C2412:
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/* enable the controller and de-assert nFCE */
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writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
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}
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return 0;
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}
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/**
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* s3c2410_nand_select_chip - select the given nand chip
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* @mtd: The MTD instance for this chip.
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* @chip: The chip number.
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*
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* This is called by the MTD layer to either select a given chip for the
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* @mtd instance, or to indicate that the access has finished and the
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* chip can be de-selected.
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*
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* The routine ensures that the nFCE line is correctly setup, and any
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* platform specific selection code is called to route nFCE to the specific
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* chip.
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*/
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static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
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{
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struct s3c2410_nand_info *info;
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struct s3c2410_nand_mtd *nmtd;
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struct nand_chip *this = mtd_to_nand(mtd);
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unsigned long cur;
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nmtd = nand_get_controller_data(this);
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info = nmtd->info;
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if (chip != -1)
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s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
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cur = readl(info->sel_reg);
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if (chip == -1) {
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cur |= info->sel_bit;
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} else {
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if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
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dev_err(info->device, "invalid chip %d\n", chip);
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return;
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}
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if (info->platform != NULL) {
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if (info->platform->select_chip != NULL)
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(info->platform->select_chip) (nmtd->set, chip);
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}
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cur &= ~info->sel_bit;
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}
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writel(cur, info->sel_reg);
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if (chip == -1)
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s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
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}
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/* s3c2410_nand_hwcontrol
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*
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* Issue command and address cycles to the chip
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*/
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static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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writeb(cmd, info->regs + S3C2410_NFCMD);
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else
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writeb(cmd, info->regs + S3C2410_NFADDR);
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}
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/* command and control functions */
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|
|
static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
|
|
unsigned int ctrl)
|
|
{
|
|
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
|
|
|
|
if (cmd == NAND_CMD_NONE)
|
|
return;
|
|
|
|
if (ctrl & NAND_CLE)
|
|
writeb(cmd, info->regs + S3C2440_NFCMD);
|
|
else
|
|
writeb(cmd, info->regs + S3C2440_NFADDR);
|
|
}
|
|
|
|
/* s3c2410_nand_devready()
|
|
*
|
|
* returns 0 if the nand is busy, 1 if it is ready
|
|
*/
|
|
|
|
static int s3c2410_nand_devready(struct mtd_info *mtd)
|
|
{
|
|
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
|
|
return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
|
|
}
|
|
|
|
static int s3c2440_nand_devready(struct mtd_info *mtd)
|
|
{
|
|
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
|
|
return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
|
|
}
|
|
|
|
static int s3c2412_nand_devready(struct mtd_info *mtd)
|
|
{
|
|
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
|
|
return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
|
|
}
|
|
|
|
/* ECC handling functions */
|
|
|
|
static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
|
|
u_char *read_ecc, u_char *calc_ecc)
|
|
{
|
|
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
|
|
unsigned int diff0, diff1, diff2;
|
|
unsigned int bit, byte;
|
|
|
|
pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
|
|
|
|
diff0 = read_ecc[0] ^ calc_ecc[0];
|
|
diff1 = read_ecc[1] ^ calc_ecc[1];
|
|
diff2 = read_ecc[2] ^ calc_ecc[2];
|
|
|
|
pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n",
|
|
__func__, 3, read_ecc, 3, calc_ecc,
|
|
diff0, diff1, diff2);
|
|
|
|
if (diff0 == 0 && diff1 == 0 && diff2 == 0)
|
|
return 0; /* ECC is ok */
|
|
|
|
/* sometimes people do not think about using the ECC, so check
|
|
* to see if we have an 0xff,0xff,0xff read ECC and then ignore
|
|
* the error, on the assumption that this is an un-eccd page.
|
|
*/
|
|
if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
|
|
&& info->platform->ignore_unset_ecc)
|
|
return 0;
|
|
|
|
/* Can we correct this ECC (ie, one row and column change).
|
|
* Note, this is similar to the 256 error code on smartmedia */
|
|
|
|
if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
|
|
((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
|
|
((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
|
|
/* calculate the bit position of the error */
|
|
|
|
bit = ((diff2 >> 3) & 1) |
|
|
((diff2 >> 4) & 2) |
|
|
((diff2 >> 5) & 4);
|
|
|
|
/* calculate the byte position of the error */
|
|
|
|
byte = ((diff2 << 7) & 0x100) |
|
|
((diff1 << 0) & 0x80) |
|
|
((diff1 << 1) & 0x40) |
|
|
((diff1 << 2) & 0x20) |
|
|
((diff1 << 3) & 0x10) |
|
|
((diff0 >> 4) & 0x08) |
|
|
((diff0 >> 3) & 0x04) |
|
|
((diff0 >> 2) & 0x02) |
|
|
((diff0 >> 1) & 0x01);
|
|
|
|
dev_dbg(info->device, "correcting error bit %d, byte %d\n",
|
|
bit, byte);
|
|
|
|
dat[byte] ^= (1 << bit);
|
|
return 1;
|
|
}
|
|
|
|
/* if there is only one bit difference in the ECC, then
|
|
* one of only a row or column parity has changed, which
|
|
* means the error is most probably in the ECC itself */
|
|
|
|
diff0 |= (diff1 << 8);
|
|
diff0 |= (diff2 << 16);
|
|
|
|
/* equal to "(diff0 & ~(1 << __ffs(diff0)))" */
|
|
if ((diff0 & (diff0 - 1)) == 0)
|
|
return 1;
|
|
|
|
return -1;
|
|
}
|
|
|
|
/* ECC functions
|
|
*
|
|
* These allow the s3c2410 and s3c2440 to use the controller's ECC
|
|
* generator block to ECC the data as it passes through]
|
|
*/
|
|
|
|
static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
|
|
{
|
|
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
|
|
unsigned long ctrl;
|
|
|
|
ctrl = readl(info->regs + S3C2410_NFCONF);
|
|
ctrl |= S3C2410_NFCONF_INITECC;
|
|
writel(ctrl, info->regs + S3C2410_NFCONF);
|
|
}
|
|
|
|
static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
|
|
{
|
|
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
|
|
unsigned long ctrl;
|
|
|
|
ctrl = readl(info->regs + S3C2440_NFCONT);
|
|
writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC,
|
|
info->regs + S3C2440_NFCONT);
|
|
}
|
|
|
|
static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
|
|
{
|
|
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
|
|
unsigned long ctrl;
|
|
|
|
ctrl = readl(info->regs + S3C2440_NFCONT);
|
|
writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
|
|
}
|
|
|
|
static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
|
|
u_char *ecc_code)
|
|
{
|
|
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
|
|
|
|
ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
|
|
ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
|
|
ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
|
|
|
|
pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
|
|
u_char *ecc_code)
|
|
{
|
|
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
|
|
unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
|
|
|
|
ecc_code[0] = ecc;
|
|
ecc_code[1] = ecc >> 8;
|
|
ecc_code[2] = ecc >> 16;
|
|
|
|
pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
|
|
u_char *ecc_code)
|
|
{
|
|
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
|
|
unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
|
|
|
|
ecc_code[0] = ecc;
|
|
ecc_code[1] = ecc >> 8;
|
|
ecc_code[2] = ecc >> 16;
|
|
|
|
pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* over-ride the standard functions for a little more speed. We can
|
|
* use read/write block to move the data buffers to/from the controller
|
|
*/
|
|
|
|
static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
|
|
{
|
|
struct nand_chip *this = mtd_to_nand(mtd);
|
|
readsb(this->IO_ADDR_R, buf, len);
|
|
}
|
|
|
|
static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
|
|
{
|
|
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
|
|
|
|
readsl(info->regs + S3C2440_NFDATA, buf, len >> 2);
|
|
|
|
/* cleanup if we've got less than a word to do */
|
|
if (len & 3) {
|
|
buf += len & ~3;
|
|
|
|
for (; len & 3; len--)
|
|
*buf++ = readb(info->regs + S3C2440_NFDATA);
|
|
}
|
|
}
|
|
|
|
static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
|
|
int len)
|
|
{
|
|
struct nand_chip *this = mtd_to_nand(mtd);
|
|
writesb(this->IO_ADDR_W, buf, len);
|
|
}
|
|
|
|
static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
|
|
int len)
|
|
{
|
|
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
|
|
|
|
writesl(info->regs + S3C2440_NFDATA, buf, len >> 2);
|
|
|
|
/* cleanup any fractional write */
|
|
if (len & 3) {
|
|
buf += len & ~3;
|
|
|
|
for (; len & 3; len--, buf++)
|
|
writeb(*buf, info->regs + S3C2440_NFDATA);
|
|
}
|
|
}
|
|
|
|
/* cpufreq driver support */
|
|
|
|
#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
|
|
|
|
static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb,
|
|
unsigned long val, void *data)
|
|
{
|
|
struct s3c2410_nand_info *info;
|
|
unsigned long newclk;
|
|
|
|
info = container_of(nb, struct s3c2410_nand_info, freq_transition);
|
|
newclk = clk_get_rate(info->clk);
|
|
|
|
if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||
|
|
(val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {
|
|
s3c2410_nand_setrate(info);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
|
|
{
|
|
info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;
|
|
|
|
return cpufreq_register_notifier(&info->freq_transition,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
}
|
|
|
|
static inline void
|
|
s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
|
|
{
|
|
cpufreq_unregister_notifier(&info->freq_transition,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
}
|
|
|
|
#else
|
|
static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void
|
|
s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
/* device management functions */
|
|
|
|
static int s3c24xx_nand_remove(struct platform_device *pdev)
|
|
{
|
|
struct s3c2410_nand_info *info = to_nand_info(pdev);
|
|
|
|
if (info == NULL)
|
|
return 0;
|
|
|
|
s3c2410_nand_cpufreq_deregister(info);
|
|
|
|
/* Release all our mtds and their partitions, then go through
|
|
* freeing the resources used
|
|
*/
|
|
|
|
if (info->mtds != NULL) {
|
|
struct s3c2410_nand_mtd *ptr = info->mtds;
|
|
int mtdno;
|
|
|
|
for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
|
|
pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
|
|
nand_release(nand_to_mtd(&ptr->chip));
|
|
}
|
|
}
|
|
|
|
/* free the common resources */
|
|
|
|
if (!IS_ERR(info->clk))
|
|
s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
|
|
struct s3c2410_nand_mtd *mtd,
|
|
struct s3c2410_nand_set *set)
|
|
{
|
|
if (set) {
|
|
struct mtd_info *mtdinfo = nand_to_mtd(&mtd->chip);
|
|
|
|
mtdinfo->name = set->name;
|
|
|
|
return mtd_device_parse_register(mtdinfo, NULL, NULL,
|
|
set->partitions, set->nr_partitions);
|
|
}
|
|
|
|
return -ENODEV;
|
|
}
|
|
|
|
static int s3c2410_nand_setup_data_interface(struct mtd_info *mtd, int csline,
|
|
const struct nand_data_interface *conf)
|
|
{
|
|
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
|
|
struct s3c2410_platform_nand *pdata = info->platform;
|
|
const struct nand_sdr_timings *timings;
|
|
int tacls;
|
|
|
|
timings = nand_get_sdr_timings(conf);
|
|
if (IS_ERR(timings))
|
|
return -ENOTSUPP;
|
|
|
|
tacls = timings->tCLS_min - timings->tWP_min;
|
|
if (tacls < 0)
|
|
tacls = 0;
|
|
|
|
pdata->tacls = DIV_ROUND_UP(tacls, 1000);
|
|
pdata->twrph0 = DIV_ROUND_UP(timings->tWP_min, 1000);
|
|
pdata->twrph1 = DIV_ROUND_UP(timings->tCLH_min, 1000);
|
|
|
|
return s3c2410_nand_setrate(info);
|
|
}
|
|
|
|
/**
|
|
* s3c2410_nand_init_chip - initialise a single instance of an chip
|
|
* @info: The base NAND controller the chip is on.
|
|
* @nmtd: The new controller MTD instance to fill in.
|
|
* @set: The information passed from the board specific platform data.
|
|
*
|
|
* Initialise the given @nmtd from the information in @info and @set. This
|
|
* readies the structure for use with the MTD layer functions by ensuring
|
|
* all pointers are setup and the necessary control routines selected.
|
|
*/
|
|
static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
|
|
struct s3c2410_nand_mtd *nmtd,
|
|
struct s3c2410_nand_set *set)
|
|
{
|
|
struct device_node *np = info->device->of_node;
|
|
struct nand_chip *chip = &nmtd->chip;
|
|
void __iomem *regs = info->regs;
|
|
|
|
nand_set_flash_node(chip, set->of_node);
|
|
|
|
chip->write_buf = s3c2410_nand_write_buf;
|
|
chip->read_buf = s3c2410_nand_read_buf;
|
|
chip->select_chip = s3c2410_nand_select_chip;
|
|
chip->chip_delay = 50;
|
|
nand_set_controller_data(chip, nmtd);
|
|
chip->options = set->options;
|
|
chip->controller = &info->controller;
|
|
|
|
/*
|
|
* let's keep behavior unchanged for legacy boards booting via pdata and
|
|
* auto-detect timings only when booting with a device tree.
|
|
*/
|
|
if (np)
|
|
chip->setup_data_interface = s3c2410_nand_setup_data_interface;
|
|
|
|
switch (info->cpu_type) {
|
|
case TYPE_S3C2410:
|
|
chip->IO_ADDR_W = regs + S3C2410_NFDATA;
|
|
info->sel_reg = regs + S3C2410_NFCONF;
|
|
info->sel_bit = S3C2410_NFCONF_nFCE;
|
|
chip->cmd_ctrl = s3c2410_nand_hwcontrol;
|
|
chip->dev_ready = s3c2410_nand_devready;
|
|
break;
|
|
|
|
case TYPE_S3C2440:
|
|
chip->IO_ADDR_W = regs + S3C2440_NFDATA;
|
|
info->sel_reg = regs + S3C2440_NFCONT;
|
|
info->sel_bit = S3C2440_NFCONT_nFCE;
|
|
chip->cmd_ctrl = s3c2440_nand_hwcontrol;
|
|
chip->dev_ready = s3c2440_nand_devready;
|
|
chip->read_buf = s3c2440_nand_read_buf;
|
|
chip->write_buf = s3c2440_nand_write_buf;
|
|
break;
|
|
|
|
case TYPE_S3C2412:
|
|
chip->IO_ADDR_W = regs + S3C2440_NFDATA;
|
|
info->sel_reg = regs + S3C2440_NFCONT;
|
|
info->sel_bit = S3C2412_NFCONT_nFCE0;
|
|
chip->cmd_ctrl = s3c2440_nand_hwcontrol;
|
|
chip->dev_ready = s3c2412_nand_devready;
|
|
|
|
if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
|
|
dev_info(info->device, "System booted from NAND\n");
|
|
|
|
break;
|
|
}
|
|
|
|
chip->IO_ADDR_R = chip->IO_ADDR_W;
|
|
|
|
nmtd->info = info;
|
|
nmtd->set = set;
|
|
|
|
chip->ecc.mode = info->platform->ecc_mode;
|
|
|
|
/*
|
|
* If you use u-boot BBT creation code, specifying this flag will
|
|
* let the kernel fish out the BBT from the NAND.
|
|
*/
|
|
if (set->flash_bbt)
|
|
chip->bbt_options |= NAND_BBT_USE_FLASH;
|
|
}
|
|
|
|
/**
|
|
* s3c2410_nand_update_chip - post probe update
|
|
* @info: The controller instance.
|
|
* @nmtd: The driver version of the MTD instance.
|
|
*
|
|
* This routine is called after the chip probe has successfully completed
|
|
* and the relevant per-chip information updated. This call ensure that
|
|
* we update the internal state accordingly.
|
|
*
|
|
* The internal state is currently limited to the ECC state information.
|
|
*/
|
|
static int s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
|
|
struct s3c2410_nand_mtd *nmtd)
|
|
{
|
|
struct nand_chip *chip = &nmtd->chip;
|
|
|
|
switch (chip->ecc.mode) {
|
|
|
|
case NAND_ECC_NONE:
|
|
dev_info(info->device, "ECC disabled\n");
|
|
break;
|
|
|
|
case NAND_ECC_SOFT:
|
|
/*
|
|
* This driver expects Hamming based ECC when ecc_mode is set
|
|
* to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
|
|
* avoid adding an extra ecc_algo field to
|
|
* s3c2410_platform_nand.
|
|
*/
|
|
chip->ecc.algo = NAND_ECC_HAMMING;
|
|
dev_info(info->device, "soft ECC\n");
|
|
break;
|
|
|
|
case NAND_ECC_HW:
|
|
chip->ecc.calculate = s3c2410_nand_calculate_ecc;
|
|
chip->ecc.correct = s3c2410_nand_correct_data;
|
|
chip->ecc.strength = 1;
|
|
|
|
switch (info->cpu_type) {
|
|
case TYPE_S3C2410:
|
|
chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
|
|
chip->ecc.calculate = s3c2410_nand_calculate_ecc;
|
|
break;
|
|
|
|
case TYPE_S3C2412:
|
|
chip->ecc.hwctl = s3c2412_nand_enable_hwecc;
|
|
chip->ecc.calculate = s3c2412_nand_calculate_ecc;
|
|
break;
|
|
|
|
case TYPE_S3C2440:
|
|
chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
|
|
chip->ecc.calculate = s3c2440_nand_calculate_ecc;
|
|
break;
|
|
}
|
|
|
|
dev_dbg(info->device, "chip %p => page shift %d\n",
|
|
chip, chip->page_shift);
|
|
|
|
/* change the behaviour depending on whether we are using
|
|
* the large or small page nand device */
|
|
if (chip->page_shift > 10) {
|
|
chip->ecc.size = 256;
|
|
chip->ecc.bytes = 3;
|
|
} else {
|
|
chip->ecc.size = 512;
|
|
chip->ecc.bytes = 3;
|
|
mtd_set_ooblayout(nand_to_mtd(chip),
|
|
&s3c2410_ooblayout_ops);
|
|
}
|
|
|
|
dev_info(info->device, "hardware ECC\n");
|
|
break;
|
|
|
|
default:
|
|
dev_err(info->device, "invalid ECC mode!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (chip->bbt_options & NAND_BBT_USE_FLASH)
|
|
chip->options |= NAND_SKIP_BBTSCAN;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id s3c24xx_nand_dt_ids[] = {
|
|
{
|
|
.compatible = "samsung,s3c2410-nand",
|
|
.data = &s3c2410_nand_devtype_data,
|
|
}, {
|
|
/* also compatible with s3c6400 */
|
|
.compatible = "samsung,s3c2412-nand",
|
|
.data = &s3c2412_nand_devtype_data,
|
|
}, {
|
|
.compatible = "samsung,s3c2440-nand",
|
|
.data = &s3c2440_nand_devtype_data,
|
|
},
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, s3c24xx_nand_dt_ids);
|
|
|
|
static int s3c24xx_nand_probe_dt(struct platform_device *pdev)
|
|
{
|
|
const struct s3c24XX_nand_devtype_data *devtype_data;
|
|
struct s3c2410_platform_nand *pdata;
|
|
struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
|
|
struct device_node *np = pdev->dev.of_node, *child;
|
|
struct s3c2410_nand_set *sets;
|
|
|
|
devtype_data = of_device_get_match_data(&pdev->dev);
|
|
if (!devtype_data)
|
|
return -ENODEV;
|
|
|
|
info->cpu_type = devtype_data->type;
|
|
|
|
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
|
|
if (!pdata)
|
|
return -ENOMEM;
|
|
|
|
pdev->dev.platform_data = pdata;
|
|
|
|
pdata->nr_sets = of_get_child_count(np);
|
|
if (!pdata->nr_sets)
|
|
return 0;
|
|
|
|
sets = devm_kzalloc(&pdev->dev, sizeof(*sets) * pdata->nr_sets,
|
|
GFP_KERNEL);
|
|
if (!sets)
|
|
return -ENOMEM;
|
|
|
|
pdata->sets = sets;
|
|
|
|
for_each_available_child_of_node(np, child) {
|
|
sets->name = (char *)child->name;
|
|
sets->of_node = child;
|
|
sets->nr_chips = 1;
|
|
|
|
of_node_get(child);
|
|
|
|
sets++;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s3c24xx_nand_probe_pdata(struct platform_device *pdev)
|
|
{
|
|
struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
|
|
|
|
info->cpu_type = platform_get_device_id(pdev)->driver_data;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* s3c24xx_nand_probe
|
|
*
|
|
* called by device layer when it finds a device matching
|
|
* one our driver can handled. This code checks to see if
|
|
* it can allocate all necessary resources then calls the
|
|
* nand layer to look for devices
|
|
*/
|
|
static int s3c24xx_nand_probe(struct platform_device *pdev)
|
|
{
|
|
struct s3c2410_platform_nand *plat;
|
|
struct s3c2410_nand_info *info;
|
|
struct s3c2410_nand_mtd *nmtd;
|
|
struct s3c2410_nand_set *sets;
|
|
struct resource *res;
|
|
int err = 0;
|
|
int size;
|
|
int nr_sets;
|
|
int setno;
|
|
|
|
info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
|
|
if (info == NULL) {
|
|
err = -ENOMEM;
|
|
goto exit_error;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, info);
|
|
|
|
nand_hw_control_init(&info->controller);
|
|
|
|
/* get the clock source and enable it */
|
|
|
|
info->clk = devm_clk_get(&pdev->dev, "nand");
|
|
if (IS_ERR(info->clk)) {
|
|
dev_err(&pdev->dev, "failed to get clock\n");
|
|
err = -ENOENT;
|
|
goto exit_error;
|
|
}
|
|
|
|
s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
|
|
|
|
if (pdev->dev.of_node)
|
|
err = s3c24xx_nand_probe_dt(pdev);
|
|
else
|
|
err = s3c24xx_nand_probe_pdata(pdev);
|
|
|
|
if (err)
|
|
goto exit_error;
|
|
|
|
plat = to_nand_plat(pdev);
|
|
|
|
/* allocate and map the resource */
|
|
|
|
/* currently we assume we have the one resource */
|
|
res = pdev->resource;
|
|
size = resource_size(res);
|
|
|
|
info->device = &pdev->dev;
|
|
info->platform = plat;
|
|
|
|
info->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(info->regs)) {
|
|
err = PTR_ERR(info->regs);
|
|
goto exit_error;
|
|
}
|
|
|
|
dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
|
|
|
|
sets = (plat != NULL) ? plat->sets : NULL;
|
|
nr_sets = (plat != NULL) ? plat->nr_sets : 1;
|
|
|
|
info->mtd_count = nr_sets;
|
|
|
|
/* allocate our information */
|
|
|
|
size = nr_sets * sizeof(*info->mtds);
|
|
info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
|
|
if (info->mtds == NULL) {
|
|
err = -ENOMEM;
|
|
goto exit_error;
|
|
}
|
|
|
|
/* initialise all possible chips */
|
|
|
|
nmtd = info->mtds;
|
|
|
|
for (setno = 0; setno < nr_sets; setno++, nmtd++) {
|
|
struct mtd_info *mtd = nand_to_mtd(&nmtd->chip);
|
|
|
|
pr_debug("initialising set %d (%p, info %p)\n",
|
|
setno, nmtd, info);
|
|
|
|
mtd->dev.parent = &pdev->dev;
|
|
s3c2410_nand_init_chip(info, nmtd, sets);
|
|
|
|
nmtd->scan_res = nand_scan_ident(mtd,
|
|
(sets) ? sets->nr_chips : 1,
|
|
NULL);
|
|
|
|
if (nmtd->scan_res == 0) {
|
|
err = s3c2410_nand_update_chip(info, nmtd);
|
|
if (err < 0)
|
|
goto exit_error;
|
|
nand_scan_tail(mtd);
|
|
s3c2410_nand_add_partition(info, nmtd, sets);
|
|
}
|
|
|
|
if (sets != NULL)
|
|
sets++;
|
|
}
|
|
|
|
/* initialise the hardware */
|
|
err = s3c2410_nand_inithw(info);
|
|
if (err != 0)
|
|
goto exit_error;
|
|
|
|
err = s3c2410_nand_cpufreq_register(info);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to init cpufreq support\n");
|
|
goto exit_error;
|
|
}
|
|
|
|
if (allow_clk_suspend(info)) {
|
|
dev_info(&pdev->dev, "clock idle support enabled\n");
|
|
s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
|
|
}
|
|
|
|
return 0;
|
|
|
|
exit_error:
|
|
s3c24xx_nand_remove(pdev);
|
|
|
|
if (err == 0)
|
|
err = -EINVAL;
|
|
return err;
|
|
}
|
|
|
|
/* PM Support */
|
|
#ifdef CONFIG_PM
|
|
|
|
static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
|
|
{
|
|
struct s3c2410_nand_info *info = platform_get_drvdata(dev);
|
|
|
|
if (info) {
|
|
info->save_sel = readl(info->sel_reg);
|
|
|
|
/* For the moment, we must ensure nFCE is high during
|
|
* the time we are suspended. This really should be
|
|
* handled by suspending the MTDs we are using, but
|
|
* that is currently not the case. */
|
|
|
|
writel(info->save_sel | info->sel_bit, info->sel_reg);
|
|
|
|
s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s3c24xx_nand_resume(struct platform_device *dev)
|
|
{
|
|
struct s3c2410_nand_info *info = platform_get_drvdata(dev);
|
|
unsigned long sel;
|
|
|
|
if (info) {
|
|
s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
|
|
s3c2410_nand_inithw(info);
|
|
|
|
/* Restore the state of the nFCE line. */
|
|
|
|
sel = readl(info->sel_reg);
|
|
sel &= ~info->sel_bit;
|
|
sel |= info->save_sel & info->sel_bit;
|
|
writel(sel, info->sel_reg);
|
|
|
|
s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#else
|
|
#define s3c24xx_nand_suspend NULL
|
|
#define s3c24xx_nand_resume NULL
|
|
#endif
|
|
|
|
/* driver device registration */
|
|
|
|
static const struct platform_device_id s3c24xx_driver_ids[] = {
|
|
{
|
|
.name = "s3c2410-nand",
|
|
.driver_data = TYPE_S3C2410,
|
|
}, {
|
|
.name = "s3c2440-nand",
|
|
.driver_data = TYPE_S3C2440,
|
|
}, {
|
|
.name = "s3c2412-nand",
|
|
.driver_data = TYPE_S3C2412,
|
|
}, {
|
|
.name = "s3c6400-nand",
|
|
.driver_data = TYPE_S3C2412, /* compatible with 2412 */
|
|
},
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
|
|
|
|
static struct platform_driver s3c24xx_nand_driver = {
|
|
.probe = s3c24xx_nand_probe,
|
|
.remove = s3c24xx_nand_remove,
|
|
.suspend = s3c24xx_nand_suspend,
|
|
.resume = s3c24xx_nand_resume,
|
|
.id_table = s3c24xx_driver_ids,
|
|
.driver = {
|
|
.name = "s3c24xx-nand",
|
|
.of_match_table = s3c24xx_nand_dt_ids,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(s3c24xx_nand_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
|
|
MODULE_DESCRIPTION("S3C24XX MTD NAND driver");
|