739 lines
19 KiB
C
739 lines
19 KiB
C
/*
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tda18271-common.c - driver for the Philips / NXP TDA18271 silicon tuner
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Copyright (C) 2007, 2008 Michael Krufky <mkrufky@linuxtv.org>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "tda18271-priv.h"
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static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
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{
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struct tda18271_priv *priv = fe->tuner_priv;
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enum tda18271_i2c_gate gate;
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int ret = 0;
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switch (priv->gate) {
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case TDA18271_GATE_DIGITAL:
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case TDA18271_GATE_ANALOG:
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gate = priv->gate;
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break;
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case TDA18271_GATE_AUTO:
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default:
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switch (priv->mode) {
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case TDA18271_DIGITAL:
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gate = TDA18271_GATE_DIGITAL;
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break;
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case TDA18271_ANALOG:
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default:
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gate = TDA18271_GATE_ANALOG;
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break;
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}
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}
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switch (gate) {
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case TDA18271_GATE_ANALOG:
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if (fe->ops.analog_ops.i2c_gate_ctrl)
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ret = fe->ops.analog_ops.i2c_gate_ctrl(fe, enable);
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break;
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case TDA18271_GATE_DIGITAL:
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if (fe->ops.i2c_gate_ctrl)
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ret = fe->ops.i2c_gate_ctrl(fe, enable);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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};
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/*---------------------------------------------------------------------*/
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static void tda18271_dump_regs(struct dvb_frontend *fe, int extended)
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{
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struct tda18271_priv *priv = fe->tuner_priv;
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unsigned char *regs = priv->tda18271_regs;
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tda_reg("=== TDA18271 REG DUMP ===\n");
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tda_reg("ID_BYTE = 0x%02x\n", 0xff & regs[R_ID]);
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tda_reg("THERMO_BYTE = 0x%02x\n", 0xff & regs[R_TM]);
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tda_reg("POWER_LEVEL_BYTE = 0x%02x\n", 0xff & regs[R_PL]);
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tda_reg("EASY_PROG_BYTE_1 = 0x%02x\n", 0xff & regs[R_EP1]);
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tda_reg("EASY_PROG_BYTE_2 = 0x%02x\n", 0xff & regs[R_EP2]);
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tda_reg("EASY_PROG_BYTE_3 = 0x%02x\n", 0xff & regs[R_EP3]);
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tda_reg("EASY_PROG_BYTE_4 = 0x%02x\n", 0xff & regs[R_EP4]);
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tda_reg("EASY_PROG_BYTE_5 = 0x%02x\n", 0xff & regs[R_EP5]);
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tda_reg("CAL_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_CPD]);
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tda_reg("CAL_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_CD1]);
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tda_reg("CAL_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_CD2]);
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tda_reg("CAL_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_CD3]);
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tda_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]);
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tda_reg("MAIN_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_MD1]);
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tda_reg("MAIN_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_MD2]);
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tda_reg("MAIN_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_MD3]);
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/* only dump extended regs if DBG_ADV is set */
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if (!(tda18271_debug & DBG_ADV))
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return;
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/* W indicates write-only registers.
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* Register dump for write-only registers shows last value written. */
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tda_reg("EXTENDED_BYTE_1 = 0x%02x\n", 0xff & regs[R_EB1]);
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tda_reg("EXTENDED_BYTE_2 = 0x%02x\n", 0xff & regs[R_EB2]);
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tda_reg("EXTENDED_BYTE_3 = 0x%02x\n", 0xff & regs[R_EB3]);
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tda_reg("EXTENDED_BYTE_4 = 0x%02x\n", 0xff & regs[R_EB4]);
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tda_reg("EXTENDED_BYTE_5 = 0x%02x\n", 0xff & regs[R_EB5]);
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tda_reg("EXTENDED_BYTE_6 = 0x%02x\n", 0xff & regs[R_EB6]);
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tda_reg("EXTENDED_BYTE_7 = 0x%02x\n", 0xff & regs[R_EB7]);
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tda_reg("EXTENDED_BYTE_8 = 0x%02x\n", 0xff & regs[R_EB8]);
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tda_reg("EXTENDED_BYTE_9 W = 0x%02x\n", 0xff & regs[R_EB9]);
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tda_reg("EXTENDED_BYTE_10 = 0x%02x\n", 0xff & regs[R_EB10]);
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tda_reg("EXTENDED_BYTE_11 = 0x%02x\n", 0xff & regs[R_EB11]);
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tda_reg("EXTENDED_BYTE_12 = 0x%02x\n", 0xff & regs[R_EB12]);
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tda_reg("EXTENDED_BYTE_13 = 0x%02x\n", 0xff & regs[R_EB13]);
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tda_reg("EXTENDED_BYTE_14 = 0x%02x\n", 0xff & regs[R_EB14]);
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tda_reg("EXTENDED_BYTE_15 = 0x%02x\n", 0xff & regs[R_EB15]);
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tda_reg("EXTENDED_BYTE_16 W = 0x%02x\n", 0xff & regs[R_EB16]);
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tda_reg("EXTENDED_BYTE_17 W = 0x%02x\n", 0xff & regs[R_EB17]);
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tda_reg("EXTENDED_BYTE_18 = 0x%02x\n", 0xff & regs[R_EB18]);
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tda_reg("EXTENDED_BYTE_19 W = 0x%02x\n", 0xff & regs[R_EB19]);
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tda_reg("EXTENDED_BYTE_20 W = 0x%02x\n", 0xff & regs[R_EB20]);
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tda_reg("EXTENDED_BYTE_21 = 0x%02x\n", 0xff & regs[R_EB21]);
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tda_reg("EXTENDED_BYTE_22 = 0x%02x\n", 0xff & regs[R_EB22]);
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tda_reg("EXTENDED_BYTE_23 = 0x%02x\n", 0xff & regs[R_EB23]);
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}
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int tda18271_read_regs(struct dvb_frontend *fe)
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{
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struct tda18271_priv *priv = fe->tuner_priv;
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unsigned char *regs = priv->tda18271_regs;
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unsigned char buf = 0x00;
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int ret;
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struct i2c_msg msg[] = {
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{ .addr = priv->i2c_props.addr, .flags = 0,
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.buf = &buf, .len = 1 },
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{ .addr = priv->i2c_props.addr, .flags = I2C_M_RD,
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.buf = regs, .len = 16 }
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};
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tda18271_i2c_gate_ctrl(fe, 1);
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/* read all registers */
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ret = i2c_transfer(priv->i2c_props.adap, msg, 2);
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tda18271_i2c_gate_ctrl(fe, 0);
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if (ret != 2)
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tda_err("ERROR: i2c_transfer returned: %d\n", ret);
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if (tda18271_debug & DBG_REG)
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tda18271_dump_regs(fe, 0);
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return (ret == 2 ? 0 : ret);
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}
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int tda18271_read_extended(struct dvb_frontend *fe)
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{
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struct tda18271_priv *priv = fe->tuner_priv;
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unsigned char *regs = priv->tda18271_regs;
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unsigned char regdump[TDA18271_NUM_REGS];
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unsigned char buf = 0x00;
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int ret, i;
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struct i2c_msg msg[] = {
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{ .addr = priv->i2c_props.addr, .flags = 0,
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.buf = &buf, .len = 1 },
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{ .addr = priv->i2c_props.addr, .flags = I2C_M_RD,
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.buf = regdump, .len = TDA18271_NUM_REGS }
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};
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tda18271_i2c_gate_ctrl(fe, 1);
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/* read all registers */
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ret = i2c_transfer(priv->i2c_props.adap, msg, 2);
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tda18271_i2c_gate_ctrl(fe, 0);
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if (ret != 2)
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tda_err("ERROR: i2c_transfer returned: %d\n", ret);
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for (i = 0; i < TDA18271_NUM_REGS; i++) {
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/* don't update write-only registers */
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if ((i != R_EB9) &&
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(i != R_EB16) &&
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(i != R_EB17) &&
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(i != R_EB19) &&
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(i != R_EB20))
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regs[i] = regdump[i];
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}
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if (tda18271_debug & DBG_REG)
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tda18271_dump_regs(fe, 1);
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return (ret == 2 ? 0 : ret);
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}
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static int __tda18271_write_regs(struct dvb_frontend *fe, int idx, int len,
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bool lock_i2c)
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{
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struct tda18271_priv *priv = fe->tuner_priv;
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unsigned char *regs = priv->tda18271_regs;
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unsigned char buf[TDA18271_NUM_REGS + 1];
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struct i2c_msg msg = { .addr = priv->i2c_props.addr, .flags = 0,
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.buf = buf };
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int i, ret = 1, max;
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BUG_ON((len == 0) || (idx + len > sizeof(buf)));
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switch (priv->small_i2c) {
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case TDA18271_03_BYTE_CHUNK_INIT:
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max = 3;
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break;
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case TDA18271_08_BYTE_CHUNK_INIT:
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max = 8;
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break;
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case TDA18271_16_BYTE_CHUNK_INIT:
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max = 16;
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break;
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case TDA18271_39_BYTE_CHUNK_INIT:
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default:
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max = 39;
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}
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/*
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* If lock_i2c is true, it will take the I2C bus for tda18271 private
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* usage during the entire write ops, as otherwise, bad things could
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* happen.
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* During device init, several write operations will happen. So,
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* tda18271_init_regs controls the I2C lock directly,
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* disabling lock_i2c here.
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*/
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if (lock_i2c) {
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tda18271_i2c_gate_ctrl(fe, 1);
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i2c_lock_adapter(priv->i2c_props.adap);
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}
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while (len) {
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if (max > len)
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max = len;
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buf[0] = idx;
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for (i = 1; i <= max; i++)
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buf[i] = regs[idx - 1 + i];
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msg.len = max + 1;
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/* write registers */
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ret = __i2c_transfer(priv->i2c_props.adap, &msg, 1);
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if (ret != 1)
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break;
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idx += max;
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len -= max;
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}
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if (lock_i2c) {
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i2c_unlock_adapter(priv->i2c_props.adap);
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tda18271_i2c_gate_ctrl(fe, 0);
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}
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if (ret != 1)
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tda_err("ERROR: idx = 0x%x, len = %d, i2c_transfer returned: %d\n",
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idx, max, ret);
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return (ret == 1 ? 0 : ret);
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}
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int tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
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{
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return __tda18271_write_regs(fe, idx, len, true);
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}
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/*---------------------------------------------------------------------*/
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static int __tda18271_charge_pump_source(struct dvb_frontend *fe,
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enum tda18271_pll pll, int force,
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bool lock_i2c)
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{
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struct tda18271_priv *priv = fe->tuner_priv;
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unsigned char *regs = priv->tda18271_regs;
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int r_cp = (pll == TDA18271_CAL_PLL) ? R_EB7 : R_EB4;
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regs[r_cp] &= ~0x20;
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regs[r_cp] |= ((force & 1) << 5);
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return __tda18271_write_regs(fe, r_cp, 1, lock_i2c);
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}
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int tda18271_charge_pump_source(struct dvb_frontend *fe,
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enum tda18271_pll pll, int force)
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{
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return __tda18271_charge_pump_source(fe, pll, force, true);
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}
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int tda18271_init_regs(struct dvb_frontend *fe)
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{
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struct tda18271_priv *priv = fe->tuner_priv;
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unsigned char *regs = priv->tda18271_regs;
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tda_dbg("initializing registers for device @ %d-%04x\n",
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i2c_adapter_id(priv->i2c_props.adap),
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priv->i2c_props.addr);
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/*
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* Don't let any other I2C transfer to happen at adapter during init,
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* as those could cause bad things
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*/
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tda18271_i2c_gate_ctrl(fe, 1);
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i2c_lock_adapter(priv->i2c_props.adap);
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/* initialize registers */
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switch (priv->id) {
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case TDA18271HDC1:
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regs[R_ID] = 0x83;
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break;
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case TDA18271HDC2:
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regs[R_ID] = 0x84;
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break;
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}
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regs[R_TM] = 0x08;
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regs[R_PL] = 0x80;
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regs[R_EP1] = 0xc6;
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regs[R_EP2] = 0xdf;
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regs[R_EP3] = 0x16;
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regs[R_EP4] = 0x60;
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regs[R_EP5] = 0x80;
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regs[R_CPD] = 0x80;
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regs[R_CD1] = 0x00;
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regs[R_CD2] = 0x00;
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regs[R_CD3] = 0x00;
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regs[R_MPD] = 0x00;
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regs[R_MD1] = 0x00;
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regs[R_MD2] = 0x00;
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regs[R_MD3] = 0x00;
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switch (priv->id) {
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case TDA18271HDC1:
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regs[R_EB1] = 0xff;
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break;
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case TDA18271HDC2:
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regs[R_EB1] = 0xfc;
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break;
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}
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regs[R_EB2] = 0x01;
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regs[R_EB3] = 0x84;
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regs[R_EB4] = 0x41;
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regs[R_EB5] = 0x01;
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regs[R_EB6] = 0x84;
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regs[R_EB7] = 0x40;
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regs[R_EB8] = 0x07;
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regs[R_EB9] = 0x00;
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regs[R_EB10] = 0x00;
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regs[R_EB11] = 0x96;
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switch (priv->id) {
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case TDA18271HDC1:
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regs[R_EB12] = 0x0f;
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break;
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case TDA18271HDC2:
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regs[R_EB12] = 0x33;
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break;
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}
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regs[R_EB13] = 0xc1;
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regs[R_EB14] = 0x00;
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regs[R_EB15] = 0x8f;
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regs[R_EB16] = 0x00;
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regs[R_EB17] = 0x00;
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switch (priv->id) {
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case TDA18271HDC1:
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regs[R_EB18] = 0x00;
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break;
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case TDA18271HDC2:
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regs[R_EB18] = 0x8c;
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break;
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}
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regs[R_EB19] = 0x00;
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regs[R_EB20] = 0x20;
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switch (priv->id) {
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case TDA18271HDC1:
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regs[R_EB21] = 0x33;
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break;
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case TDA18271HDC2:
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regs[R_EB21] = 0xb3;
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break;
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}
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regs[R_EB22] = 0x48;
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regs[R_EB23] = 0xb0;
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__tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS, false);
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/* setup agc1 gain */
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regs[R_EB17] = 0x00;
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__tda18271_write_regs(fe, R_EB17, 1, false);
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regs[R_EB17] = 0x03;
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__tda18271_write_regs(fe, R_EB17, 1, false);
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regs[R_EB17] = 0x43;
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__tda18271_write_regs(fe, R_EB17, 1, false);
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regs[R_EB17] = 0x4c;
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__tda18271_write_regs(fe, R_EB17, 1, false);
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/* setup agc2 gain */
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if ((priv->id) == TDA18271HDC1) {
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regs[R_EB20] = 0xa0;
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__tda18271_write_regs(fe, R_EB20, 1, false);
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regs[R_EB20] = 0xa7;
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__tda18271_write_regs(fe, R_EB20, 1, false);
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regs[R_EB20] = 0xe7;
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__tda18271_write_regs(fe, R_EB20, 1, false);
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regs[R_EB20] = 0xec;
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__tda18271_write_regs(fe, R_EB20, 1, false);
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}
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/* image rejection calibration */
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/* low-band */
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regs[R_EP3] = 0x1f;
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regs[R_EP4] = 0x66;
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regs[R_EP5] = 0x81;
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regs[R_CPD] = 0xcc;
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regs[R_CD1] = 0x6c;
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regs[R_CD2] = 0x00;
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regs[R_CD3] = 0x00;
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regs[R_MPD] = 0xcd;
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regs[R_MD1] = 0x77;
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regs[R_MD2] = 0x08;
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regs[R_MD3] = 0x00;
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__tda18271_write_regs(fe, R_EP3, 11, false);
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if ((priv->id) == TDA18271HDC2) {
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/* main pll cp source on */
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__tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 1, false);
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msleep(1);
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/* main pll cp source off */
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__tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 0, false);
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}
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|
|
msleep(5); /* pll locking */
|
|
|
|
/* launch detector */
|
|
__tda18271_write_regs(fe, R_EP1, 1, false);
|
|
msleep(5); /* wanted low measurement */
|
|
|
|
regs[R_EP5] = 0x85;
|
|
regs[R_CPD] = 0xcb;
|
|
regs[R_CD1] = 0x66;
|
|
regs[R_CD2] = 0x70;
|
|
|
|
__tda18271_write_regs(fe, R_EP3, 7, false);
|
|
msleep(5); /* pll locking */
|
|
|
|
/* launch optimization algorithm */
|
|
__tda18271_write_regs(fe, R_EP2, 1, false);
|
|
msleep(30); /* image low optimization completion */
|
|
|
|
/* mid-band */
|
|
regs[R_EP5] = 0x82;
|
|
regs[R_CPD] = 0xa8;
|
|
regs[R_CD2] = 0x00;
|
|
regs[R_MPD] = 0xa9;
|
|
regs[R_MD1] = 0x73;
|
|
regs[R_MD2] = 0x1a;
|
|
|
|
__tda18271_write_regs(fe, R_EP3, 11, false);
|
|
msleep(5); /* pll locking */
|
|
|
|
/* launch detector */
|
|
__tda18271_write_regs(fe, R_EP1, 1, false);
|
|
msleep(5); /* wanted mid measurement */
|
|
|
|
regs[R_EP5] = 0x86;
|
|
regs[R_CPD] = 0xa8;
|
|
regs[R_CD1] = 0x66;
|
|
regs[R_CD2] = 0xa0;
|
|
|
|
__tda18271_write_regs(fe, R_EP3, 7, false);
|
|
msleep(5); /* pll locking */
|
|
|
|
/* launch optimization algorithm */
|
|
__tda18271_write_regs(fe, R_EP2, 1, false);
|
|
msleep(30); /* image mid optimization completion */
|
|
|
|
/* high-band */
|
|
regs[R_EP5] = 0x83;
|
|
regs[R_CPD] = 0x98;
|
|
regs[R_CD1] = 0x65;
|
|
regs[R_CD2] = 0x00;
|
|
regs[R_MPD] = 0x99;
|
|
regs[R_MD1] = 0x71;
|
|
regs[R_MD2] = 0xcd;
|
|
|
|
__tda18271_write_regs(fe, R_EP3, 11, false);
|
|
msleep(5); /* pll locking */
|
|
|
|
/* launch detector */
|
|
__tda18271_write_regs(fe, R_EP1, 1, false);
|
|
msleep(5); /* wanted high measurement */
|
|
|
|
regs[R_EP5] = 0x87;
|
|
regs[R_CD1] = 0x65;
|
|
regs[R_CD2] = 0x50;
|
|
|
|
__tda18271_write_regs(fe, R_EP3, 7, false);
|
|
msleep(5); /* pll locking */
|
|
|
|
/* launch optimization algorithm */
|
|
__tda18271_write_regs(fe, R_EP2, 1, false);
|
|
msleep(30); /* image high optimization completion */
|
|
|
|
/* return to normal mode */
|
|
regs[R_EP4] = 0x64;
|
|
__tda18271_write_regs(fe, R_EP4, 1, false);
|
|
|
|
/* synchronize */
|
|
__tda18271_write_regs(fe, R_EP1, 1, false);
|
|
|
|
i2c_unlock_adapter(priv->i2c_props.adap);
|
|
tda18271_i2c_gate_ctrl(fe, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* Standby modes, EP3 [7:5]
|
|
*
|
|
* | SM || SM_LT || SM_XT || mode description
|
|
* |=====\\=======\\=======\\===================================
|
|
* | 0 || 0 || 0 || normal mode
|
|
* |-----||-------||-------||-----------------------------------
|
|
* | || || || standby mode w/ slave tuner output
|
|
* | 1 || 0 || 0 || & loop thru & xtal oscillator on
|
|
* |-----||-------||-------||-----------------------------------
|
|
* | 1 || 1 || 0 || standby mode w/ xtal oscillator on
|
|
* |-----||-------||-------||-----------------------------------
|
|
* | 1 || 1 || 1 || power off
|
|
*
|
|
*/
|
|
|
|
int tda18271_set_standby_mode(struct dvb_frontend *fe,
|
|
int sm, int sm_lt, int sm_xt)
|
|
{
|
|
struct tda18271_priv *priv = fe->tuner_priv;
|
|
unsigned char *regs = priv->tda18271_regs;
|
|
|
|
if (tda18271_debug & DBG_ADV)
|
|
tda_dbg("sm = %d, sm_lt = %d, sm_xt = %d\n", sm, sm_lt, sm_xt);
|
|
|
|
regs[R_EP3] &= ~0xe0; /* clear sm, sm_lt, sm_xt */
|
|
regs[R_EP3] |= (sm ? (1 << 7) : 0) |
|
|
(sm_lt ? (1 << 6) : 0) |
|
|
(sm_xt ? (1 << 5) : 0);
|
|
|
|
return tda18271_write_regs(fe, R_EP3, 1);
|
|
}
|
|
|
|
/*---------------------------------------------------------------------*/
|
|
|
|
int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq)
|
|
{
|
|
/* sets main post divider & divider bytes, but does not write them */
|
|
struct tda18271_priv *priv = fe->tuner_priv;
|
|
unsigned char *regs = priv->tda18271_regs;
|
|
u8 d, pd;
|
|
u32 div;
|
|
|
|
int ret = tda18271_lookup_pll_map(fe, MAIN_PLL, &freq, &pd, &d);
|
|
if (tda_fail(ret))
|
|
goto fail;
|
|
|
|
regs[R_MPD] = (0x7f & pd);
|
|
|
|
div = ((d * (freq / 1000)) << 7) / 125;
|
|
|
|
regs[R_MD1] = 0x7f & (div >> 16);
|
|
regs[R_MD2] = 0xff & (div >> 8);
|
|
regs[R_MD3] = 0xff & div;
|
|
fail:
|
|
return ret;
|
|
}
|
|
|
|
int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq)
|
|
{
|
|
/* sets cal post divider & divider bytes, but does not write them */
|
|
struct tda18271_priv *priv = fe->tuner_priv;
|
|
unsigned char *regs = priv->tda18271_regs;
|
|
u8 d, pd;
|
|
u32 div;
|
|
|
|
int ret = tda18271_lookup_pll_map(fe, CAL_PLL, &freq, &pd, &d);
|
|
if (tda_fail(ret))
|
|
goto fail;
|
|
|
|
regs[R_CPD] = pd;
|
|
|
|
div = ((d * (freq / 1000)) << 7) / 125;
|
|
|
|
regs[R_CD1] = 0x7f & (div >> 16);
|
|
regs[R_CD2] = 0xff & (div >> 8);
|
|
regs[R_CD3] = 0xff & div;
|
|
fail:
|
|
return ret;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------*/
|
|
|
|
int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq)
|
|
{
|
|
/* sets bp filter bits, but does not write them */
|
|
struct tda18271_priv *priv = fe->tuner_priv;
|
|
unsigned char *regs = priv->tda18271_regs;
|
|
u8 val;
|
|
|
|
int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val);
|
|
if (tda_fail(ret))
|
|
goto fail;
|
|
|
|
regs[R_EP1] &= ~0x07; /* clear bp filter bits */
|
|
regs[R_EP1] |= (0x07 & val);
|
|
fail:
|
|
return ret;
|
|
}
|
|
|
|
int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq)
|
|
{
|
|
/* sets K & M bits, but does not write them */
|
|
struct tda18271_priv *priv = fe->tuner_priv;
|
|
unsigned char *regs = priv->tda18271_regs;
|
|
u8 val;
|
|
|
|
int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val);
|
|
if (tda_fail(ret))
|
|
goto fail;
|
|
|
|
regs[R_EB13] &= ~0x7c; /* clear k & m bits */
|
|
regs[R_EB13] |= (0x7c & val);
|
|
fail:
|
|
return ret;
|
|
}
|
|
|
|
int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq)
|
|
{
|
|
/* sets rf band bits, but does not write them */
|
|
struct tda18271_priv *priv = fe->tuner_priv;
|
|
unsigned char *regs = priv->tda18271_regs;
|
|
u8 val;
|
|
|
|
int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val);
|
|
if (tda_fail(ret))
|
|
goto fail;
|
|
|
|
regs[R_EP2] &= ~0xe0; /* clear rf band bits */
|
|
regs[R_EP2] |= (0xe0 & (val << 5));
|
|
fail:
|
|
return ret;
|
|
}
|
|
|
|
int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq)
|
|
{
|
|
/* sets gain taper bits, but does not write them */
|
|
struct tda18271_priv *priv = fe->tuner_priv;
|
|
unsigned char *regs = priv->tda18271_regs;
|
|
u8 val;
|
|
|
|
int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val);
|
|
if (tda_fail(ret))
|
|
goto fail;
|
|
|
|
regs[R_EP2] &= ~0x1f; /* clear gain taper bits */
|
|
regs[R_EP2] |= (0x1f & val);
|
|
fail:
|
|
return ret;
|
|
}
|
|
|
|
int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq)
|
|
{
|
|
/* sets IR Meas bits, but does not write them */
|
|
struct tda18271_priv *priv = fe->tuner_priv;
|
|
unsigned char *regs = priv->tda18271_regs;
|
|
u8 val;
|
|
|
|
int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val);
|
|
if (tda_fail(ret))
|
|
goto fail;
|
|
|
|
regs[R_EP5] &= ~0x07;
|
|
regs[R_EP5] |= (0x07 & val);
|
|
fail:
|
|
return ret;
|
|
}
|
|
|
|
int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq)
|
|
{
|
|
/* sets rf cal byte (RFC_Cprog), but does not write it */
|
|
struct tda18271_priv *priv = fe->tuner_priv;
|
|
unsigned char *regs = priv->tda18271_regs;
|
|
u8 val;
|
|
|
|
int ret = tda18271_lookup_map(fe, RF_CAL, freq, &val);
|
|
/* The TDA18271HD/C1 rf_cal map lookup is expected to go out of range
|
|
* for frequencies above 61.1 MHz. In these cases, the internal RF
|
|
* tracking filters calibration mechanism is used.
|
|
*
|
|
* There is no need to warn the user about this.
|
|
*/
|
|
if (ret < 0)
|
|
goto fail;
|
|
|
|
regs[R_EB14] = val;
|
|
fail:
|
|
return ret;
|
|
}
|
|
|
|
void _tda_printk(struct tda18271_priv *state, const char *level,
|
|
const char *func, const char *fmt, ...)
|
|
{
|
|
struct va_format vaf;
|
|
va_list args;
|
|
|
|
va_start(args, fmt);
|
|
|
|
vaf.fmt = fmt;
|
|
vaf.va = &args;
|
|
|
|
if (state)
|
|
printk("%s%s: [%d-%04x|%c] %pV",
|
|
level, func, i2c_adapter_id(state->i2c_props.adap),
|
|
state->i2c_props.addr,
|
|
(state->role == TDA18271_MASTER) ? 'M' : 'S',
|
|
&vaf);
|
|
else
|
|
printk("%s%s: %pV", level, func, &vaf);
|
|
|
|
va_end(args);
|
|
}
|