610 lines
15 KiB
C
610 lines
15 KiB
C
/*
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driver for LSI L64781 COFDM demodulator
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Copyright (C) 2001 Holger Waechtler for Convergence Integrated Media GmbH
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Marko Kohtala <marko.kohtala@luukku.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include "dvb_frontend.h"
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#include "l64781.h"
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struct l64781_state {
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struct i2c_adapter* i2c;
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const struct l64781_config* config;
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struct dvb_frontend frontend;
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/* private demodulator data */
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unsigned int first:1;
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};
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#define dprintk(args...) \
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do { \
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if (debug) printk(KERN_DEBUG "l64781: " args); \
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} while (0)
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static int debug;
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module_param(debug, int, 0644);
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MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
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static int l64781_writereg (struct l64781_state* state, u8 reg, u8 data)
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{
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int ret;
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u8 buf [] = { reg, data };
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struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
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if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1)
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dprintk ("%s: write_reg error (reg == %02x) = %02x!\n",
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__func__, reg, ret);
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return (ret != 1) ? -1 : 0;
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}
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static int l64781_readreg (struct l64781_state* state, u8 reg)
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{
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int ret;
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u8 b0 [] = { reg };
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u8 b1 [] = { 0 };
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struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
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{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2) return ret;
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return b1[0];
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}
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static void apply_tps (struct l64781_state* state)
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{
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l64781_writereg (state, 0x2a, 0x00);
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l64781_writereg (state, 0x2a, 0x01);
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/* This here is a little bit questionable because it enables
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the automatic update of TPS registers. I think we'd need to
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handle the IRQ from FE to update some other registers as
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well, or at least implement some magic to tuning to correct
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to the TPS received from transmission. */
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l64781_writereg (state, 0x2a, 0x02);
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}
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static void reset_afc (struct l64781_state* state)
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{
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/* Set AFC stall for the AFC_INIT_FRQ setting, TIM_STALL for
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timing offset */
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l64781_writereg (state, 0x07, 0x9e); /* stall AFC */
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l64781_writereg (state, 0x08, 0); /* AFC INIT FREQ */
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l64781_writereg (state, 0x09, 0);
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l64781_writereg (state, 0x0a, 0);
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l64781_writereg (state, 0x07, 0x8e);
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l64781_writereg (state, 0x0e, 0); /* AGC gain to zero in beginning */
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l64781_writereg (state, 0x11, 0x80); /* stall TIM */
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l64781_writereg (state, 0x10, 0); /* TIM_OFFSET_LSB */
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l64781_writereg (state, 0x12, 0);
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l64781_writereg (state, 0x13, 0);
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l64781_writereg (state, 0x11, 0x00);
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}
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static int reset_and_configure (struct l64781_state* state)
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{
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u8 buf [] = { 0x06 };
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struct i2c_msg msg = { .addr = 0x00, .flags = 0, .buf = buf, .len = 1 };
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// NOTE: this is correct in writing to address 0x00
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return (i2c_transfer(state->i2c, &msg, 1) == 1) ? 0 : -ENODEV;
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}
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static int apply_frontend_param(struct dvb_frontend *fe)
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{
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struct dtv_frontend_properties *p = &fe->dtv_property_cache;
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struct l64781_state* state = fe->demodulator_priv;
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/* The coderates for FEC_NONE, FEC_4_5 and FEC_FEC_6_7 are arbitrary */
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static const u8 fec_tab[] = { 7, 0, 1, 2, 9, 3, 10, 4 };
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/* QPSK, QAM_16, QAM_64 */
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static const u8 qam_tab [] = { 2, 4, 0, 6 };
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static const u8 guard_tab [] = { 1, 2, 4, 8 };
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/* The Grundig 29504-401.04 Tuner comes with 18.432MHz crystal. */
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static const u32 ppm = 8000;
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u32 ddfs_offset_fixed;
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/* u32 ddfs_offset_variable = 0x6000-((1000000UL+ppm)/ */
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/* bw_tab[p->bandWidth]<<10)/15625; */
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u32 init_freq;
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u32 spi_bias;
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u8 val0x04;
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u8 val0x05;
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u8 val0x06;
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int bw;
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switch (p->bandwidth_hz) {
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case 8000000:
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bw = 8;
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break;
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case 7000000:
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bw = 7;
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break;
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case 6000000:
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bw = 6;
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break;
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default:
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return -EINVAL;
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}
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if (fe->ops.tuner_ops.set_params) {
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fe->ops.tuner_ops.set_params(fe);
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if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
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}
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if (p->inversion != INVERSION_ON &&
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p->inversion != INVERSION_OFF)
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return -EINVAL;
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if (p->code_rate_HP != FEC_1_2 && p->code_rate_HP != FEC_2_3 &&
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p->code_rate_HP != FEC_3_4 && p->code_rate_HP != FEC_5_6 &&
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p->code_rate_HP != FEC_7_8)
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return -EINVAL;
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if (p->hierarchy != HIERARCHY_NONE &&
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(p->code_rate_LP != FEC_1_2 && p->code_rate_LP != FEC_2_3 &&
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p->code_rate_LP != FEC_3_4 && p->code_rate_LP != FEC_5_6 &&
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p->code_rate_LP != FEC_7_8))
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return -EINVAL;
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if (p->modulation != QPSK && p->modulation != QAM_16 &&
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p->modulation != QAM_64)
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return -EINVAL;
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if (p->transmission_mode != TRANSMISSION_MODE_2K &&
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p->transmission_mode != TRANSMISSION_MODE_8K)
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return -EINVAL;
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if ((int)p->guard_interval < GUARD_INTERVAL_1_32 ||
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p->guard_interval > GUARD_INTERVAL_1_4)
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return -EINVAL;
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if ((int)p->hierarchy < HIERARCHY_NONE ||
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p->hierarchy > HIERARCHY_4)
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return -EINVAL;
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ddfs_offset_fixed = 0x4000-(ppm<<16)/bw/1000000;
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/* This works up to 20000 ppm, it overflows if too large ppm! */
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init_freq = (((8UL<<25) + (8UL<<19) / 25*ppm / (15625/25)) /
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bw & 0xFFFFFF);
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/* SPI bias calculation is slightly modified to fit in 32bit */
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/* will work for high ppm only... */
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spi_bias = 378 * (1 << 10);
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spi_bias *= 16;
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spi_bias *= bw;
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spi_bias *= qam_tab[p->modulation];
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spi_bias /= p->code_rate_HP + 1;
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spi_bias /= (guard_tab[p->guard_interval] + 32);
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spi_bias *= 1000;
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spi_bias /= 1000 + ppm/1000;
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spi_bias *= p->code_rate_HP;
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val0x04 = (p->transmission_mode << 2) | p->guard_interval;
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val0x05 = fec_tab[p->code_rate_HP];
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if (p->hierarchy != HIERARCHY_NONE)
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val0x05 |= (p->code_rate_LP - FEC_1_2) << 3;
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val0x06 = (p->hierarchy << 2) | p->modulation;
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l64781_writereg (state, 0x04, val0x04);
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l64781_writereg (state, 0x05, val0x05);
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l64781_writereg (state, 0x06, val0x06);
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reset_afc (state);
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/* Technical manual section 2.6.1, TIM_IIR_GAIN optimal values */
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l64781_writereg (state, 0x15,
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p->transmission_mode == TRANSMISSION_MODE_2K ? 1 : 3);
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l64781_writereg (state, 0x16, init_freq & 0xff);
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l64781_writereg (state, 0x17, (init_freq >> 8) & 0xff);
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l64781_writereg (state, 0x18, (init_freq >> 16) & 0xff);
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l64781_writereg (state, 0x1b, spi_bias & 0xff);
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l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff);
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l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) |
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(p->inversion == INVERSION_ON ? 0x80 : 0x00));
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l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff);
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l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f);
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l64781_readreg (state, 0x00); /* clear interrupt registers... */
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l64781_readreg (state, 0x01); /* dto. */
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apply_tps (state);
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return 0;
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}
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static int get_frontend(struct dvb_frontend *fe,
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struct dtv_frontend_properties *p)
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{
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struct l64781_state* state = fe->demodulator_priv;
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int tmp;
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tmp = l64781_readreg(state, 0x04);
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switch(tmp & 3) {
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case 0:
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p->guard_interval = GUARD_INTERVAL_1_32;
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break;
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case 1:
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p->guard_interval = GUARD_INTERVAL_1_16;
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break;
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case 2:
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p->guard_interval = GUARD_INTERVAL_1_8;
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break;
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case 3:
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p->guard_interval = GUARD_INTERVAL_1_4;
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break;
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}
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switch((tmp >> 2) & 3) {
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case 0:
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p->transmission_mode = TRANSMISSION_MODE_2K;
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break;
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case 1:
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p->transmission_mode = TRANSMISSION_MODE_8K;
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break;
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default:
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printk(KERN_WARNING "Unexpected value for transmission_mode\n");
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}
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tmp = l64781_readreg(state, 0x05);
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switch(tmp & 7) {
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case 0:
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p->code_rate_HP = FEC_1_2;
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break;
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case 1:
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p->code_rate_HP = FEC_2_3;
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break;
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case 2:
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p->code_rate_HP = FEC_3_4;
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break;
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case 3:
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p->code_rate_HP = FEC_5_6;
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break;
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case 4:
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p->code_rate_HP = FEC_7_8;
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break;
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default:
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printk("Unexpected value for code_rate_HP\n");
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}
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switch((tmp >> 3) & 7) {
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case 0:
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p->code_rate_LP = FEC_1_2;
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break;
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case 1:
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p->code_rate_LP = FEC_2_3;
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break;
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case 2:
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p->code_rate_LP = FEC_3_4;
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break;
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case 3:
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p->code_rate_LP = FEC_5_6;
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break;
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case 4:
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p->code_rate_LP = FEC_7_8;
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break;
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default:
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printk("Unexpected value for code_rate_LP\n");
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}
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tmp = l64781_readreg(state, 0x06);
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switch(tmp & 3) {
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case 0:
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p->modulation = QPSK;
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break;
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case 1:
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p->modulation = QAM_16;
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break;
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case 2:
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p->modulation = QAM_64;
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break;
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default:
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printk(KERN_WARNING "Unexpected value for modulation\n");
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}
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switch((tmp >> 2) & 7) {
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case 0:
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p->hierarchy = HIERARCHY_NONE;
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break;
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case 1:
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p->hierarchy = HIERARCHY_1;
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break;
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case 2:
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p->hierarchy = HIERARCHY_2;
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break;
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case 3:
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p->hierarchy = HIERARCHY_4;
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break;
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default:
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printk("Unexpected value for hierarchy\n");
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}
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tmp = l64781_readreg (state, 0x1d);
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p->inversion = (tmp & 0x80) ? INVERSION_ON : INVERSION_OFF;
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tmp = (int) (l64781_readreg (state, 0x08) |
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(l64781_readreg (state, 0x09) << 8) |
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(l64781_readreg (state, 0x0a) << 16));
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p->frequency += tmp;
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return 0;
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}
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static int l64781_read_status(struct dvb_frontend *fe, enum fe_status *status)
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{
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struct l64781_state* state = fe->demodulator_priv;
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int sync = l64781_readreg (state, 0x32);
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int gain = l64781_readreg (state, 0x0e);
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l64781_readreg (state, 0x00); /* clear interrupt registers... */
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l64781_readreg (state, 0x01); /* dto. */
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*status = 0;
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if (gain > 5)
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*status |= FE_HAS_SIGNAL;
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if (sync & 0x02) /* VCXO locked, this criteria should be ok */
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*status |= FE_HAS_CARRIER;
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if (sync & 0x20)
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*status |= FE_HAS_VITERBI;
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if (sync & 0x40)
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*status |= FE_HAS_SYNC;
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if (sync == 0x7f)
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*status |= FE_HAS_LOCK;
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return 0;
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}
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static int l64781_read_ber(struct dvb_frontend* fe, u32* ber)
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{
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struct l64781_state* state = fe->demodulator_priv;
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/* XXX FIXME: set up counting period (reg 0x26...0x28)
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*/
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*ber = l64781_readreg (state, 0x39)
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| (l64781_readreg (state, 0x3a) << 8);
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return 0;
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}
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static int l64781_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
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{
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struct l64781_state* state = fe->demodulator_priv;
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u8 gain = l64781_readreg (state, 0x0e);
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*signal_strength = (gain << 8) | gain;
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return 0;
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}
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static int l64781_read_snr(struct dvb_frontend* fe, u16* snr)
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{
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struct l64781_state* state = fe->demodulator_priv;
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u8 avg_quality = 0xff - l64781_readreg (state, 0x33);
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*snr = (avg_quality << 8) | avg_quality; /* not exact, but...*/
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return 0;
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}
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static int l64781_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
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{
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struct l64781_state* state = fe->demodulator_priv;
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*ucblocks = l64781_readreg (state, 0x37)
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| (l64781_readreg (state, 0x38) << 8);
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return 0;
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}
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static int l64781_sleep(struct dvb_frontend* fe)
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{
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struct l64781_state* state = fe->demodulator_priv;
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/* Power down */
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return l64781_writereg (state, 0x3e, 0x5a);
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}
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static int l64781_init(struct dvb_frontend* fe)
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{
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struct l64781_state* state = fe->demodulator_priv;
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reset_and_configure (state);
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/* Power up */
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l64781_writereg (state, 0x3e, 0xa5);
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/* Reset hard */
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l64781_writereg (state, 0x2a, 0x04);
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l64781_writereg (state, 0x2a, 0x00);
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/* Set tuner specific things */
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/* AFC_POL, set also in reset_afc */
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l64781_writereg (state, 0x07, 0x8e);
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/* Use internal ADC */
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l64781_writereg (state, 0x0b, 0x81);
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/* AGC loop gain, and polarity is positive */
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l64781_writereg (state, 0x0c, 0x84);
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/* Internal ADC outputs two's complement */
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l64781_writereg (state, 0x0d, 0x8c);
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/* With ppm=8000, it seems the DTR_SENSITIVITY will result in
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value of 2 with all possible bandwidths and guard
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intervals, which is the initial value anyway. */
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/*l64781_writereg (state, 0x19, 0x92);*/
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/* Everything is two's complement, soft bit and CSI_OUT too */
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l64781_writereg (state, 0x1e, 0x09);
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/* delay a bit after first init attempt */
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if (state->first) {
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state->first = 0;
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msleep(200);
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}
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return 0;
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}
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static int l64781_get_tune_settings(struct dvb_frontend* fe,
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struct dvb_frontend_tune_settings* fesettings)
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{
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fesettings->min_delay_ms = 4000;
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fesettings->step_size = 0;
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fesettings->max_drift = 0;
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return 0;
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}
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static void l64781_release(struct dvb_frontend* fe)
|
|
{
|
|
struct l64781_state* state = fe->demodulator_priv;
|
|
kfree(state);
|
|
}
|
|
|
|
static const struct dvb_frontend_ops l64781_ops;
|
|
|
|
struct dvb_frontend* l64781_attach(const struct l64781_config* config,
|
|
struct i2c_adapter* i2c)
|
|
{
|
|
struct l64781_state* state = NULL;
|
|
int reg0x3e = -1;
|
|
u8 b0 [] = { 0x1a };
|
|
u8 b1 [] = { 0x00 };
|
|
struct i2c_msg msg [] = { { .addr = config->demod_address, .flags = 0, .buf = b0, .len = 1 },
|
|
{ .addr = config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
|
|
|
|
/* allocate memory for the internal state */
|
|
state = kzalloc(sizeof(struct l64781_state), GFP_KERNEL);
|
|
if (state == NULL) goto error;
|
|
|
|
/* setup the state */
|
|
state->config = config;
|
|
state->i2c = i2c;
|
|
state->first = 1;
|
|
|
|
/*
|
|
* the L64781 won't show up before we send the reset_and_configure()
|
|
* broadcast. If nothing responds there is no L64781 on the bus...
|
|
*/
|
|
if (reset_and_configure(state) < 0) {
|
|
dprintk("No response to reset and configure broadcast...\n");
|
|
goto error;
|
|
}
|
|
|
|
/* The chip always responds to reads */
|
|
if (i2c_transfer(state->i2c, msg, 2) != 2) {
|
|
dprintk("No response to read on I2C bus\n");
|
|
goto error;
|
|
}
|
|
|
|
/* Save current register contents for bailout */
|
|
reg0x3e = l64781_readreg(state, 0x3e);
|
|
|
|
/* Reading the POWER_DOWN register always returns 0 */
|
|
if (reg0x3e != 0) {
|
|
dprintk("Device doesn't look like L64781\n");
|
|
goto error;
|
|
}
|
|
|
|
/* Turn the chip off */
|
|
l64781_writereg (state, 0x3e, 0x5a);
|
|
|
|
/* Responds to all reads with 0 */
|
|
if (l64781_readreg(state, 0x1a) != 0) {
|
|
dprintk("Read 1 returned unexpcted value\n");
|
|
goto error;
|
|
}
|
|
|
|
/* Turn the chip on */
|
|
l64781_writereg (state, 0x3e, 0xa5);
|
|
|
|
/* Responds with register default value */
|
|
if (l64781_readreg(state, 0x1a) != 0xa1) {
|
|
dprintk("Read 2 returned unexpcted value\n");
|
|
goto error;
|
|
}
|
|
|
|
/* create dvb_frontend */
|
|
memcpy(&state->frontend.ops, &l64781_ops, sizeof(struct dvb_frontend_ops));
|
|
state->frontend.demodulator_priv = state;
|
|
return &state->frontend;
|
|
|
|
error:
|
|
if (reg0x3e >= 0)
|
|
l64781_writereg (state, 0x3e, reg0x3e); /* restore reg 0x3e */
|
|
kfree(state);
|
|
return NULL;
|
|
}
|
|
|
|
static const struct dvb_frontend_ops l64781_ops = {
|
|
.delsys = { SYS_DVBT },
|
|
.info = {
|
|
.name = "LSI L64781 DVB-T",
|
|
/* .frequency_min = ???,*/
|
|
/* .frequency_max = ???,*/
|
|
.frequency_stepsize = 166666,
|
|
/* .frequency_tolerance = ???,*/
|
|
/* .symbol_rate_tolerance = ???,*/
|
|
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
|
|
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
|
|
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
|
|
FE_CAN_MUTE_TS
|
|
},
|
|
|
|
.release = l64781_release,
|
|
|
|
.init = l64781_init,
|
|
.sleep = l64781_sleep,
|
|
|
|
.set_frontend = apply_frontend_param,
|
|
.get_frontend = get_frontend,
|
|
.get_tune_settings = l64781_get_tune_settings,
|
|
|
|
.read_status = l64781_read_status,
|
|
.read_ber = l64781_read_ber,
|
|
.read_signal_strength = l64781_read_signal_strength,
|
|
.read_snr = l64781_read_snr,
|
|
.read_ucblocks = l64781_read_ucblocks,
|
|
};
|
|
|
|
MODULE_DESCRIPTION("LSI L64781 DVB-T Demodulator driver");
|
|
MODULE_AUTHOR("Holger Waechtler, Marko Kohtala");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
EXPORT_SYMBOL(l64781_attach);
|