430 lines
10 KiB
C
430 lines
10 KiB
C
/*
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* Copyright (c) 2016-2017 Lucas Stach, Pengutronix
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <drm/drm_fourcc.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/iopoll.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <video/imx-ipu-v3.h>
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#include "ipu-prv.h"
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#define IPU_PRG_CTL 0x00
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#define IPU_PRG_CTL_BYPASS(i) (1 << (0 + i))
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#define IPU_PRG_CTL_SOFT_ARID_MASK 0x3
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#define IPU_PRG_CTL_SOFT_ARID_SHIFT(i) (8 + i * 2)
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#define IPU_PRG_CTL_SOFT_ARID(i, v) ((v & 0x3) << (8 + 2 * i))
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#define IPU_PRG_CTL_SO(i) (1 << (16 + i))
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#define IPU_PRG_CTL_VFLIP(i) (1 << (19 + i))
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#define IPU_PRG_CTL_BLOCK_MODE(i) (1 << (22 + i))
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#define IPU_PRG_CTL_CNT_LOAD_EN(i) (1 << (25 + i))
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#define IPU_PRG_CTL_SOFTRST (1 << 30)
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#define IPU_PRG_CTL_SHADOW_EN (1 << 31)
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#define IPU_PRG_STATUS 0x04
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#define IPU_PRG_STATUS_BUFFER0_READY(i) (1 << (0 + i * 2))
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#define IPU_PRG_STATUS_BUFFER1_READY(i) (1 << (1 + i * 2))
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#define IPU_PRG_QOS 0x08
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#define IPU_PRG_QOS_ARID_MASK 0xf
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#define IPU_PRG_QOS_ARID_SHIFT(i) (0 + i * 4)
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#define IPU_PRG_REG_UPDATE 0x0c
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#define IPU_PRG_REG_UPDATE_REG_UPDATE (1 << 0)
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#define IPU_PRG_STRIDE(i) (0x10 + i * 0x4)
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#define IPU_PRG_STRIDE_STRIDE_MASK 0x3fff
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#define IPU_PRG_CROP_LINE 0x1c
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#define IPU_PRG_THD 0x20
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#define IPU_PRG_BADDR(i) (0x24 + i * 0x4)
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#define IPU_PRG_OFFSET(i) (0x30 + i * 0x4)
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#define IPU_PRG_ILO(i) (0x3c + i * 0x4)
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#define IPU_PRG_HEIGHT(i) (0x48 + i * 0x4)
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#define IPU_PRG_HEIGHT_PRE_HEIGHT_MASK 0xfff
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#define IPU_PRG_HEIGHT_PRE_HEIGHT_SHIFT 0
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#define IPU_PRG_HEIGHT_IPU_HEIGHT_MASK 0xfff
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#define IPU_PRG_HEIGHT_IPU_HEIGHT_SHIFT 16
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struct ipu_prg_channel {
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bool enabled;
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int used_pre;
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};
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struct ipu_prg {
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struct list_head list;
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struct device *dev;
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int id;
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void __iomem *regs;
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struct clk *clk_ipg, *clk_axi;
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struct regmap *iomuxc_gpr;
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struct ipu_pre *pres[3];
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struct ipu_prg_channel chan[3];
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};
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static DEFINE_MUTEX(ipu_prg_list_mutex);
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static LIST_HEAD(ipu_prg_list);
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struct ipu_prg *
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ipu_prg_lookup_by_phandle(struct device *dev, const char *name, int ipu_id)
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{
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struct device_node *prg_node = of_parse_phandle(dev->of_node,
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name, 0);
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struct ipu_prg *prg;
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mutex_lock(&ipu_prg_list_mutex);
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list_for_each_entry(prg, &ipu_prg_list, list) {
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if (prg_node == prg->dev->of_node) {
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mutex_unlock(&ipu_prg_list_mutex);
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device_link_add(dev, prg->dev, DL_FLAG_AUTOREMOVE);
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prg->id = ipu_id;
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return prg;
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}
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}
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mutex_unlock(&ipu_prg_list_mutex);
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return NULL;
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}
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int ipu_prg_max_active_channels(void)
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{
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return ipu_pre_get_available_count();
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}
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EXPORT_SYMBOL_GPL(ipu_prg_max_active_channels);
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bool ipu_prg_present(struct ipu_soc *ipu)
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{
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if (ipu->prg_priv)
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return true;
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return false;
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}
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EXPORT_SYMBOL_GPL(ipu_prg_present);
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bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format,
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uint64_t modifier)
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{
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const struct drm_format_info *info = drm_format_info(format);
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if (info->num_planes != 1)
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return false;
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return true;
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}
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EXPORT_SYMBOL_GPL(ipu_prg_format_supported);
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int ipu_prg_enable(struct ipu_soc *ipu)
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{
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struct ipu_prg *prg = ipu->prg_priv;
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int ret;
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if (!prg)
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return 0;
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ret = clk_prepare_enable(prg->clk_axi);
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if (ret)
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goto fail_disable_ipg;
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return 0;
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fail_disable_ipg:
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clk_disable_unprepare(prg->clk_ipg);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ipu_prg_enable);
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void ipu_prg_disable(struct ipu_soc *ipu)
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{
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struct ipu_prg *prg = ipu->prg_priv;
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if (!prg)
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return;
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clk_disable_unprepare(prg->clk_axi);
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}
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EXPORT_SYMBOL_GPL(ipu_prg_disable);
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/*
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* The channel configuartion functions below are not thread safe, as they
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* must be only called from the atomic commit path in the DRM driver, which
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* is properly serialized.
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*/
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static int ipu_prg_ipu_to_prg_chan(int ipu_chan)
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{
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/*
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* This isn't clearly documented in the RM, but IPU to PRG channel
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* assignment is fixed, as only with this mapping the control signals
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* match up.
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*/
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switch (ipu_chan) {
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case IPUV3_CHANNEL_MEM_BG_SYNC:
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return 0;
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case IPUV3_CHANNEL_MEM_FG_SYNC:
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return 1;
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case IPUV3_CHANNEL_MEM_DC_SYNC:
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return 2;
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default:
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return -EINVAL;
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}
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}
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static int ipu_prg_get_pre(struct ipu_prg *prg, int prg_chan)
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{
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int i, ret;
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/* channel 0 is special as it is hardwired to one of the PREs */
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if (prg_chan == 0) {
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ret = ipu_pre_get(prg->pres[0]);
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if (ret)
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goto fail;
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prg->chan[prg_chan].used_pre = 0;
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return 0;
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}
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for (i = 1; i < 3; i++) {
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ret = ipu_pre_get(prg->pres[i]);
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if (!ret) {
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u32 val, mux;
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int shift;
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prg->chan[prg_chan].used_pre = i;
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/* configure the PRE to PRG channel mux */
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shift = (i == 1) ? 12 : 14;
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mux = (prg->id << 1) | (prg_chan - 1);
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regmap_update_bits(prg->iomuxc_gpr, IOMUXC_GPR5,
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0x3 << shift, mux << shift);
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/* check other mux, must not point to same channel */
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shift = (i == 1) ? 14 : 12;
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regmap_read(prg->iomuxc_gpr, IOMUXC_GPR5, &val);
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if (((val >> shift) & 0x3) == mux) {
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regmap_update_bits(prg->iomuxc_gpr, IOMUXC_GPR5,
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0x3 << shift,
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(mux ^ 0x1) << shift);
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}
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return 0;
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}
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}
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fail:
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dev_err(prg->dev, "could not get PRE for PRG chan %d", prg_chan);
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return ret;
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}
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static void ipu_prg_put_pre(struct ipu_prg *prg, int prg_chan)
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{
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struct ipu_prg_channel *chan = &prg->chan[prg_chan];
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ipu_pre_put(prg->pres[chan->used_pre]);
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chan->used_pre = -1;
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}
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void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan)
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{
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int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
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struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
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struct ipu_prg_channel *chan = &prg->chan[prg_chan];
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u32 val;
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if (!chan->enabled || prg_chan < 0)
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return;
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clk_prepare_enable(prg->clk_ipg);
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val = readl(prg->regs + IPU_PRG_CTL);
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val |= IPU_PRG_CTL_BYPASS(prg_chan);
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writel(val, prg->regs + IPU_PRG_CTL);
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val = IPU_PRG_REG_UPDATE_REG_UPDATE;
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writel(val, prg->regs + IPU_PRG_REG_UPDATE);
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clk_disable_unprepare(prg->clk_ipg);
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ipu_prg_put_pre(prg, prg_chan);
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chan->enabled = false;
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}
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EXPORT_SYMBOL_GPL(ipu_prg_channel_disable);
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int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
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unsigned int axi_id, unsigned int width,
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unsigned int height, unsigned int stride,
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u32 format, unsigned long *eba)
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{
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int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
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struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
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struct ipu_prg_channel *chan = &prg->chan[prg_chan];
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u32 val;
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int ret;
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if (prg_chan < 0)
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return prg_chan;
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if (chan->enabled) {
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ipu_pre_update(prg->pres[chan->used_pre], *eba);
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return 0;
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}
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ret = ipu_prg_get_pre(prg, prg_chan);
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if (ret)
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return ret;
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ipu_pre_configure(prg->pres[chan->used_pre],
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width, height, stride, format, *eba);
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ret = clk_prepare_enable(prg->clk_ipg);
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if (ret) {
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ipu_prg_put_pre(prg, prg_chan);
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return ret;
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}
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val = (stride - 1) & IPU_PRG_STRIDE_STRIDE_MASK;
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writel(val, prg->regs + IPU_PRG_STRIDE(prg_chan));
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val = ((height & IPU_PRG_HEIGHT_PRE_HEIGHT_MASK) <<
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IPU_PRG_HEIGHT_PRE_HEIGHT_SHIFT) |
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((height & IPU_PRG_HEIGHT_IPU_HEIGHT_MASK) <<
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IPU_PRG_HEIGHT_IPU_HEIGHT_SHIFT);
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writel(val, prg->regs + IPU_PRG_HEIGHT(prg_chan));
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val = ipu_pre_get_baddr(prg->pres[chan->used_pre]);
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*eba = val;
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writel(val, prg->regs + IPU_PRG_BADDR(prg_chan));
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val = readl(prg->regs + IPU_PRG_CTL);
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/* config AXI ID */
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val &= ~(IPU_PRG_CTL_SOFT_ARID_MASK <<
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IPU_PRG_CTL_SOFT_ARID_SHIFT(prg_chan));
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val |= IPU_PRG_CTL_SOFT_ARID(prg_chan, axi_id);
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/* enable channel */
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val &= ~IPU_PRG_CTL_BYPASS(prg_chan);
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writel(val, prg->regs + IPU_PRG_CTL);
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val = IPU_PRG_REG_UPDATE_REG_UPDATE;
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writel(val, prg->regs + IPU_PRG_REG_UPDATE);
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/* wait for both double buffers to be filled */
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readl_poll_timeout(prg->regs + IPU_PRG_STATUS, val,
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(val & IPU_PRG_STATUS_BUFFER0_READY(prg_chan)) &&
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(val & IPU_PRG_STATUS_BUFFER1_READY(prg_chan)),
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5, 1000);
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clk_disable_unprepare(prg->clk_ipg);
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chan->enabled = true;
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_prg_channel_configure);
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static int ipu_prg_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *res;
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struct ipu_prg *prg;
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u32 val;
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int i, ret;
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prg = devm_kzalloc(dev, sizeof(*prg), GFP_KERNEL);
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if (!prg)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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prg->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(prg->regs))
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return PTR_ERR(prg->regs);
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prg->clk_ipg = devm_clk_get(dev, "ipg");
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if (IS_ERR(prg->clk_ipg))
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return PTR_ERR(prg->clk_ipg);
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prg->clk_axi = devm_clk_get(dev, "axi");
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if (IS_ERR(prg->clk_axi))
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return PTR_ERR(prg->clk_axi);
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prg->iomuxc_gpr =
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syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
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if (IS_ERR(prg->iomuxc_gpr))
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return PTR_ERR(prg->iomuxc_gpr);
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for (i = 0; i < 3; i++) {
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prg->pres[i] = ipu_pre_lookup_by_phandle(dev, "fsl,pres", i);
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if (!prg->pres[i])
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return -EPROBE_DEFER;
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}
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ret = clk_prepare_enable(prg->clk_ipg);
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if (ret)
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return ret;
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/* init to free running mode */
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val = readl(prg->regs + IPU_PRG_CTL);
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val |= IPU_PRG_CTL_SHADOW_EN;
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writel(val, prg->regs + IPU_PRG_CTL);
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/* disable address threshold */
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writel(0xffffffff, prg->regs + IPU_PRG_THD);
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clk_disable_unprepare(prg->clk_ipg);
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prg->dev = dev;
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platform_set_drvdata(pdev, prg);
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mutex_lock(&ipu_prg_list_mutex);
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list_add(&prg->list, &ipu_prg_list);
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mutex_unlock(&ipu_prg_list_mutex);
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return 0;
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}
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static int ipu_prg_remove(struct platform_device *pdev)
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{
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struct ipu_prg *prg = platform_get_drvdata(pdev);
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mutex_lock(&ipu_prg_list_mutex);
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list_del(&prg->list);
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mutex_unlock(&ipu_prg_list_mutex);
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return 0;
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}
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static const struct of_device_id ipu_prg_dt_ids[] = {
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{ .compatible = "fsl,imx6qp-prg", },
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{ /* sentinel */ },
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};
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struct platform_driver ipu_prg_drv = {
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.probe = ipu_prg_probe,
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.remove = ipu_prg_remove,
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.driver = {
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.name = "imx-ipu-prg",
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.of_match_table = ipu_prg_dt_ids,
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},
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};
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