801 lines
20 KiB
C
801 lines
20 KiB
C
/*
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* Copyright (C) 2012-2014 Mentor Graphics Inc.
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* Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/spinlock.h>
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#include <linux/bitrev.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include "ipu-prv.h"
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/* IC Register Offsets */
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#define IC_CONF 0x0000
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#define IC_PRP_ENC_RSC 0x0004
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#define IC_PRP_VF_RSC 0x0008
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#define IC_PP_RSC 0x000C
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#define IC_CMBP_1 0x0010
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#define IC_CMBP_2 0x0014
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#define IC_IDMAC_1 0x0018
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#define IC_IDMAC_2 0x001C
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#define IC_IDMAC_3 0x0020
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#define IC_IDMAC_4 0x0024
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/* IC Register Fields */
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#define IC_CONF_PRPENC_EN (1 << 0)
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#define IC_CONF_PRPENC_CSC1 (1 << 1)
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#define IC_CONF_PRPENC_ROT_EN (1 << 2)
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#define IC_CONF_PRPVF_EN (1 << 8)
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#define IC_CONF_PRPVF_CSC1 (1 << 9)
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#define IC_CONF_PRPVF_CSC2 (1 << 10)
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#define IC_CONF_PRPVF_CMB (1 << 11)
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#define IC_CONF_PRPVF_ROT_EN (1 << 12)
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#define IC_CONF_PP_EN (1 << 16)
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#define IC_CONF_PP_CSC1 (1 << 17)
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#define IC_CONF_PP_CSC2 (1 << 18)
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#define IC_CONF_PP_CMB (1 << 19)
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#define IC_CONF_PP_ROT_EN (1 << 20)
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#define IC_CONF_IC_GLB_LOC_A (1 << 28)
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#define IC_CONF_KEY_COLOR_EN (1 << 29)
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#define IC_CONF_RWS_EN (1 << 30)
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#define IC_CONF_CSI_MEM_WR_EN (1 << 31)
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#define IC_IDMAC_1_CB0_BURST_16 (1 << 0)
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#define IC_IDMAC_1_CB1_BURST_16 (1 << 1)
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#define IC_IDMAC_1_CB2_BURST_16 (1 << 2)
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#define IC_IDMAC_1_CB3_BURST_16 (1 << 3)
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#define IC_IDMAC_1_CB4_BURST_16 (1 << 4)
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#define IC_IDMAC_1_CB5_BURST_16 (1 << 5)
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#define IC_IDMAC_1_CB6_BURST_16 (1 << 6)
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#define IC_IDMAC_1_CB7_BURST_16 (1 << 7)
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#define IC_IDMAC_1_PRPENC_ROT_MASK (0x7 << 11)
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#define IC_IDMAC_1_PRPENC_ROT_OFFSET 11
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#define IC_IDMAC_1_PRPVF_ROT_MASK (0x7 << 14)
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#define IC_IDMAC_1_PRPVF_ROT_OFFSET 14
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#define IC_IDMAC_1_PP_ROT_MASK (0x7 << 17)
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#define IC_IDMAC_1_PP_ROT_OFFSET 17
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#define IC_IDMAC_1_PP_FLIP_RS (1 << 22)
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#define IC_IDMAC_1_PRPVF_FLIP_RS (1 << 21)
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#define IC_IDMAC_1_PRPENC_FLIP_RS (1 << 20)
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#define IC_IDMAC_2_PRPENC_HEIGHT_MASK (0x3ff << 0)
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#define IC_IDMAC_2_PRPENC_HEIGHT_OFFSET 0
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#define IC_IDMAC_2_PRPVF_HEIGHT_MASK (0x3ff << 10)
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#define IC_IDMAC_2_PRPVF_HEIGHT_OFFSET 10
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#define IC_IDMAC_2_PP_HEIGHT_MASK (0x3ff << 20)
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#define IC_IDMAC_2_PP_HEIGHT_OFFSET 20
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#define IC_IDMAC_3_PRPENC_WIDTH_MASK (0x3ff << 0)
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#define IC_IDMAC_3_PRPENC_WIDTH_OFFSET 0
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#define IC_IDMAC_3_PRPVF_WIDTH_MASK (0x3ff << 10)
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#define IC_IDMAC_3_PRPVF_WIDTH_OFFSET 10
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#define IC_IDMAC_3_PP_WIDTH_MASK (0x3ff << 20)
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#define IC_IDMAC_3_PP_WIDTH_OFFSET 20
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struct ic_task_regoffs {
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u32 rsc;
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u32 tpmem_csc[2];
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};
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struct ic_task_bitfields {
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u32 ic_conf_en;
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u32 ic_conf_rot_en;
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u32 ic_conf_cmb_en;
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u32 ic_conf_csc1_en;
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u32 ic_conf_csc2_en;
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u32 ic_cmb_galpha_bit;
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};
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static const struct ic_task_regoffs ic_task_reg[IC_NUM_TASKS] = {
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[IC_TASK_ENCODER] = {
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.rsc = IC_PRP_ENC_RSC,
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.tpmem_csc = {0x2008, 0},
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},
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[IC_TASK_VIEWFINDER] = {
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.rsc = IC_PRP_VF_RSC,
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.tpmem_csc = {0x4028, 0x4040},
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},
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[IC_TASK_POST_PROCESSOR] = {
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.rsc = IC_PP_RSC,
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.tpmem_csc = {0x6060, 0x6078},
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},
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};
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static const struct ic_task_bitfields ic_task_bit[IC_NUM_TASKS] = {
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[IC_TASK_ENCODER] = {
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.ic_conf_en = IC_CONF_PRPENC_EN,
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.ic_conf_rot_en = IC_CONF_PRPENC_ROT_EN,
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.ic_conf_cmb_en = 0, /* NA */
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.ic_conf_csc1_en = IC_CONF_PRPENC_CSC1,
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.ic_conf_csc2_en = 0, /* NA */
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.ic_cmb_galpha_bit = 0, /* NA */
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},
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[IC_TASK_VIEWFINDER] = {
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.ic_conf_en = IC_CONF_PRPVF_EN,
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.ic_conf_rot_en = IC_CONF_PRPVF_ROT_EN,
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.ic_conf_cmb_en = IC_CONF_PRPVF_CMB,
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.ic_conf_csc1_en = IC_CONF_PRPVF_CSC1,
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.ic_conf_csc2_en = IC_CONF_PRPVF_CSC2,
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.ic_cmb_galpha_bit = 0,
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},
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[IC_TASK_POST_PROCESSOR] = {
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.ic_conf_en = IC_CONF_PP_EN,
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.ic_conf_rot_en = IC_CONF_PP_ROT_EN,
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.ic_conf_cmb_en = IC_CONF_PP_CMB,
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.ic_conf_csc1_en = IC_CONF_PP_CSC1,
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.ic_conf_csc2_en = IC_CONF_PP_CSC2,
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.ic_cmb_galpha_bit = 8,
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},
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};
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struct ipu_ic_priv;
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struct ipu_ic {
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enum ipu_ic_task task;
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const struct ic_task_regoffs *reg;
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const struct ic_task_bitfields *bit;
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enum ipu_color_space in_cs, g_in_cs;
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enum ipu_color_space out_cs;
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bool graphics;
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bool rotation;
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bool in_use;
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struct ipu_ic_priv *priv;
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};
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struct ipu_ic_priv {
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void __iomem *base;
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void __iomem *tpmem_base;
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spinlock_t lock;
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struct ipu_soc *ipu;
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int use_count;
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int irt_use_count;
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struct ipu_ic task[IC_NUM_TASKS];
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};
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static inline u32 ipu_ic_read(struct ipu_ic *ic, unsigned offset)
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{
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return readl(ic->priv->base + offset);
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}
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static inline void ipu_ic_write(struct ipu_ic *ic, u32 value, unsigned offset)
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{
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writel(value, ic->priv->base + offset);
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}
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struct ic_csc_params {
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s16 coeff[3][3]; /* signed 9-bit integer coefficients */
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s16 offset[3]; /* signed 11+2-bit fixed point offset */
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u8 scale:2; /* scale coefficients * 2^(scale-1) */
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bool sat:1; /* saturate to (16, 235(Y) / 240(U, V)) */
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};
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/*
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* Y = R * .299 + G * .587 + B * .114;
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* U = R * -.169 + G * -.332 + B * .500 + 128.;
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* V = R * .500 + G * -.419 + B * -.0813 + 128.;
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*/
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static const struct ic_csc_params ic_csc_rgb2ycbcr = {
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.coeff = {
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{ 77, 150, 29 },
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{ 469, 427, 128 },
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{ 128, 405, 491 },
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},
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.offset = { 0, 512, 512 },
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.scale = 1,
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};
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/* transparent RGB->RGB matrix for graphics combining */
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static const struct ic_csc_params ic_csc_rgb2rgb = {
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.coeff = {
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{ 128, 0, 0 },
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{ 0, 128, 0 },
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{ 0, 0, 128 },
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},
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.scale = 2,
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};
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/*
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* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
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* G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
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* B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128);
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*/
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static const struct ic_csc_params ic_csc_ycbcr2rgb = {
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.coeff = {
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{ 149, 0, 204 },
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{ 149, 462, 408 },
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{ 149, 255, 0 },
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},
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.offset = { -446, 266, -554 },
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.scale = 2,
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};
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static int init_csc(struct ipu_ic *ic,
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enum ipu_color_space inf,
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enum ipu_color_space outf,
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int csc_index)
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{
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struct ipu_ic_priv *priv = ic->priv;
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const struct ic_csc_params *params;
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u32 __iomem *base;
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const u16 (*c)[3];
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const u16 *a;
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u32 param;
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base = (u32 __iomem *)
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(priv->tpmem_base + ic->reg->tpmem_csc[csc_index]);
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if (inf == IPUV3_COLORSPACE_YUV && outf == IPUV3_COLORSPACE_RGB)
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params = &ic_csc_ycbcr2rgb;
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else if (inf == IPUV3_COLORSPACE_RGB && outf == IPUV3_COLORSPACE_YUV)
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params = &ic_csc_rgb2ycbcr;
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else if (inf == IPUV3_COLORSPACE_RGB && outf == IPUV3_COLORSPACE_RGB)
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params = &ic_csc_rgb2rgb;
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else {
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dev_err(priv->ipu->dev, "Unsupported color space conversion\n");
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return -EINVAL;
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}
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/* Cast to unsigned */
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c = (const u16 (*)[3])params->coeff;
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a = (const u16 *)params->offset;
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param = ((a[0] & 0x1f) << 27) | ((c[0][0] & 0x1ff) << 18) |
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((c[1][1] & 0x1ff) << 9) | (c[2][2] & 0x1ff);
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writel(param, base++);
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param = ((a[0] & 0x1fe0) >> 5) | (params->scale << 8) |
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(params->sat << 9);
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writel(param, base++);
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param = ((a[1] & 0x1f) << 27) | ((c[0][1] & 0x1ff) << 18) |
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((c[1][0] & 0x1ff) << 9) | (c[2][0] & 0x1ff);
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writel(param, base++);
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param = ((a[1] & 0x1fe0) >> 5);
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writel(param, base++);
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param = ((a[2] & 0x1f) << 27) | ((c[0][2] & 0x1ff) << 18) |
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((c[1][2] & 0x1ff) << 9) | (c[2][1] & 0x1ff);
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writel(param, base++);
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param = ((a[2] & 0x1fe0) >> 5);
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writel(param, base++);
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return 0;
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}
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static int calc_resize_coeffs(struct ipu_ic *ic,
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u32 in_size, u32 out_size,
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u32 *resize_coeff,
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u32 *downsize_coeff)
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{
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struct ipu_ic_priv *priv = ic->priv;
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struct ipu_soc *ipu = priv->ipu;
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u32 temp_size, temp_downsize;
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/*
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* Input size cannot be more than 4096, and output size cannot
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* be more than 1024
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*/
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if (in_size > 4096) {
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dev_err(ipu->dev, "Unsupported resize (in_size > 4096)\n");
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return -EINVAL;
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}
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if (out_size > 1024) {
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dev_err(ipu->dev, "Unsupported resize (out_size > 1024)\n");
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return -EINVAL;
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}
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/* Cannot downsize more than 4:1 */
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if ((out_size << 2) < in_size) {
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dev_err(ipu->dev, "Unsupported downsize\n");
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return -EINVAL;
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}
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/* Compute downsizing coefficient */
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temp_downsize = 0;
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temp_size = in_size;
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while (((temp_size > 1024) || (temp_size >= out_size * 2)) &&
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(temp_downsize < 2)) {
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temp_size >>= 1;
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temp_downsize++;
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}
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*downsize_coeff = temp_downsize;
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/*
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* compute resizing coefficient using the following equation:
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* resize_coeff = M * (SI - 1) / (SO - 1)
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* where M = 2^13, SI = input size, SO = output size
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*/
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*resize_coeff = (8192L * (temp_size - 1)) / (out_size - 1);
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if (*resize_coeff >= 16384L) {
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dev_err(ipu->dev, "Warning! Overflow on resize coeff.\n");
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*resize_coeff = 0x3FFF;
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}
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return 0;
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}
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void ipu_ic_task_enable(struct ipu_ic *ic)
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{
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struct ipu_ic_priv *priv = ic->priv;
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unsigned long flags;
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u32 ic_conf;
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spin_lock_irqsave(&priv->lock, flags);
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ic_conf = ipu_ic_read(ic, IC_CONF);
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ic_conf |= ic->bit->ic_conf_en;
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if (ic->rotation)
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ic_conf |= ic->bit->ic_conf_rot_en;
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if (ic->in_cs != ic->out_cs)
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ic_conf |= ic->bit->ic_conf_csc1_en;
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if (ic->graphics) {
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ic_conf |= ic->bit->ic_conf_cmb_en;
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ic_conf |= ic->bit->ic_conf_csc1_en;
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if (ic->g_in_cs != ic->out_cs)
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ic_conf |= ic->bit->ic_conf_csc2_en;
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}
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ipu_ic_write(ic, ic_conf, IC_CONF);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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EXPORT_SYMBOL_GPL(ipu_ic_task_enable);
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void ipu_ic_task_disable(struct ipu_ic *ic)
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{
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struct ipu_ic_priv *priv = ic->priv;
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unsigned long flags;
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u32 ic_conf;
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spin_lock_irqsave(&priv->lock, flags);
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ic_conf = ipu_ic_read(ic, IC_CONF);
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ic_conf &= ~(ic->bit->ic_conf_en |
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ic->bit->ic_conf_csc1_en |
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ic->bit->ic_conf_rot_en);
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if (ic->bit->ic_conf_csc2_en)
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ic_conf &= ~ic->bit->ic_conf_csc2_en;
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if (ic->bit->ic_conf_cmb_en)
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ic_conf &= ~ic->bit->ic_conf_cmb_en;
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ipu_ic_write(ic, ic_conf, IC_CONF);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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EXPORT_SYMBOL_GPL(ipu_ic_task_disable);
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int ipu_ic_task_graphics_init(struct ipu_ic *ic,
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enum ipu_color_space in_g_cs,
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bool galpha_en, u32 galpha,
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bool colorkey_en, u32 colorkey)
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{
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struct ipu_ic_priv *priv = ic->priv;
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unsigned long flags;
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u32 reg, ic_conf;
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int ret = 0;
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if (ic->task == IC_TASK_ENCODER)
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return -EINVAL;
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spin_lock_irqsave(&priv->lock, flags);
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ic_conf = ipu_ic_read(ic, IC_CONF);
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if (!(ic_conf & ic->bit->ic_conf_csc1_en)) {
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/* need transparent CSC1 conversion */
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ret = init_csc(ic, IPUV3_COLORSPACE_RGB,
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IPUV3_COLORSPACE_RGB, 0);
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if (ret)
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goto unlock;
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}
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ic->g_in_cs = in_g_cs;
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if (ic->g_in_cs != ic->out_cs) {
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ret = init_csc(ic, ic->g_in_cs, ic->out_cs, 1);
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if (ret)
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goto unlock;
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}
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if (galpha_en) {
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ic_conf |= IC_CONF_IC_GLB_LOC_A;
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reg = ipu_ic_read(ic, IC_CMBP_1);
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reg &= ~(0xff << ic->bit->ic_cmb_galpha_bit);
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reg |= (galpha << ic->bit->ic_cmb_galpha_bit);
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ipu_ic_write(ic, reg, IC_CMBP_1);
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} else
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ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
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if (colorkey_en) {
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ic_conf |= IC_CONF_KEY_COLOR_EN;
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ipu_ic_write(ic, colorkey, IC_CMBP_2);
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} else
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ic_conf &= ~IC_CONF_KEY_COLOR_EN;
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ipu_ic_write(ic, ic_conf, IC_CONF);
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ic->graphics = true;
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unlock:
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spin_unlock_irqrestore(&priv->lock, flags);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ipu_ic_task_graphics_init);
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int ipu_ic_task_init(struct ipu_ic *ic,
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int in_width, int in_height,
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int out_width, int out_height,
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enum ipu_color_space in_cs,
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enum ipu_color_space out_cs)
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{
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struct ipu_ic_priv *priv = ic->priv;
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u32 reg, downsize_coeff, resize_coeff;
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unsigned long flags;
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int ret = 0;
|
|
|
|
/* Setup vertical resizing */
|
|
ret = calc_resize_coeffs(ic, in_height, out_height,
|
|
&resize_coeff, &downsize_coeff);
|
|
if (ret)
|
|
return ret;
|
|
|
|
reg = (downsize_coeff << 30) | (resize_coeff << 16);
|
|
|
|
/* Setup horizontal resizing */
|
|
ret = calc_resize_coeffs(ic, in_width, out_width,
|
|
&resize_coeff, &downsize_coeff);
|
|
if (ret)
|
|
return ret;
|
|
|
|
reg |= (downsize_coeff << 14) | resize_coeff;
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
ipu_ic_write(ic, reg, ic->reg->rsc);
|
|
|
|
/* Setup color space conversion */
|
|
ic->in_cs = in_cs;
|
|
ic->out_cs = out_cs;
|
|
|
|
if (ic->in_cs != ic->out_cs) {
|
|
ret = init_csc(ic, ic->in_cs, ic->out_cs, 0);
|
|
if (ret)
|
|
goto unlock;
|
|
}
|
|
|
|
unlock:
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_ic_task_init);
|
|
|
|
int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
|
|
u32 width, u32 height, int burst_size,
|
|
enum ipu_rotate_mode rot)
|
|
{
|
|
struct ipu_ic_priv *priv = ic->priv;
|
|
struct ipu_soc *ipu = priv->ipu;
|
|
u32 ic_idmac_1, ic_idmac_2, ic_idmac_3;
|
|
u32 temp_rot = bitrev8(rot) >> 5;
|
|
bool need_hor_flip = false;
|
|
unsigned long flags;
|
|
int ret = 0;
|
|
|
|
if ((burst_size != 8) && (burst_size != 16)) {
|
|
dev_err(ipu->dev, "Illegal burst length for IC\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
width--;
|
|
height--;
|
|
|
|
if (temp_rot & 0x2) /* Need horizontal flip */
|
|
need_hor_flip = true;
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
ic_idmac_1 = ipu_ic_read(ic, IC_IDMAC_1);
|
|
ic_idmac_2 = ipu_ic_read(ic, IC_IDMAC_2);
|
|
ic_idmac_3 = ipu_ic_read(ic, IC_IDMAC_3);
|
|
|
|
switch (channel->num) {
|
|
case IPUV3_CHANNEL_IC_PP_MEM:
|
|
if (burst_size == 16)
|
|
ic_idmac_1 |= IC_IDMAC_1_CB2_BURST_16;
|
|
else
|
|
ic_idmac_1 &= ~IC_IDMAC_1_CB2_BURST_16;
|
|
|
|
if (need_hor_flip)
|
|
ic_idmac_1 |= IC_IDMAC_1_PP_FLIP_RS;
|
|
else
|
|
ic_idmac_1 &= ~IC_IDMAC_1_PP_FLIP_RS;
|
|
|
|
ic_idmac_2 &= ~IC_IDMAC_2_PP_HEIGHT_MASK;
|
|
ic_idmac_2 |= height << IC_IDMAC_2_PP_HEIGHT_OFFSET;
|
|
|
|
ic_idmac_3 &= ~IC_IDMAC_3_PP_WIDTH_MASK;
|
|
ic_idmac_3 |= width << IC_IDMAC_3_PP_WIDTH_OFFSET;
|
|
break;
|
|
case IPUV3_CHANNEL_MEM_IC_PP:
|
|
if (burst_size == 16)
|
|
ic_idmac_1 |= IC_IDMAC_1_CB5_BURST_16;
|
|
else
|
|
ic_idmac_1 &= ~IC_IDMAC_1_CB5_BURST_16;
|
|
break;
|
|
case IPUV3_CHANNEL_MEM_ROT_PP:
|
|
ic_idmac_1 &= ~IC_IDMAC_1_PP_ROT_MASK;
|
|
ic_idmac_1 |= temp_rot << IC_IDMAC_1_PP_ROT_OFFSET;
|
|
break;
|
|
case IPUV3_CHANNEL_MEM_IC_PRP_VF:
|
|
if (burst_size == 16)
|
|
ic_idmac_1 |= IC_IDMAC_1_CB6_BURST_16;
|
|
else
|
|
ic_idmac_1 &= ~IC_IDMAC_1_CB6_BURST_16;
|
|
break;
|
|
case IPUV3_CHANNEL_IC_PRP_ENC_MEM:
|
|
if (burst_size == 16)
|
|
ic_idmac_1 |= IC_IDMAC_1_CB0_BURST_16;
|
|
else
|
|
ic_idmac_1 &= ~IC_IDMAC_1_CB0_BURST_16;
|
|
|
|
if (need_hor_flip)
|
|
ic_idmac_1 |= IC_IDMAC_1_PRPENC_FLIP_RS;
|
|
else
|
|
ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_FLIP_RS;
|
|
|
|
ic_idmac_2 &= ~IC_IDMAC_2_PRPENC_HEIGHT_MASK;
|
|
ic_idmac_2 |= height << IC_IDMAC_2_PRPENC_HEIGHT_OFFSET;
|
|
|
|
ic_idmac_3 &= ~IC_IDMAC_3_PRPENC_WIDTH_MASK;
|
|
ic_idmac_3 |= width << IC_IDMAC_3_PRPENC_WIDTH_OFFSET;
|
|
break;
|
|
case IPUV3_CHANNEL_MEM_ROT_ENC:
|
|
ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_ROT_MASK;
|
|
ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPENC_ROT_OFFSET;
|
|
break;
|
|
case IPUV3_CHANNEL_IC_PRP_VF_MEM:
|
|
if (burst_size == 16)
|
|
ic_idmac_1 |= IC_IDMAC_1_CB1_BURST_16;
|
|
else
|
|
ic_idmac_1 &= ~IC_IDMAC_1_CB1_BURST_16;
|
|
|
|
if (need_hor_flip)
|
|
ic_idmac_1 |= IC_IDMAC_1_PRPVF_FLIP_RS;
|
|
else
|
|
ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_FLIP_RS;
|
|
|
|
ic_idmac_2 &= ~IC_IDMAC_2_PRPVF_HEIGHT_MASK;
|
|
ic_idmac_2 |= height << IC_IDMAC_2_PRPVF_HEIGHT_OFFSET;
|
|
|
|
ic_idmac_3 &= ~IC_IDMAC_3_PRPVF_WIDTH_MASK;
|
|
ic_idmac_3 |= width << IC_IDMAC_3_PRPVF_WIDTH_OFFSET;
|
|
break;
|
|
case IPUV3_CHANNEL_MEM_ROT_VF:
|
|
ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_ROT_MASK;
|
|
ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPVF_ROT_OFFSET;
|
|
break;
|
|
case IPUV3_CHANNEL_G_MEM_IC_PRP_VF:
|
|
if (burst_size == 16)
|
|
ic_idmac_1 |= IC_IDMAC_1_CB3_BURST_16;
|
|
else
|
|
ic_idmac_1 &= ~IC_IDMAC_1_CB3_BURST_16;
|
|
break;
|
|
case IPUV3_CHANNEL_G_MEM_IC_PP:
|
|
if (burst_size == 16)
|
|
ic_idmac_1 |= IC_IDMAC_1_CB4_BURST_16;
|
|
else
|
|
ic_idmac_1 &= ~IC_IDMAC_1_CB4_BURST_16;
|
|
break;
|
|
case IPUV3_CHANNEL_VDI_MEM_IC_VF:
|
|
if (burst_size == 16)
|
|
ic_idmac_1 |= IC_IDMAC_1_CB7_BURST_16;
|
|
else
|
|
ic_idmac_1 &= ~IC_IDMAC_1_CB7_BURST_16;
|
|
break;
|
|
default:
|
|
goto unlock;
|
|
}
|
|
|
|
ipu_ic_write(ic, ic_idmac_1, IC_IDMAC_1);
|
|
ipu_ic_write(ic, ic_idmac_2, IC_IDMAC_2);
|
|
ipu_ic_write(ic, ic_idmac_3, IC_IDMAC_3);
|
|
|
|
if (ipu_rot_mode_is_irt(rot))
|
|
ic->rotation = true;
|
|
|
|
unlock:
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_ic_task_idma_init);
|
|
|
|
static void ipu_irt_enable(struct ipu_ic *ic)
|
|
{
|
|
struct ipu_ic_priv *priv = ic->priv;
|
|
|
|
if (!priv->irt_use_count)
|
|
ipu_module_enable(priv->ipu, IPU_CONF_ROT_EN);
|
|
|
|
priv->irt_use_count++;
|
|
}
|
|
|
|
static void ipu_irt_disable(struct ipu_ic *ic)
|
|
{
|
|
struct ipu_ic_priv *priv = ic->priv;
|
|
|
|
if (priv->irt_use_count) {
|
|
if (!--priv->irt_use_count)
|
|
ipu_module_disable(priv->ipu, IPU_CONF_ROT_EN);
|
|
}
|
|
}
|
|
|
|
int ipu_ic_enable(struct ipu_ic *ic)
|
|
{
|
|
struct ipu_ic_priv *priv = ic->priv;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
if (!priv->use_count)
|
|
ipu_module_enable(priv->ipu, IPU_CONF_IC_EN);
|
|
|
|
priv->use_count++;
|
|
|
|
if (ic->rotation)
|
|
ipu_irt_enable(ic);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_ic_enable);
|
|
|
|
int ipu_ic_disable(struct ipu_ic *ic)
|
|
{
|
|
struct ipu_ic_priv *priv = ic->priv;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
priv->use_count--;
|
|
|
|
if (!priv->use_count)
|
|
ipu_module_disable(priv->ipu, IPU_CONF_IC_EN);
|
|
|
|
if (priv->use_count < 0)
|
|
priv->use_count = 0;
|
|
|
|
if (ic->rotation)
|
|
ipu_irt_disable(ic);
|
|
|
|
ic->rotation = ic->graphics = false;
|
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_ic_disable);
|
|
|
|
struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task)
|
|
{
|
|
struct ipu_ic_priv *priv = ipu->ic_priv;
|
|
unsigned long flags;
|
|
struct ipu_ic *ic, *ret;
|
|
|
|
if (task >= IC_NUM_TASKS)
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
ic = &priv->task[task];
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
if (ic->in_use) {
|
|
ret = ERR_PTR(-EBUSY);
|
|
goto unlock;
|
|
}
|
|
|
|
ic->in_use = true;
|
|
ret = ic;
|
|
|
|
unlock:
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_ic_get);
|
|
|
|
void ipu_ic_put(struct ipu_ic *ic)
|
|
{
|
|
struct ipu_ic_priv *priv = ic->priv;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
ic->in_use = false;
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_ic_put);
|
|
|
|
int ipu_ic_init(struct ipu_soc *ipu, struct device *dev,
|
|
unsigned long base, unsigned long tpmem_base)
|
|
{
|
|
struct ipu_ic_priv *priv;
|
|
int i;
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
ipu->ic_priv = priv;
|
|
|
|
spin_lock_init(&priv->lock);
|
|
priv->base = devm_ioremap(dev, base, PAGE_SIZE);
|
|
if (!priv->base)
|
|
return -ENOMEM;
|
|
priv->tpmem_base = devm_ioremap(dev, tpmem_base, SZ_64K);
|
|
if (!priv->tpmem_base)
|
|
return -ENOMEM;
|
|
|
|
dev_dbg(dev, "IC base: 0x%08lx remapped to %p\n", base, priv->base);
|
|
|
|
priv->ipu = ipu;
|
|
|
|
for (i = 0; i < IC_NUM_TASKS; i++) {
|
|
priv->task[i].task = i;
|
|
priv->task[i].priv = priv;
|
|
priv->task[i].reg = &ic_task_reg[i];
|
|
priv->task[i].bit = &ic_task_bit[i];
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void ipu_ic_exit(struct ipu_soc *ipu)
|
|
{
|
|
}
|
|
|
|
void ipu_ic_dump(struct ipu_ic *ic)
|
|
{
|
|
struct ipu_ic_priv *priv = ic->priv;
|
|
struct ipu_soc *ipu = priv->ipu;
|
|
|
|
dev_dbg(ipu->dev, "IC_CONF = \t0x%08X\n",
|
|
ipu_ic_read(ic, IC_CONF));
|
|
dev_dbg(ipu->dev, "IC_PRP_ENC_RSC = \t0x%08X\n",
|
|
ipu_ic_read(ic, IC_PRP_ENC_RSC));
|
|
dev_dbg(ipu->dev, "IC_PRP_VF_RSC = \t0x%08X\n",
|
|
ipu_ic_read(ic, IC_PRP_VF_RSC));
|
|
dev_dbg(ipu->dev, "IC_PP_RSC = \t0x%08X\n",
|
|
ipu_ic_read(ic, IC_PP_RSC));
|
|
dev_dbg(ipu->dev, "IC_CMBP_1 = \t0x%08X\n",
|
|
ipu_ic_read(ic, IC_CMBP_1));
|
|
dev_dbg(ipu->dev, "IC_CMBP_2 = \t0x%08X\n",
|
|
ipu_ic_read(ic, IC_CMBP_2));
|
|
dev_dbg(ipu->dev, "IC_IDMAC_1 = \t0x%08X\n",
|
|
ipu_ic_read(ic, IC_IDMAC_1));
|
|
dev_dbg(ipu->dev, "IC_IDMAC_2 = \t0x%08X\n",
|
|
ipu_ic_read(ic, IC_IDMAC_2));
|
|
dev_dbg(ipu->dev, "IC_IDMAC_3 = \t0x%08X\n",
|
|
ipu_ic_read(ic, IC_IDMAC_3));
|
|
dev_dbg(ipu->dev, "IC_IDMAC_4 = \t0x%08X\n",
|
|
ipu_ic_read(ic, IC_IDMAC_4));
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_ic_dump);
|