187 lines
5.6 KiB
C
187 lines
5.6 KiB
C
/*
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* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#define gk20a_volt(p) container_of((p), struct gk20a_volt, base)
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#include "priv.h"
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#include <core/tegra.h>
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#include "gk20a.h"
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static const struct cvb_coef gk20a_cvb_coef[] = {
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/* MHz, c0, c1, c2, c3, c4, c5 */
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/* 72 */ { 1209886, -36468, 515, 417, -13123, 203},
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/* 108 */ { 1130804, -27659, 296, 298, -10834, 221},
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/* 180 */ { 1162871, -27110, 247, 238, -10681, 268},
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/* 252 */ { 1220458, -28654, 247, 179, -10376, 298},
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/* 324 */ { 1280953, -30204, 247, 119, -9766, 304},
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/* 396 */ { 1344547, -31777, 247, 119, -8545, 292},
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/* 468 */ { 1420168, -34227, 269, 60, -7172, 256},
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/* 540 */ { 1490757, -35955, 274, 60, -5188, 197},
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/* 612 */ { 1599112, -42583, 398, 0, -1831, 119},
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/* 648 */ { 1366986, -16459, -274, 0, -3204, 72},
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/* 684 */ { 1391884, -17078, -274, -60, -1526, 30},
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/* 708 */ { 1415522, -17497, -274, -60, -458, 0},
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/* 756 */ { 1464061, -18331, -274, -119, 1831, -72},
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/* 804 */ { 1524225, -20064, -254, -119, 4272, -155},
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/* 852 */ { 1608418, -21643, -269, 0, 763, -48},
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};
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/**
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* cvb_mv = ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0)
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*/
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static inline int
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gk20a_volt_get_cvb_voltage(int speedo, int s_scale, const struct cvb_coef *coef)
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{
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int mv;
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mv = DIV_ROUND_CLOSEST(coef->c2 * speedo, s_scale);
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mv = DIV_ROUND_CLOSEST((mv + coef->c1) * speedo, s_scale) + coef->c0;
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return mv;
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}
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/**
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* cvb_t_mv =
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* ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0) +
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* ((c3 * speedo / s_scale + c4 + c5 * T / t_scale) * T / t_scale)
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*/
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static inline int
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gk20a_volt_get_cvb_t_voltage(int speedo, int temp, int s_scale, int t_scale,
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const struct cvb_coef *coef)
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{
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int cvb_mv, mv;
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cvb_mv = gk20a_volt_get_cvb_voltage(speedo, s_scale, coef);
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mv = DIV_ROUND_CLOSEST(coef->c3 * speedo, s_scale) + coef->c4 +
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DIV_ROUND_CLOSEST(coef->c5 * temp, t_scale);
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mv = DIV_ROUND_CLOSEST(mv * temp, t_scale) + cvb_mv;
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return mv;
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}
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static int
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gk20a_volt_calc_voltage(const struct cvb_coef *coef, int speedo)
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{
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static const int v_scale = 1000;
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int mv;
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mv = gk20a_volt_get_cvb_t_voltage(speedo, -10, 100, 10, coef);
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mv = DIV_ROUND_UP(mv, v_scale);
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return mv * 1000;
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}
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static int
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gk20a_volt_vid_get(struct nvkm_volt *base)
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{
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struct gk20a_volt *volt = gk20a_volt(base);
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int i, uv;
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uv = regulator_get_voltage(volt->vdd);
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for (i = 0; i < volt->base.vid_nr; i++)
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if (volt->base.vid[i].uv >= uv)
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return i;
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return -EINVAL;
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}
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static int
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gk20a_volt_vid_set(struct nvkm_volt *base, u8 vid)
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{
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struct gk20a_volt *volt = gk20a_volt(base);
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struct nvkm_subdev *subdev = &volt->base.subdev;
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nvkm_debug(subdev, "set voltage as %duv\n", volt->base.vid[vid].uv);
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return regulator_set_voltage(volt->vdd, volt->base.vid[vid].uv, 1200000);
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}
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static int
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gk20a_volt_set_id(struct nvkm_volt *base, u8 id, int condition)
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{
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struct gk20a_volt *volt = gk20a_volt(base);
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struct nvkm_subdev *subdev = &volt->base.subdev;
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int prev_uv = regulator_get_voltage(volt->vdd);
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int target_uv = volt->base.vid[id].uv;
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int ret;
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nvkm_debug(subdev, "prev=%d, target=%d, condition=%d\n",
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prev_uv, target_uv, condition);
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if (!condition ||
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(condition < 0 && target_uv < prev_uv) ||
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(condition > 0 && target_uv > prev_uv)) {
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ret = gk20a_volt_vid_set(&volt->base, volt->base.vid[id].vid);
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} else {
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ret = 0;
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}
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return ret;
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}
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static const struct nvkm_volt_func
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gk20a_volt = {
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.vid_get = gk20a_volt_vid_get,
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.vid_set = gk20a_volt_vid_set,
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.set_id = gk20a_volt_set_id,
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};
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int
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gk20a_volt_ctor(struct nvkm_device *device, int index,
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const struct cvb_coef *coefs, int nb_coefs,
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int vmin, struct gk20a_volt *volt)
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{
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struct nvkm_device_tegra *tdev = device->func->tegra(device);
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int i, uv;
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nvkm_volt_ctor(&gk20a_volt, device, index, &volt->base);
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uv = regulator_get_voltage(tdev->vdd);
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nvkm_debug(&volt->base.subdev, "the default voltage is %duV\n", uv);
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volt->vdd = tdev->vdd;
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volt->base.vid_nr = nb_coefs;
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for (i = 0; i < volt->base.vid_nr; i++) {
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volt->base.vid[i].vid = i;
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volt->base.vid[i].uv = max(
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gk20a_volt_calc_voltage(&coefs[i], tdev->gpu_speedo),
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vmin);
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nvkm_debug(&volt->base.subdev, "%2d: vid=%d, uv=%d\n", i,
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volt->base.vid[i].vid, volt->base.vid[i].uv);
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}
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return 0;
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}
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int
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gk20a_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt)
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{
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struct gk20a_volt *volt;
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volt = kzalloc(sizeof(*volt), GFP_KERNEL);
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if (!volt)
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return -ENOMEM;
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*pvolt = &volt->base;
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return gk20a_volt_ctor(device, index, gk20a_cvb_coef,
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ARRAY_SIZE(gk20a_cvb_coef), 0, volt);
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}
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