157 lines
4.1 KiB
C
157 lines
4.1 KiB
C
/*
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* Copyright 2015 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs <bskeggs@redhat.com>
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*/
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#include "priv.h"
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#include <core/pci.h>
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static int
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g84_pcie_version_supported(struct nvkm_pci *pci)
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{
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/* g84 and g86 report wrong information about what they support */
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return 1;
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}
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int
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g84_pcie_version(struct nvkm_pci *pci)
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{
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struct nvkm_device *device = pci->subdev.device;
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return (nvkm_rd32(device, 0x00154c) & 0x1) + 1;
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}
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void
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g84_pcie_set_version(struct nvkm_pci *pci, u8 ver)
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{
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struct nvkm_device *device = pci->subdev.device;
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nvkm_mask(device, 0x00154c, 0x1, (ver >= 2 ? 0x1 : 0x0));
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}
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static void
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g84_pcie_set_cap_speed(struct nvkm_pci *pci, bool full_speed)
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{
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struct nvkm_device *device = pci->subdev.device;
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nvkm_mask(device, 0x00154c, 0x80, full_speed ? 0x80 : 0x0);
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}
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enum nvkm_pcie_speed
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g84_pcie_cur_speed(struct nvkm_pci *pci)
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{
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u32 reg_v = nvkm_pci_rd32(pci, 0x88) & 0x30000;
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switch (reg_v) {
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case 0x30000:
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return NVKM_PCIE_SPEED_8_0;
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case 0x20000:
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return NVKM_PCIE_SPEED_5_0;
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case 0x10000:
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default:
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return NVKM_PCIE_SPEED_2_5;
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}
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}
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enum nvkm_pcie_speed
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g84_pcie_max_speed(struct nvkm_pci *pci)
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{
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u32 reg_v = nvkm_pci_rd32(pci, 0x460) & 0x3300;
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if (reg_v == 0x2200)
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return NVKM_PCIE_SPEED_5_0;
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return NVKM_PCIE_SPEED_2_5;
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}
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void
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g84_pcie_set_link_speed(struct nvkm_pci *pci, enum nvkm_pcie_speed speed)
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{
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u32 mask_value;
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if (speed == NVKM_PCIE_SPEED_5_0)
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mask_value = 0x20;
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else
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mask_value = 0x10;
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nvkm_pci_mask(pci, 0x460, 0x30, mask_value);
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nvkm_pci_mask(pci, 0x460, 0x1, 0x1);
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}
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int
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g84_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed speed, u8 width)
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{
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g84_pcie_set_cap_speed(pci, speed == NVKM_PCIE_SPEED_5_0);
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g84_pcie_set_link_speed(pci, speed);
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return 0;
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}
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void
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g84_pci_init(struct nvkm_pci *pci)
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{
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/* The following only concerns PCIe cards. */
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if (!pci_is_pcie(pci->pdev))
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return;
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/* Tag field is 8-bit long, regardless of EXT_TAG.
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* However, if EXT_TAG is disabled, only the lower 5 bits of the tag
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* field should be used, limiting the number of request to 32.
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*
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* Apparently, 0x041c stores some limit on the number of requests
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* possible, so if EXT_TAG is disabled, limit that requests number to
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* 32
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*
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* Fixes fdo#86537
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*/
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if (nvkm_pci_rd32(pci, 0x007c) & 0x00000020)
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nvkm_pci_mask(pci, 0x0080, 0x00000100, 0x00000100);
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else
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nvkm_pci_mask(pci, 0x041c, 0x00000060, 0x00000000);
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}
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int
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g84_pcie_init(struct nvkm_pci *pci)
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{
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bool full_speed = g84_pcie_cur_speed(pci) == NVKM_PCIE_SPEED_5_0;
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g84_pcie_set_cap_speed(pci, full_speed);
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return 0;
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}
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static const struct nvkm_pci_func
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g84_pci_func = {
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.init = g84_pci_init,
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.rd32 = nv40_pci_rd32,
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.wr08 = nv40_pci_wr08,
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.wr32 = nv40_pci_wr32,
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.msi_rearm = nv46_pci_msi_rearm,
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.pcie.init = g84_pcie_init,
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.pcie.set_link = g84_pcie_set_link,
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.pcie.max_speed = g84_pcie_max_speed,
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.pcie.cur_speed = g84_pcie_cur_speed,
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.pcie.set_version = g84_pcie_set_version,
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.pcie.version = g84_pcie_version,
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.pcie.version_supported = g84_pcie_version_supported,
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};
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int
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g84_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
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{
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return nvkm_pci_new_(&g84_pci_func, device, index, ppci);
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}
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