660 lines
15 KiB
C
660 lines
15 KiB
C
/*
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* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c
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*
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*/
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#include "priv.h"
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#include "gk20a.h"
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#include <core/tegra.h>
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#include <subdev/timer.h>
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static const u8 _pl_to_div[] = {
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/* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
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/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32,
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};
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static u32 pl_to_div(u32 pl)
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{
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if (pl >= ARRAY_SIZE(_pl_to_div))
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return 1;
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return _pl_to_div[pl];
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}
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static u32 div_to_pl(u32 div)
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{
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u32 pl;
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for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) {
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if (_pl_to_div[pl] >= div)
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return pl;
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}
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return ARRAY_SIZE(_pl_to_div) - 1;
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}
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static const struct gk20a_clk_pllg_params gk20a_pllg_params = {
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.min_vco = 1000000, .max_vco = 2064000,
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.min_u = 12000, .max_u = 38000,
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.min_m = 1, .max_m = 255,
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.min_n = 8, .max_n = 255,
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.min_pl = 1, .max_pl = 32,
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};
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void
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gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll)
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{
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struct nvkm_device *device = clk->base.subdev.device;
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u32 val;
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val = nvkm_rd32(device, GPCPLL_COEFF);
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pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
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pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
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pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
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}
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void
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gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)
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{
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struct nvkm_device *device = clk->base.subdev.device;
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u32 val;
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val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT;
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val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT;
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val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT;
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nvkm_wr32(device, GPCPLL_COEFF, val);
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}
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u32
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gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll)
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{
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u32 rate;
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u32 divider;
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rate = clk->parent_rate * pll->n;
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divider = pll->m * clk->pl_to_div(pll->pl);
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return rate / divider / 2;
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}
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int
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gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate,
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struct gk20a_pll *pll)
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{
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struct nvkm_subdev *subdev = &clk->base.subdev;
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u32 target_clk_f, ref_clk_f, target_freq;
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u32 min_vco_f, max_vco_f;
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u32 low_pl, high_pl, best_pl;
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u32 target_vco_f;
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u32 best_m, best_n;
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u32 best_delta = ~0;
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u32 pl;
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target_clk_f = rate * 2 / KHZ;
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ref_clk_f = clk->parent_rate / KHZ;
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target_vco_f = target_clk_f + target_clk_f / 50;
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max_vco_f = max(clk->params->max_vco, target_vco_f);
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min_vco_f = clk->params->min_vco;
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best_m = clk->params->max_m;
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best_n = clk->params->min_n;
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best_pl = clk->params->min_pl;
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/* min_pl <= high_pl <= max_pl */
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high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f;
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high_pl = min(high_pl, clk->params->max_pl);
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high_pl = max(high_pl, clk->params->min_pl);
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high_pl = clk->div_to_pl(high_pl);
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/* min_pl <= low_pl <= max_pl */
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low_pl = min_vco_f / target_vco_f;
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low_pl = min(low_pl, clk->params->max_pl);
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low_pl = max(low_pl, clk->params->min_pl);
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low_pl = clk->div_to_pl(low_pl);
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nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl,
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clk->pl_to_div(low_pl), high_pl, clk->pl_to_div(high_pl));
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/* Select lowest possible VCO */
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for (pl = low_pl; pl <= high_pl; pl++) {
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u32 m, n, n2;
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target_vco_f = target_clk_f * clk->pl_to_div(pl);
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for (m = clk->params->min_m; m <= clk->params->max_m; m++) {
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u32 u_f = ref_clk_f / m;
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if (u_f < clk->params->min_u)
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break;
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if (u_f > clk->params->max_u)
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continue;
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n = (target_vco_f * m) / ref_clk_f;
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n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f;
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if (n > clk->params->max_n)
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break;
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for (; n <= n2; n++) {
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u32 vco_f;
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if (n < clk->params->min_n)
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continue;
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if (n > clk->params->max_n)
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break;
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vco_f = ref_clk_f * n / m;
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if (vco_f >= min_vco_f && vco_f <= max_vco_f) {
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u32 delta, lwv;
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lwv = (vco_f + (clk->pl_to_div(pl) / 2))
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/ clk->pl_to_div(pl);
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delta = abs(lwv - target_clk_f);
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if (delta < best_delta) {
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best_delta = delta;
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best_m = m;
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best_n = n;
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best_pl = pl;
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if (best_delta == 0)
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goto found_match;
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}
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}
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}
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}
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}
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found_match:
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WARN_ON(best_delta == ~0);
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if (best_delta != 0)
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nvkm_debug(subdev,
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"no best match for target @ %dMHz on gpc_pll",
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target_clk_f / KHZ);
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pll->m = best_m;
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pll->n = best_n;
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pll->pl = best_pl;
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target_freq = gk20a_pllg_calc_rate(clk, pll);
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nvkm_debug(subdev,
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"actual target freq %d KHz, M %d, N %d, PL %d(div%d)\n",
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target_freq / KHZ, pll->m, pll->n, pll->pl,
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clk->pl_to_div(pll->pl));
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return 0;
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}
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static int
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gk20a_pllg_slide(struct gk20a_clk *clk, u32 n)
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{
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvkm_device *device = subdev->device;
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struct gk20a_pll pll;
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int ret = 0;
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/* get old coefficients */
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gk20a_pllg_read_mnp(clk, &pll);
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/* do nothing if NDIV is the same */
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if (n == pll.n)
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return 0;
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/* pll slowdown mode */
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nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,
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BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT),
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BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT));
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/* new ndiv ready for ramp */
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pll.n = n;
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udelay(1);
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gk20a_pllg_write_mnp(clk, &pll);
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/* dynamic ramp to new ndiv */
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udelay(1);
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nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,
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BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT),
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BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT));
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/* wait for ramping to complete */
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if (nvkm_wait_usec(device, 500, GPC_BCAST_NDIV_SLOWDOWN_DEBUG,
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GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK,
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GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK) < 0)
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ret = -ETIMEDOUT;
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/* exit slowdown mode */
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nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,
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BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) |
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BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0);
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nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN);
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return ret;
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}
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static int
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gk20a_pllg_enable(struct gk20a_clk *clk)
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{
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struct nvkm_device *device = clk->base.subdev.device;
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u32 val;
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nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);
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nvkm_rd32(device, GPCPLL_CFG);
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/* enable lock detection */
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val = nvkm_rd32(device, GPCPLL_CFG);
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if (val & GPCPLL_CFG_LOCK_DET_OFF) {
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val &= ~GPCPLL_CFG_LOCK_DET_OFF;
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nvkm_wr32(device, GPCPLL_CFG, val);
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}
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/* wait for lock */
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if (nvkm_wait_usec(device, 300, GPCPLL_CFG, GPCPLL_CFG_LOCK,
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GPCPLL_CFG_LOCK) < 0)
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return -ETIMEDOUT;
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/* switch to VCO mode */
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nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT),
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BIT(SEL_VCO_GPC2CLK_OUT_SHIFT));
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return 0;
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}
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static void
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gk20a_pllg_disable(struct gk20a_clk *clk)
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{
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struct nvkm_device *device = clk->base.subdev.device;
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/* put PLL in bypass before disabling it */
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nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0);
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nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);
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nvkm_rd32(device, GPCPLL_CFG);
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}
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static int
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gk20a_pllg_program_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)
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{
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvkm_device *device = subdev->device;
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struct gk20a_pll cur_pll;
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int ret;
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gk20a_pllg_read_mnp(clk, &cur_pll);
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/* split VCO-to-bypass jump in half by setting out divider 1:2 */
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nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
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GPC2CLK_OUT_VCODIV2 << GPC2CLK_OUT_VCODIV_SHIFT);
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/* Intentional 2nd write to assure linear divider operation */
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nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
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GPC2CLK_OUT_VCODIV2 << GPC2CLK_OUT_VCODIV_SHIFT);
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nvkm_rd32(device, GPC2CLK_OUT);
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udelay(2);
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gk20a_pllg_disable(clk);
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gk20a_pllg_write_mnp(clk, pll);
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ret = gk20a_pllg_enable(clk);
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if (ret)
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return ret;
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/* restore out divider 1:1 */
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udelay(2);
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nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
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GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT);
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/* Intentional 2nd write to assure linear divider operation */
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nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
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GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT);
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nvkm_rd32(device, GPC2CLK_OUT);
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return 0;
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}
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static int
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gk20a_pllg_program_mnp_slide(struct gk20a_clk *clk, const struct gk20a_pll *pll)
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{
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struct gk20a_pll cur_pll;
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int ret;
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if (gk20a_pllg_is_enabled(clk)) {
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gk20a_pllg_read_mnp(clk, &cur_pll);
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/* just do NDIV slide if there is no change to M and PL */
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if (pll->m == cur_pll.m && pll->pl == cur_pll.pl)
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return gk20a_pllg_slide(clk, pll->n);
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/* slide down to current NDIV_LO */
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cur_pll.n = gk20a_pllg_n_lo(clk, &cur_pll);
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ret = gk20a_pllg_slide(clk, cur_pll.n);
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if (ret)
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return ret;
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}
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/* program MNP with the new clock parameters and new NDIV_LO */
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cur_pll = *pll;
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cur_pll.n = gk20a_pllg_n_lo(clk, &cur_pll);
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ret = gk20a_pllg_program_mnp(clk, &cur_pll);
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if (ret)
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return ret;
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/* slide up to new NDIV */
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return gk20a_pllg_slide(clk, pll->n);
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}
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static struct nvkm_pstate
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gk20a_pstates[] = {
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{
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.base = {
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.domain[nv_clk_src_gpc] = 72000,
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.voltage = 0,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 108000,
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.voltage = 1,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 180000,
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.voltage = 2,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 252000,
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.voltage = 3,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 324000,
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.voltage = 4,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 396000,
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.voltage = 5,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 468000,
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.voltage = 6,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 540000,
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.voltage = 7,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 612000,
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.voltage = 8,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 648000,
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.voltage = 9,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 684000,
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.voltage = 10,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 708000,
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.voltage = 11,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 756000,
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.voltage = 12,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 804000,
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.voltage = 13,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 852000,
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.voltage = 14,
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},
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},
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};
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int
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gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
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{
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struct gk20a_clk *clk = gk20a_clk(base);
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvkm_device *device = subdev->device;
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struct gk20a_pll pll;
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switch (src) {
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case nv_clk_src_crystal:
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return device->crystal;
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case nv_clk_src_gpc:
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gk20a_pllg_read_mnp(clk, &pll);
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return gk20a_pllg_calc_rate(clk, &pll) / GK20A_CLK_GPC_MDIV;
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default:
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nvkm_error(subdev, "invalid clock source %d\n", src);
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return -EINVAL;
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}
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}
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int
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gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
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{
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struct gk20a_clk *clk = gk20a_clk(base);
|
|
|
|
return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] *
|
|
GK20A_CLK_GPC_MDIV, &clk->pll);
|
|
}
|
|
|
|
int
|
|
gk20a_clk_prog(struct nvkm_clk *base)
|
|
{
|
|
struct gk20a_clk *clk = gk20a_clk(base);
|
|
int ret;
|
|
|
|
ret = gk20a_pllg_program_mnp_slide(clk, &clk->pll);
|
|
if (ret)
|
|
ret = gk20a_pllg_program_mnp(clk, &clk->pll);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void
|
|
gk20a_clk_tidy(struct nvkm_clk *base)
|
|
{
|
|
}
|
|
|
|
int
|
|
gk20a_clk_setup_slide(struct gk20a_clk *clk)
|
|
{
|
|
struct nvkm_subdev *subdev = &clk->base.subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
u32 step_a, step_b;
|
|
|
|
switch (clk->parent_rate) {
|
|
case 12000000:
|
|
case 12800000:
|
|
case 13000000:
|
|
step_a = 0x2b;
|
|
step_b = 0x0b;
|
|
break;
|
|
case 19200000:
|
|
step_a = 0x12;
|
|
step_b = 0x08;
|
|
break;
|
|
case 38400000:
|
|
step_a = 0x04;
|
|
step_b = 0x05;
|
|
break;
|
|
default:
|
|
nvkm_error(subdev, "invalid parent clock rate %u KHz",
|
|
clk->parent_rate / KHZ);
|
|
return -EINVAL;
|
|
}
|
|
|
|
nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT,
|
|
step_a << GPCPLL_CFG2_PLL_STEPA_SHIFT);
|
|
nvkm_mask(device, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT,
|
|
step_b << GPCPLL_CFG3_PLL_STEPB_SHIFT);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
gk20a_clk_fini(struct nvkm_clk *base)
|
|
{
|
|
struct nvkm_device *device = base->subdev.device;
|
|
struct gk20a_clk *clk = gk20a_clk(base);
|
|
|
|
/* slide to VCO min */
|
|
if (gk20a_pllg_is_enabled(clk)) {
|
|
struct gk20a_pll pll;
|
|
u32 n_lo;
|
|
|
|
gk20a_pllg_read_mnp(clk, &pll);
|
|
n_lo = gk20a_pllg_n_lo(clk, &pll);
|
|
gk20a_pllg_slide(clk, n_lo);
|
|
}
|
|
|
|
gk20a_pllg_disable(clk);
|
|
|
|
/* set IDDQ */
|
|
nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 1);
|
|
}
|
|
|
|
static int
|
|
gk20a_clk_init(struct nvkm_clk *base)
|
|
{
|
|
struct gk20a_clk *clk = gk20a_clk(base);
|
|
struct nvkm_subdev *subdev = &clk->base.subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
int ret;
|
|
|
|
/* get out from IDDQ */
|
|
nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 0);
|
|
nvkm_rd32(device, GPCPLL_CFG);
|
|
udelay(5);
|
|
|
|
nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK,
|
|
GPC2CLK_OUT_INIT_VAL);
|
|
|
|
ret = gk20a_clk_setup_slide(clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Start with lowest frequency */
|
|
base->func->calc(base, &base->func->pstates[0].base);
|
|
ret = base->func->prog(&clk->base);
|
|
if (ret) {
|
|
nvkm_error(subdev, "cannot initialize clock\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct nvkm_clk_func
|
|
gk20a_clk = {
|
|
.init = gk20a_clk_init,
|
|
.fini = gk20a_clk_fini,
|
|
.read = gk20a_clk_read,
|
|
.calc = gk20a_clk_calc,
|
|
.prog = gk20a_clk_prog,
|
|
.tidy = gk20a_clk_tidy,
|
|
.pstates = gk20a_pstates,
|
|
.nr_pstates = ARRAY_SIZE(gk20a_pstates),
|
|
.domains = {
|
|
{ nv_clk_src_crystal, 0xff },
|
|
{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
|
|
{ nv_clk_src_max }
|
|
}
|
|
};
|
|
|
|
int
|
|
gk20a_clk_ctor(struct nvkm_device *device, int index,
|
|
const struct nvkm_clk_func *func,
|
|
const struct gk20a_clk_pllg_params *params,
|
|
struct gk20a_clk *clk)
|
|
{
|
|
struct nvkm_device_tegra *tdev = device->func->tegra(device);
|
|
int ret;
|
|
int i;
|
|
|
|
/* Finish initializing the pstates */
|
|
for (i = 0; i < func->nr_pstates; i++) {
|
|
INIT_LIST_HEAD(&func->pstates[i].list);
|
|
func->pstates[i].pstate = i + 1;
|
|
}
|
|
|
|
clk->params = params;
|
|
clk->parent_rate = clk_get_rate(tdev->clk);
|
|
|
|
ret = nvkm_clk_ctor(func, device, index, true, &clk->base);
|
|
if (ret)
|
|
return ret;
|
|
|
|
nvkm_debug(&clk->base.subdev, "parent clock rate: %d Khz\n",
|
|
clk->parent_rate / KHZ);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
|
|
{
|
|
struct gk20a_clk *clk;
|
|
int ret;
|
|
|
|
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
|
|
if (!clk)
|
|
return -ENOMEM;
|
|
*pclk = &clk->base;
|
|
|
|
ret = gk20a_clk_ctor(device, index, &gk20a_clk, &gk20a_pllg_params,
|
|
clk);
|
|
|
|
clk->pl_to_div = pl_to_div;
|
|
clk->div_to_pl = div_to_pl;
|
|
|
|
return ret;
|
|
}
|