497 lines
14 KiB
C
497 lines
14 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "rootnv50.h"
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#include "dmacnv50.h"
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#include "dp.h"
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#include "head.h"
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#include "ior.h"
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#include <core/client.h>
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#include <core/ramht.h>
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#include <subdev/timer.h>
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#include <nvif/class.h>
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#include <nvif/cl5070.h>
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#include <nvif/unpack.h>
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static int
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nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
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{
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union {
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struct nv50_disp_mthd_v0 v0;
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struct nv50_disp_mthd_v1 v1;
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} *args = data;
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struct nv50_disp_root *root = nv50_disp_root(object);
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struct nv50_disp *disp = root->disp;
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struct nvkm_outp *temp, *outp = NULL;
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struct nvkm_head *head;
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u16 type, mask = 0;
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int hidx, ret = -ENOSYS;
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if (mthd != NV50_DISP_MTHD)
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return -EINVAL;
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nvif_ioctl(object, "disp mthd size %d\n", size);
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if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
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nvif_ioctl(object, "disp mthd vers %d mthd %02x head %d\n",
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args->v0.version, args->v0.method, args->v0.head);
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mthd = args->v0.method;
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hidx = args->v0.head;
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} else
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if (!(ret = nvif_unpack(ret, &data, &size, args->v1, 1, 1, true))) {
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nvif_ioctl(object, "disp mthd vers %d mthd %02x "
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"type %04x mask %04x\n",
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args->v1.version, args->v1.method,
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args->v1.hasht, args->v1.hashm);
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mthd = args->v1.method;
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type = args->v1.hasht;
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mask = args->v1.hashm;
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hidx = ffs((mask >> 8) & 0x0f) - 1;
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} else
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return ret;
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if (!(head = nvkm_head_find(&disp->base, hidx)))
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return -ENXIO;
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if (mask) {
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list_for_each_entry(temp, &disp->base.outp, head) {
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if ((temp->info.hasht == type) &&
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(temp->info.hashm & mask) == mask) {
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outp = temp;
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break;
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}
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}
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if (outp == NULL)
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return -ENXIO;
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}
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switch (mthd) {
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case NV50_DISP_SCANOUTPOS: {
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return nvkm_head_mthd_scanoutpos(object, head, data, size);
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}
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default:
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break;
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}
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switch (mthd * !!outp) {
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case NV50_DISP_MTHD_V1_ACQUIRE: {
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union {
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struct nv50_disp_acquire_v0 v0;
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} *args = data;
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int ret = -ENOSYS;
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if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
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ret = nvkm_outp_acquire(outp, NVKM_OUTP_USER);
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if (ret == 0) {
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args->v0.or = outp->ior->id;
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args->v0.link = outp->ior->asy.link;
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}
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}
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return ret;
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}
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break;
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case NV50_DISP_MTHD_V1_RELEASE:
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nvkm_outp_release(outp, NVKM_OUTP_USER);
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return 0;
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case NV50_DISP_MTHD_V1_DAC_LOAD: {
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union {
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struct nv50_disp_dac_load_v0 v0;
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} *args = data;
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int ret = -ENOSYS;
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if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
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if (args->v0.data & 0xfff00000)
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return -EINVAL;
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ret = nvkm_outp_acquire(outp, NVKM_OUTP_PRIV);
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if (ret)
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return ret;
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ret = outp->ior->func->sense(outp->ior, args->v0.data);
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nvkm_outp_release(outp, NVKM_OUTP_PRIV);
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if (ret < 0)
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return ret;
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args->v0.load = ret;
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return 0;
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} else
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return ret;
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}
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break;
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case NV50_DISP_MTHD_V1_SOR_HDA_ELD: {
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union {
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struct nv50_disp_sor_hda_eld_v0 v0;
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} *args = data;
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struct nvkm_ior *ior = outp->ior;
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int ret = -ENOSYS;
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nvif_ioctl(object, "disp sor hda eld size %d\n", size);
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if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
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nvif_ioctl(object, "disp sor hda eld vers %d\n",
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args->v0.version);
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if (size > 0x60)
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return -E2BIG;
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} else
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return ret;
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if (!ior->func->hda.hpd)
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return -ENODEV;
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if (size && args->v0.data[0]) {
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if (outp->info.type == DCB_OUTPUT_DP)
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ior->func->dp.audio(ior, hidx, true);
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ior->func->hda.hpd(ior, hidx, true);
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ior->func->hda.eld(ior, data, size);
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} else {
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if (outp->info.type == DCB_OUTPUT_DP)
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ior->func->dp.audio(ior, hidx, false);
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ior->func->hda.hpd(ior, hidx, false);
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}
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return 0;
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}
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break;
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case NV50_DISP_MTHD_V1_SOR_HDMI_PWR: {
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union {
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struct nv50_disp_sor_hdmi_pwr_v0 v0;
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} *args = data;
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u8 *vendor, vendor_size;
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u8 *avi, avi_size;
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int ret = -ENOSYS;
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nvif_ioctl(object, "disp sor hdmi ctrl size %d\n", size);
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if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
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nvif_ioctl(object, "disp sor hdmi ctrl vers %d state %d "
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"max_ac_packet %d rekey %d\n",
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args->v0.version, args->v0.state,
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args->v0.max_ac_packet, args->v0.rekey);
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if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f)
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return -EINVAL;
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if ((args->v0.avi_infoframe_length
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+ args->v0.vendor_infoframe_length) > size)
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return -EINVAL;
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else
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if ((args->v0.avi_infoframe_length
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+ args->v0.vendor_infoframe_length) < size)
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return -E2BIG;
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avi = data;
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avi_size = args->v0.avi_infoframe_length;
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vendor = avi + avi_size;
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vendor_size = args->v0.vendor_infoframe_length;
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} else
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return ret;
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if (!outp->ior->func->hdmi.ctrl)
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return -ENODEV;
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outp->ior->func->hdmi.ctrl(outp->ior, hidx, args->v0.state,
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args->v0.max_ac_packet,
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args->v0.rekey, avi, avi_size,
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vendor, vendor_size);
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return 0;
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}
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break;
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case NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT: {
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union {
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struct nv50_disp_sor_lvds_script_v0 v0;
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} *args = data;
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int ret = -ENOSYS;
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nvif_ioctl(object, "disp sor lvds script size %d\n", size);
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if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
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nvif_ioctl(object, "disp sor lvds script "
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"vers %d name %04x\n",
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args->v0.version, args->v0.script);
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disp->sor.lvdsconf = args->v0.script;
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return 0;
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} else
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return ret;
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}
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break;
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case NV50_DISP_MTHD_V1_SOR_DP_MST_LINK: {
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struct nvkm_dp *dp = nvkm_dp(outp);
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union {
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struct nv50_disp_sor_dp_mst_link_v0 v0;
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} *args = data;
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int ret = -ENOSYS;
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nvif_ioctl(object, "disp sor dp mst link size %d\n", size);
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if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
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nvif_ioctl(object, "disp sor dp mst link vers %d state %d\n",
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args->v0.version, args->v0.state);
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dp->lt.mst = !!args->v0.state;
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return 0;
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} else
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return ret;
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}
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break;
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case NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI: {
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union {
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struct nv50_disp_sor_dp_mst_vcpi_v0 v0;
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} *args = data;
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int ret = -ENOSYS;
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nvif_ioctl(object, "disp sor dp mst vcpi size %d\n", size);
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if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
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nvif_ioctl(object, "disp sor dp mst vcpi vers %d "
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"slot %02x/%02x pbn %04x/%04x\n",
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args->v0.version, args->v0.start_slot,
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args->v0.num_slots, args->v0.pbn,
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args->v0.aligned_pbn);
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if (!outp->ior->func->dp.vcpi)
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return -ENODEV;
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outp->ior->func->dp.vcpi(outp->ior, hidx,
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args->v0.start_slot,
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args->v0.num_slots,
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args->v0.pbn,
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args->v0.aligned_pbn);
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return 0;
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} else
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return ret;
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}
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break;
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default:
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break;
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}
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return -EINVAL;
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}
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static int
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nv50_disp_root_dmac_new_(const struct nvkm_oclass *oclass,
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void *data, u32 size, struct nvkm_object **pobject)
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{
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const struct nv50_disp_dmac_oclass *sclass = oclass->priv;
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struct nv50_disp_root *root = nv50_disp_root(oclass->parent);
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return sclass->ctor(sclass->func, sclass->mthd, root, sclass->chid,
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oclass, data, size, pobject);
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}
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static int
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nv50_disp_root_pioc_new_(const struct nvkm_oclass *oclass,
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void *data, u32 size, struct nvkm_object **pobject)
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{
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const struct nv50_disp_pioc_oclass *sclass = oclass->priv;
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struct nv50_disp_root *root = nv50_disp_root(oclass->parent);
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return sclass->ctor(sclass->func, sclass->mthd, root, sclass->chid.ctrl,
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sclass->chid.user, oclass, data, size, pobject);
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}
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static int
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nv50_disp_root_child_get_(struct nvkm_object *object, int index,
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struct nvkm_oclass *sclass)
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{
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struct nv50_disp_root *root = nv50_disp_root(object);
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if (index < ARRAY_SIZE(root->func->dmac)) {
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sclass->base = root->func->dmac[index]->base;
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sclass->priv = root->func->dmac[index];
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sclass->ctor = nv50_disp_root_dmac_new_;
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return 0;
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}
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index -= ARRAY_SIZE(root->func->dmac);
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if (index < ARRAY_SIZE(root->func->pioc)) {
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sclass->base = root->func->pioc[index]->base;
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sclass->priv = root->func->pioc[index];
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sclass->ctor = nv50_disp_root_pioc_new_;
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return 0;
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}
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return -EINVAL;
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}
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static int
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nv50_disp_root_fini_(struct nvkm_object *object, bool suspend)
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{
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struct nv50_disp_root *root = nv50_disp_root(object);
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root->func->fini(root);
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return 0;
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}
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static int
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nv50_disp_root_init_(struct nvkm_object *object)
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{
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struct nv50_disp_root *root = nv50_disp_root(object);
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struct nvkm_ior *ior;
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int ret;
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ret = root->func->init(root);
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if (ret)
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return ret;
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/* Set 'normal' (ie. when it's attached to a head) state for
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* each output resource to 'fully enabled'.
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*/
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list_for_each_entry(ior, &root->disp->base.ior, head) {
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ior->func->power(ior, true, true, true, true, true);
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}
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return 0;
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}
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static void *
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nv50_disp_root_dtor_(struct nvkm_object *object)
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{
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struct nv50_disp_root *root = nv50_disp_root(object);
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nvkm_ramht_del(&root->ramht);
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nvkm_gpuobj_del(&root->instmem);
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return root;
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}
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static const struct nvkm_object_func
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nv50_disp_root_ = {
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.dtor = nv50_disp_root_dtor_,
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.init = nv50_disp_root_init_,
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.fini = nv50_disp_root_fini_,
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.mthd = nv50_disp_root_mthd_,
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.ntfy = nvkm_disp_ntfy,
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.sclass = nv50_disp_root_child_get_,
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};
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int
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nv50_disp_root_new_(const struct nv50_disp_root_func *func,
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struct nvkm_disp *base, const struct nvkm_oclass *oclass,
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void *data, u32 size, struct nvkm_object **pobject)
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{
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struct nv50_disp *disp = nv50_disp(base);
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struct nv50_disp_root *root;
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struct nvkm_device *device = disp->base.engine.subdev.device;
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int ret;
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if (!(root = kzalloc(sizeof(*root), GFP_KERNEL)))
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return -ENOMEM;
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*pobject = &root->object;
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nvkm_object_ctor(&nv50_disp_root_, oclass, &root->object);
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root->func = func;
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root->disp = disp;
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ret = nvkm_gpuobj_new(disp->base.engine.subdev.device, 0x10000, 0x10000,
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false, NULL, &root->instmem);
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if (ret)
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return ret;
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return nvkm_ramht_new(device, 0x1000, 0, root->instmem, &root->ramht);
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}
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void
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nv50_disp_root_fini(struct nv50_disp_root *root)
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{
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struct nvkm_device *device = root->disp->base.engine.subdev.device;
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/* disable all interrupts */
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nvkm_wr32(device, 0x610024, 0x00000000);
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nvkm_wr32(device, 0x610020, 0x00000000);
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}
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int
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nv50_disp_root_init(struct nv50_disp_root *root)
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{
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struct nv50_disp *disp = root->disp;
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struct nvkm_head *head;
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struct nvkm_device *device = disp->base.engine.subdev.device;
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u32 tmp;
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int i;
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/* The below segments of code copying values from one register to
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* another appear to inform EVO of the display capabilities or
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* something similar. NFI what the 0x614004 caps are for..
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*/
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tmp = nvkm_rd32(device, 0x614004);
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nvkm_wr32(device, 0x610184, tmp);
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/* ... CRTC caps */
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list_for_each_entry(head, &disp->base.head, head) {
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tmp = nvkm_rd32(device, 0x616100 + (head->id * 0x800));
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nvkm_wr32(device, 0x610190 + (head->id * 0x10), tmp);
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tmp = nvkm_rd32(device, 0x616104 + (head->id * 0x800));
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nvkm_wr32(device, 0x610194 + (head->id * 0x10), tmp);
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tmp = nvkm_rd32(device, 0x616108 + (head->id * 0x800));
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nvkm_wr32(device, 0x610198 + (head->id * 0x10), tmp);
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tmp = nvkm_rd32(device, 0x61610c + (head->id * 0x800));
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nvkm_wr32(device, 0x61019c + (head->id * 0x10), tmp);
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}
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/* ... DAC caps */
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for (i = 0; i < disp->func->dac.nr; i++) {
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tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800));
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nvkm_wr32(device, 0x6101d0 + (i * 0x04), tmp);
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}
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/* ... SOR caps */
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for (i = 0; i < disp->func->sor.nr; i++) {
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tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
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nvkm_wr32(device, 0x6101e0 + (i * 0x04), tmp);
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}
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/* ... PIOR caps */
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for (i = 0; i < disp->func->pior.nr; i++) {
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tmp = nvkm_rd32(device, 0x61e000 + (i * 0x800));
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nvkm_wr32(device, 0x6101f0 + (i * 0x04), tmp);
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}
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/* steal display away from vbios, or something like that */
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if (nvkm_rd32(device, 0x610024) & 0x00000100) {
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nvkm_wr32(device, 0x610024, 0x00000100);
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nvkm_mask(device, 0x6194e8, 0x00000001, 0x00000000);
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if (nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x6194e8) & 0x00000002))
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break;
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) < 0)
|
|
return -EBUSY;
|
|
}
|
|
|
|
/* point at display engine memory area (hash table, objects) */
|
|
nvkm_wr32(device, 0x610010, (root->instmem->addr >> 8) | 9);
|
|
|
|
/* enable supervisor interrupts, disable everything else */
|
|
nvkm_wr32(device, 0x61002c, 0x00000370);
|
|
nvkm_wr32(device, 0x610028, 0x00000000);
|
|
return 0;
|
|
}
|
|
|
|
static const struct nv50_disp_root_func
|
|
nv50_disp_root = {
|
|
.init = nv50_disp_root_init,
|
|
.fini = nv50_disp_root_fini,
|
|
.dmac = {
|
|
&nv50_disp_core_oclass,
|
|
&nv50_disp_base_oclass,
|
|
&nv50_disp_ovly_oclass,
|
|
},
|
|
.pioc = {
|
|
&nv50_disp_oimm_oclass,
|
|
&nv50_disp_curs_oclass,
|
|
},
|
|
};
|
|
|
|
static int
|
|
nv50_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
|
|
void *data, u32 size, struct nvkm_object **pobject)
|
|
{
|
|
return nv50_disp_root_new_(&nv50_disp_root, disp, oclass,
|
|
data, size, pobject);
|
|
}
|
|
|
|
const struct nvkm_disp_oclass
|
|
nv50_disp_root_oclass = {
|
|
.base.oclass = NV50_DISP,
|
|
.base.minver = -1,
|
|
.base.maxver = -1,
|
|
.ctor = nv50_disp_root_new,
|
|
};
|