889 lines
21 KiB
C
889 lines
21 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/prime_numbers.h>
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#include "../i915_selftest.h"
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#include "mock_context.h"
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#include "mock_gem_device.h"
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static int igt_add_request(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct drm_i915_gem_request *request;
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int err = -ENOMEM;
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/* Basic preliminary test to create a request and let it loose! */
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mutex_lock(&i915->drm.struct_mutex);
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request = mock_request(i915->engine[RCS],
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i915->kernel_context,
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HZ / 10);
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if (!request)
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goto out_unlock;
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i915_add_request(request);
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err = 0;
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out_unlock:
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mutex_unlock(&i915->drm.struct_mutex);
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return err;
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}
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static int igt_wait_request(void *arg)
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{
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const long T = HZ / 4;
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struct drm_i915_private *i915 = arg;
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struct drm_i915_gem_request *request;
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int err = -EINVAL;
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/* Submit a request, then wait upon it */
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mutex_lock(&i915->drm.struct_mutex);
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request = mock_request(i915->engine[RCS], i915->kernel_context, T);
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if (!request) {
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err = -ENOMEM;
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goto out_unlock;
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}
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if (i915_wait_request(request, I915_WAIT_LOCKED, 0) != -ETIME) {
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pr_err("request wait (busy query) succeeded (expected timeout before submit!)\n");
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goto out_unlock;
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}
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if (i915_wait_request(request, I915_WAIT_LOCKED, T) != -ETIME) {
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pr_err("request wait succeeded (expected timeout before submit!)\n");
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goto out_unlock;
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}
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if (i915_gem_request_completed(request)) {
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pr_err("request completed before submit!!\n");
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goto out_unlock;
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}
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i915_add_request(request);
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if (i915_wait_request(request, I915_WAIT_LOCKED, 0) != -ETIME) {
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pr_err("request wait (busy query) succeeded (expected timeout after submit!)\n");
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goto out_unlock;
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}
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if (i915_gem_request_completed(request)) {
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pr_err("request completed immediately!\n");
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goto out_unlock;
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}
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if (i915_wait_request(request, I915_WAIT_LOCKED, T / 2) != -ETIME) {
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pr_err("request wait succeeded (expected timeout!)\n");
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goto out_unlock;
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}
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if (i915_wait_request(request, I915_WAIT_LOCKED, T) == -ETIME) {
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pr_err("request wait timed out!\n");
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goto out_unlock;
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}
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if (!i915_gem_request_completed(request)) {
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pr_err("request not complete after waiting!\n");
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goto out_unlock;
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}
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if (i915_wait_request(request, I915_WAIT_LOCKED, T) == -ETIME) {
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pr_err("request wait timed out when already complete!\n");
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goto out_unlock;
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}
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err = 0;
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out_unlock:
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mock_device_flush(i915);
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mutex_unlock(&i915->drm.struct_mutex);
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return err;
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}
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static int igt_fence_wait(void *arg)
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{
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const long T = HZ / 4;
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struct drm_i915_private *i915 = arg;
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struct drm_i915_gem_request *request;
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int err = -EINVAL;
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/* Submit a request, treat it as a fence and wait upon it */
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mutex_lock(&i915->drm.struct_mutex);
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request = mock_request(i915->engine[RCS], i915->kernel_context, T);
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if (!request) {
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err = -ENOMEM;
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goto out_locked;
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}
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mutex_unlock(&i915->drm.struct_mutex); /* safe as we are single user */
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if (dma_fence_wait_timeout(&request->fence, false, T) != -ETIME) {
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pr_err("fence wait success before submit (expected timeout)!\n");
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goto out_device;
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}
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mutex_lock(&i915->drm.struct_mutex);
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i915_add_request(request);
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mutex_unlock(&i915->drm.struct_mutex);
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if (dma_fence_is_signaled(&request->fence)) {
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pr_err("fence signaled immediately!\n");
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goto out_device;
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}
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if (dma_fence_wait_timeout(&request->fence, false, T / 2) != -ETIME) {
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pr_err("fence wait success after submit (expected timeout)!\n");
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goto out_device;
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}
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if (dma_fence_wait_timeout(&request->fence, false, T) <= 0) {
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pr_err("fence wait timed out (expected success)!\n");
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goto out_device;
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}
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if (!dma_fence_is_signaled(&request->fence)) {
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pr_err("fence unsignaled after waiting!\n");
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goto out_device;
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}
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if (dma_fence_wait_timeout(&request->fence, false, T) <= 0) {
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pr_err("fence wait timed out when complete (expected success)!\n");
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goto out_device;
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}
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err = 0;
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out_device:
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mutex_lock(&i915->drm.struct_mutex);
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out_locked:
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mock_device_flush(i915);
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mutex_unlock(&i915->drm.struct_mutex);
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return err;
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}
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static int igt_request_rewind(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct drm_i915_gem_request *request, *vip;
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struct i915_gem_context *ctx[2];
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int err = -EINVAL;
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mutex_lock(&i915->drm.struct_mutex);
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ctx[0] = mock_context(i915, "A");
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request = mock_request(i915->engine[RCS], ctx[0], 2 * HZ);
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if (!request) {
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err = -ENOMEM;
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goto err_context_0;
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}
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i915_gem_request_get(request);
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i915_add_request(request);
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ctx[1] = mock_context(i915, "B");
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vip = mock_request(i915->engine[RCS], ctx[1], 0);
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if (!vip) {
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err = -ENOMEM;
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goto err_context_1;
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}
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/* Simulate preemption by manual reordering */
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if (!mock_cancel_request(request)) {
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pr_err("failed to cancel request (already executed)!\n");
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i915_add_request(vip);
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goto err_context_1;
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}
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i915_gem_request_get(vip);
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i915_add_request(vip);
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rcu_read_lock();
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request->engine->submit_request(request);
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rcu_read_unlock();
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mutex_unlock(&i915->drm.struct_mutex);
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if (i915_wait_request(vip, 0, HZ) == -ETIME) {
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pr_err("timed out waiting for high priority request, vip.seqno=%d, current seqno=%d\n",
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vip->global_seqno, intel_engine_get_seqno(i915->engine[RCS]));
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goto err;
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}
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if (i915_gem_request_completed(request)) {
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pr_err("low priority request already completed\n");
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goto err;
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}
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err = 0;
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err:
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i915_gem_request_put(vip);
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mutex_lock(&i915->drm.struct_mutex);
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err_context_1:
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mock_context_close(ctx[1]);
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i915_gem_request_put(request);
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err_context_0:
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mock_context_close(ctx[0]);
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mock_device_flush(i915);
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mutex_unlock(&i915->drm.struct_mutex);
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return err;
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}
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int i915_gem_request_mock_selftests(void)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(igt_add_request),
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SUBTEST(igt_wait_request),
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SUBTEST(igt_fence_wait),
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SUBTEST(igt_request_rewind),
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};
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struct drm_i915_private *i915;
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int err;
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i915 = mock_gem_device();
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if (!i915)
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return -ENOMEM;
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err = i915_subtests(tests, i915);
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drm_dev_unref(&i915->drm);
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return err;
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}
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struct live_test {
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struct drm_i915_private *i915;
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const char *func;
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const char *name;
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unsigned int reset_count;
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};
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static int begin_live_test(struct live_test *t,
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struct drm_i915_private *i915,
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const char *func,
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const char *name)
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{
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int err;
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t->i915 = i915;
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t->func = func;
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t->name = name;
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err = i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED);
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if (err) {
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pr_err("%s(%s): failed to idle before, with err=%d!",
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func, name, err);
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return err;
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}
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i915->gpu_error.missed_irq_rings = 0;
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t->reset_count = i915_reset_count(&i915->gpu_error);
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return 0;
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}
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static int end_live_test(struct live_test *t)
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{
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struct drm_i915_private *i915 = t->i915;
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i915_gem_retire_requests(i915);
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if (wait_for(intel_engines_are_idle(i915), 10)) {
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pr_err("%s(%s): GPU not idle\n", t->func, t->name);
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return -EIO;
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}
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if (t->reset_count != i915_reset_count(&i915->gpu_error)) {
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pr_err("%s(%s): GPU was reset %d times!\n",
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t->func, t->name,
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i915_reset_count(&i915->gpu_error) - t->reset_count);
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return -EIO;
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}
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if (i915->gpu_error.missed_irq_rings) {
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pr_err("%s(%s): Missed interrupts on engines %lx\n",
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t->func, t->name, i915->gpu_error.missed_irq_rings);
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return -EIO;
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}
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return 0;
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}
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static int live_nop_request(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct intel_engine_cs *engine;
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struct live_test t;
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unsigned int id;
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int err;
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/* Submit various sized batches of empty requests, to each engine
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* (individually), and wait for the batch to complete. We can check
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* the overhead of submitting requests to the hardware.
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*/
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mutex_lock(&i915->drm.struct_mutex);
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for_each_engine(engine, i915, id) {
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IGT_TIMEOUT(end_time);
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struct drm_i915_gem_request *request;
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unsigned long n, prime;
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ktime_t times[2] = {};
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err = begin_live_test(&t, i915, __func__, engine->name);
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if (err)
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goto out_unlock;
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for_each_prime_number_from(prime, 1, 8192) {
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times[1] = ktime_get_raw();
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for (n = 0; n < prime; n++) {
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request = i915_gem_request_alloc(engine,
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i915->kernel_context);
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if (IS_ERR(request)) {
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err = PTR_ERR(request);
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goto out_unlock;
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}
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/* This space is left intentionally blank.
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*
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* We do not actually want to perform any
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* action with this request, we just want
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* to measure the latency in allocation
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* and submission of our breadcrumbs -
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* ensuring that the bare request is sufficient
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* for the system to work (i.e. proper HEAD
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* tracking of the rings, interrupt handling,
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* etc). It also gives us the lowest bounds
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* for latency.
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*/
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i915_add_request(request);
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}
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i915_wait_request(request,
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I915_WAIT_LOCKED,
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MAX_SCHEDULE_TIMEOUT);
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times[1] = ktime_sub(ktime_get_raw(), times[1]);
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if (prime == 1)
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times[0] = times[1];
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if (__igt_timeout(end_time, NULL))
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break;
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}
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err = end_live_test(&t);
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if (err)
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goto out_unlock;
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pr_info("Request latencies on %s: 1 = %lluns, %lu = %lluns\n",
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engine->name,
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ktime_to_ns(times[0]),
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prime, div64_u64(ktime_to_ns(times[1]), prime));
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}
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out_unlock:
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mutex_unlock(&i915->drm.struct_mutex);
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return err;
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}
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static struct i915_vma *empty_batch(struct drm_i915_private *i915)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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u32 *cmd;
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int err;
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obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
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if (IS_ERR(obj))
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return ERR_CAST(obj);
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cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
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if (IS_ERR(cmd)) {
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err = PTR_ERR(cmd);
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goto err;
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}
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*cmd = MI_BATCH_BUFFER_END;
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i915_gem_chipset_flush(i915);
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i915_gem_object_unpin_map(obj);
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err = i915_gem_object_set_to_gtt_domain(obj, false);
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if (err)
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goto err;
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vma = i915_vma_instance(obj, &i915->ggtt.base, NULL);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto err;
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}
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err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_GLOBAL);
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if (err)
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goto err;
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return vma;
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err:
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i915_gem_object_put(obj);
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return ERR_PTR(err);
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}
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static struct drm_i915_gem_request *
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empty_request(struct intel_engine_cs *engine,
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struct i915_vma *batch)
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{
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struct drm_i915_gem_request *request;
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int err;
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request = i915_gem_request_alloc(engine,
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engine->i915->kernel_context);
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if (IS_ERR(request))
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return request;
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err = engine->emit_flush(request, EMIT_INVALIDATE);
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if (err)
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goto out_request;
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err = i915_switch_context(request);
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if (err)
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goto out_request;
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err = engine->emit_bb_start(request,
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batch->node.start,
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batch->node.size,
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I915_DISPATCH_SECURE);
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if (err)
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goto out_request;
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out_request:
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__i915_add_request(request, err == 0);
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return err ? ERR_PTR(err) : request;
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}
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static int live_empty_request(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct intel_engine_cs *engine;
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struct live_test t;
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struct i915_vma *batch;
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unsigned int id;
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int err = 0;
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/* Submit various sized batches of empty requests, to each engine
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* (individually), and wait for the batch to complete. We can check
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* the overhead of submitting requests to the hardware.
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*/
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mutex_lock(&i915->drm.struct_mutex);
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batch = empty_batch(i915);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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goto out_unlock;
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}
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for_each_engine(engine, i915, id) {
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IGT_TIMEOUT(end_time);
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struct drm_i915_gem_request *request;
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unsigned long n, prime;
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ktime_t times[2] = {};
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err = begin_live_test(&t, i915, __func__, engine->name);
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if (err)
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goto out_batch;
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/* Warmup / preload */
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request = empty_request(engine, batch);
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if (IS_ERR(request)) {
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err = PTR_ERR(request);
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goto out_batch;
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}
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i915_wait_request(request,
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I915_WAIT_LOCKED,
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MAX_SCHEDULE_TIMEOUT);
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for_each_prime_number_from(prime, 1, 8192) {
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times[1] = ktime_get_raw();
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for (n = 0; n < prime; n++) {
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request = empty_request(engine, batch);
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if (IS_ERR(request)) {
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err = PTR_ERR(request);
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goto out_batch;
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}
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}
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i915_wait_request(request,
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I915_WAIT_LOCKED,
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MAX_SCHEDULE_TIMEOUT);
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times[1] = ktime_sub(ktime_get_raw(), times[1]);
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if (prime == 1)
|
|
times[0] = times[1];
|
|
|
|
if (__igt_timeout(end_time, NULL))
|
|
break;
|
|
}
|
|
|
|
err = end_live_test(&t);
|
|
if (err)
|
|
goto out_batch;
|
|
|
|
pr_info("Batch latencies on %s: 1 = %lluns, %lu = %lluns\n",
|
|
engine->name,
|
|
ktime_to_ns(times[0]),
|
|
prime, div64_u64(ktime_to_ns(times[1]), prime));
|
|
}
|
|
|
|
out_batch:
|
|
i915_vma_unpin(batch);
|
|
i915_vma_put(batch);
|
|
out_unlock:
|
|
mutex_unlock(&i915->drm.struct_mutex);
|
|
return err;
|
|
}
|
|
|
|
static struct i915_vma *recursive_batch(struct drm_i915_private *i915)
|
|
{
|
|
struct i915_gem_context *ctx = i915->kernel_context;
|
|
struct i915_address_space *vm = ctx->ppgtt ? &ctx->ppgtt->base : &i915->ggtt.base;
|
|
struct drm_i915_gem_object *obj;
|
|
const int gen = INTEL_GEN(i915);
|
|
struct i915_vma *vma;
|
|
u32 *cmd;
|
|
int err;
|
|
|
|
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
|
|
if (IS_ERR(obj))
|
|
return ERR_CAST(obj);
|
|
|
|
vma = i915_vma_instance(obj, vm, NULL);
|
|
if (IS_ERR(vma)) {
|
|
err = PTR_ERR(vma);
|
|
goto err;
|
|
}
|
|
|
|
err = i915_vma_pin(vma, 0, 0, PIN_USER);
|
|
if (err)
|
|
goto err;
|
|
|
|
err = i915_gem_object_set_to_wc_domain(obj, true);
|
|
if (err)
|
|
goto err;
|
|
|
|
cmd = i915_gem_object_pin_map(obj, I915_MAP_WC);
|
|
if (IS_ERR(cmd)) {
|
|
err = PTR_ERR(cmd);
|
|
goto err;
|
|
}
|
|
|
|
if (gen >= 8) {
|
|
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
|
|
*cmd++ = lower_32_bits(vma->node.start);
|
|
*cmd++ = upper_32_bits(vma->node.start);
|
|
} else if (gen >= 6) {
|
|
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8;
|
|
*cmd++ = lower_32_bits(vma->node.start);
|
|
} else if (gen >= 4) {
|
|
*cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
|
|
*cmd++ = lower_32_bits(vma->node.start);
|
|
} else {
|
|
*cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | 1;
|
|
*cmd++ = lower_32_bits(vma->node.start);
|
|
}
|
|
*cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */
|
|
i915_gem_chipset_flush(i915);
|
|
|
|
i915_gem_object_unpin_map(obj);
|
|
|
|
return vma;
|
|
|
|
err:
|
|
i915_gem_object_put(obj);
|
|
return ERR_PTR(err);
|
|
}
|
|
|
|
static int recursive_batch_resolve(struct i915_vma *batch)
|
|
{
|
|
u32 *cmd;
|
|
|
|
cmd = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
|
|
if (IS_ERR(cmd))
|
|
return PTR_ERR(cmd);
|
|
|
|
*cmd = MI_BATCH_BUFFER_END;
|
|
i915_gem_chipset_flush(batch->vm->i915);
|
|
|
|
i915_gem_object_unpin_map(batch->obj);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int live_all_engines(void *arg)
|
|
{
|
|
struct drm_i915_private *i915 = arg;
|
|
struct intel_engine_cs *engine;
|
|
struct drm_i915_gem_request *request[I915_NUM_ENGINES];
|
|
struct i915_vma *batch;
|
|
struct live_test t;
|
|
unsigned int id;
|
|
int err;
|
|
|
|
/* Check we can submit requests to all engines simultaneously. We
|
|
* send a recursive batch to each engine - checking that we don't
|
|
* block doing so, and that they don't complete too soon.
|
|
*/
|
|
|
|
mutex_lock(&i915->drm.struct_mutex);
|
|
|
|
err = begin_live_test(&t, i915, __func__, "");
|
|
if (err)
|
|
goto out_unlock;
|
|
|
|
batch = recursive_batch(i915);
|
|
if (IS_ERR(batch)) {
|
|
err = PTR_ERR(batch);
|
|
pr_err("%s: Unable to create batch, err=%d\n", __func__, err);
|
|
goto out_unlock;
|
|
}
|
|
|
|
for_each_engine(engine, i915, id) {
|
|
request[id] = i915_gem_request_alloc(engine,
|
|
i915->kernel_context);
|
|
if (IS_ERR(request[id])) {
|
|
err = PTR_ERR(request[id]);
|
|
pr_err("%s: Request allocation failed with err=%d\n",
|
|
__func__, err);
|
|
goto out_request;
|
|
}
|
|
|
|
err = engine->emit_flush(request[id], EMIT_INVALIDATE);
|
|
GEM_BUG_ON(err);
|
|
|
|
err = i915_switch_context(request[id]);
|
|
GEM_BUG_ON(err);
|
|
|
|
err = engine->emit_bb_start(request[id],
|
|
batch->node.start,
|
|
batch->node.size,
|
|
0);
|
|
GEM_BUG_ON(err);
|
|
request[id]->batch = batch;
|
|
|
|
if (!i915_gem_object_has_active_reference(batch->obj)) {
|
|
i915_gem_object_get(batch->obj);
|
|
i915_gem_object_set_active_reference(batch->obj);
|
|
}
|
|
|
|
i915_vma_move_to_active(batch, request[id], 0);
|
|
i915_gem_request_get(request[id]);
|
|
i915_add_request(request[id]);
|
|
}
|
|
|
|
for_each_engine(engine, i915, id) {
|
|
if (i915_gem_request_completed(request[id])) {
|
|
pr_err("%s(%s): request completed too early!\n",
|
|
__func__, engine->name);
|
|
err = -EINVAL;
|
|
goto out_request;
|
|
}
|
|
}
|
|
|
|
err = recursive_batch_resolve(batch);
|
|
if (err) {
|
|
pr_err("%s: failed to resolve batch, err=%d\n", __func__, err);
|
|
goto out_request;
|
|
}
|
|
|
|
for_each_engine(engine, i915, id) {
|
|
long timeout;
|
|
|
|
timeout = i915_wait_request(request[id],
|
|
I915_WAIT_LOCKED,
|
|
MAX_SCHEDULE_TIMEOUT);
|
|
if (timeout < 0) {
|
|
err = timeout;
|
|
pr_err("%s: error waiting for request on %s, err=%d\n",
|
|
__func__, engine->name, err);
|
|
goto out_request;
|
|
}
|
|
|
|
GEM_BUG_ON(!i915_gem_request_completed(request[id]));
|
|
i915_gem_request_put(request[id]);
|
|
request[id] = NULL;
|
|
}
|
|
|
|
err = end_live_test(&t);
|
|
|
|
out_request:
|
|
for_each_engine(engine, i915, id)
|
|
if (request[id])
|
|
i915_gem_request_put(request[id]);
|
|
i915_vma_unpin(batch);
|
|
i915_vma_put(batch);
|
|
out_unlock:
|
|
mutex_unlock(&i915->drm.struct_mutex);
|
|
return err;
|
|
}
|
|
|
|
static int live_sequential_engines(void *arg)
|
|
{
|
|
struct drm_i915_private *i915 = arg;
|
|
struct drm_i915_gem_request *request[I915_NUM_ENGINES] = {};
|
|
struct drm_i915_gem_request *prev = NULL;
|
|
struct intel_engine_cs *engine;
|
|
struct live_test t;
|
|
unsigned int id;
|
|
int err;
|
|
|
|
/* Check we can submit requests to all engines sequentially, such
|
|
* that each successive request waits for the earlier ones. This
|
|
* tests that we don't execute requests out of order, even though
|
|
* they are running on independent engines.
|
|
*/
|
|
|
|
mutex_lock(&i915->drm.struct_mutex);
|
|
|
|
err = begin_live_test(&t, i915, __func__, "");
|
|
if (err)
|
|
goto out_unlock;
|
|
|
|
for_each_engine(engine, i915, id) {
|
|
struct i915_vma *batch;
|
|
|
|
batch = recursive_batch(i915);
|
|
if (IS_ERR(batch)) {
|
|
err = PTR_ERR(batch);
|
|
pr_err("%s: Unable to create batch for %s, err=%d\n",
|
|
__func__, engine->name, err);
|
|
goto out_unlock;
|
|
}
|
|
|
|
request[id] = i915_gem_request_alloc(engine,
|
|
i915->kernel_context);
|
|
if (IS_ERR(request[id])) {
|
|
err = PTR_ERR(request[id]);
|
|
pr_err("%s: Request allocation failed for %s with err=%d\n",
|
|
__func__, engine->name, err);
|
|
goto out_request;
|
|
}
|
|
|
|
if (prev) {
|
|
err = i915_gem_request_await_dma_fence(request[id],
|
|
&prev->fence);
|
|
if (err) {
|
|
i915_add_request(request[id]);
|
|
pr_err("%s: Request await failed for %s with err=%d\n",
|
|
__func__, engine->name, err);
|
|
goto out_request;
|
|
}
|
|
}
|
|
|
|
err = engine->emit_flush(request[id], EMIT_INVALIDATE);
|
|
GEM_BUG_ON(err);
|
|
|
|
err = i915_switch_context(request[id]);
|
|
GEM_BUG_ON(err);
|
|
|
|
err = engine->emit_bb_start(request[id],
|
|
batch->node.start,
|
|
batch->node.size,
|
|
0);
|
|
GEM_BUG_ON(err);
|
|
request[id]->batch = batch;
|
|
|
|
i915_vma_move_to_active(batch, request[id], 0);
|
|
i915_gem_object_set_active_reference(batch->obj);
|
|
i915_vma_get(batch);
|
|
|
|
i915_gem_request_get(request[id]);
|
|
i915_add_request(request[id]);
|
|
|
|
prev = request[id];
|
|
}
|
|
|
|
for_each_engine(engine, i915, id) {
|
|
long timeout;
|
|
|
|
if (i915_gem_request_completed(request[id])) {
|
|
pr_err("%s(%s): request completed too early!\n",
|
|
__func__, engine->name);
|
|
err = -EINVAL;
|
|
goto out_request;
|
|
}
|
|
|
|
err = recursive_batch_resolve(request[id]->batch);
|
|
if (err) {
|
|
pr_err("%s: failed to resolve batch, err=%d\n",
|
|
__func__, err);
|
|
goto out_request;
|
|
}
|
|
|
|
timeout = i915_wait_request(request[id],
|
|
I915_WAIT_LOCKED,
|
|
MAX_SCHEDULE_TIMEOUT);
|
|
if (timeout < 0) {
|
|
err = timeout;
|
|
pr_err("%s: error waiting for request on %s, err=%d\n",
|
|
__func__, engine->name, err);
|
|
goto out_request;
|
|
}
|
|
|
|
GEM_BUG_ON(!i915_gem_request_completed(request[id]));
|
|
}
|
|
|
|
err = end_live_test(&t);
|
|
|
|
out_request:
|
|
for_each_engine(engine, i915, id) {
|
|
u32 *cmd;
|
|
|
|
if (!request[id])
|
|
break;
|
|
|
|
cmd = i915_gem_object_pin_map(request[id]->batch->obj,
|
|
I915_MAP_WC);
|
|
if (!IS_ERR(cmd)) {
|
|
*cmd = MI_BATCH_BUFFER_END;
|
|
i915_gem_chipset_flush(i915);
|
|
|
|
i915_gem_object_unpin_map(request[id]->batch->obj);
|
|
}
|
|
|
|
i915_vma_put(request[id]->batch);
|
|
i915_gem_request_put(request[id]);
|
|
}
|
|
out_unlock:
|
|
mutex_unlock(&i915->drm.struct_mutex);
|
|
return err;
|
|
}
|
|
|
|
int i915_gem_request_live_selftests(struct drm_i915_private *i915)
|
|
{
|
|
static const struct i915_subtest tests[] = {
|
|
SUBTEST(live_nop_request),
|
|
SUBTEST(live_all_engines),
|
|
SUBTEST(live_sequential_engines),
|
|
SUBTEST(live_empty_request),
|
|
};
|
|
return i915_subtests(tests, i915);
|
|
}
|