1395 lines
38 KiB
C
1395 lines
38 KiB
C
/*
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* Copyright (C) 2012 Russell King
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* Rewritten from the dovefb driver, and Armada510 manuals.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_plane_helper.h>
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#include "armada_crtc.h"
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#include "armada_drm.h"
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#include "armada_fb.h"
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#include "armada_gem.h"
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#include "armada_hw.h"
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#include "armada_trace.h"
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struct armada_frame_work {
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struct armada_plane_work work;
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struct drm_pending_vblank_event *event;
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struct armada_regs regs[4];
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struct drm_framebuffer *old_fb;
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};
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enum csc_mode {
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CSC_AUTO = 0,
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CSC_YUV_CCIR601 = 1,
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CSC_YUV_CCIR709 = 2,
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CSC_RGB_COMPUTER = 1,
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CSC_RGB_STUDIO = 2,
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};
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static const uint32_t armada_primary_formats[] = {
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DRM_FORMAT_UYVY,
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DRM_FORMAT_YUYV,
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DRM_FORMAT_VYUY,
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DRM_FORMAT_YVYU,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_BGR888,
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_ABGR1555,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_BGR565,
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};
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/*
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* A note about interlacing. Let's consider HDMI 1920x1080i.
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* The timing parameters we have from X are:
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* Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
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* 1920 2448 2492 2640 1080 1084 1094 1125
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* Which get translated to:
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* Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
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* 1920 2448 2492 2640 540 542 547 562
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*
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* This is how it is defined by CEA-861-D - line and pixel numbers are
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* referenced to the rising edge of VSYNC and HSYNC. Total clocks per
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* line: 2640. The odd frame, the first active line is at line 21, and
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* the even frame, the first active line is 584.
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*
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* LN: 560 561 562 563 567 568 569
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* DE: ~~~|____________________________//__________________________
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* HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
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* VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
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* 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge).
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*
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* LN: 1123 1124 1125 1 5 6 7
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* DE: ~~~|____________________________//__________________________
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* HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
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* VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
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* 23 blanking lines
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*
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* The Armada LCD Controller line and pixel numbers are, like X timings,
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* referenced to the top left of the active frame.
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*
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* So, translating these to our LCD controller:
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* Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
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* Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
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* Note: Vsync front porch remains constant!
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*
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* if (odd_frame) {
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* vtotal = mode->crtc_vtotal + 1;
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* vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
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* vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
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* } else {
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* vtotal = mode->crtc_vtotal;
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* vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
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* vhorizpos = mode->crtc_hsync_start;
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* }
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* vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
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*
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* So, we need to reprogram these registers on each vsync event:
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* LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
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*
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* Note: we do not use the frame done interrupts because these appear
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* to happen too early, and lead to jitter on the display (presumably
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* they occur at the end of the last active line, before the vsync back
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* porch, which we're reprogramming.)
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*/
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void
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armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
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{
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while (regs->offset != ~0) {
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void __iomem *reg = dcrtc->base + regs->offset;
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uint32_t val;
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val = regs->mask;
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if (val != 0)
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val &= readl_relaxed(reg);
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writel_relaxed(val | regs->val, reg);
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++regs;
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}
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}
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#define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON)
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static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
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{
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uint32_t dumb_ctrl;
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dumb_ctrl = dcrtc->cfg_dumb_ctrl;
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if (!dpms_blanked(dcrtc->dpms))
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dumb_ctrl |= CFG_DUMB_ENA;
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/*
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* When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
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* be using SPI or GPIO. If we set this to DUMB_BLANK, we will
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* force LCD_D[23:0] to output blank color, overriding the GPIO or
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* SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode.
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*/
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if (dpms_blanked(dcrtc->dpms) &&
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(dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
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dumb_ctrl &= ~DUMB_MASK;
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dumb_ctrl |= DUMB_BLANK;
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}
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/*
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* The documentation doesn't indicate what the normal state of
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* the sync signals are. Sebastian Hesselbart kindly probed
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* these signals on his board to determine their state.
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*
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* The non-inverted state of the sync signals is active high.
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* Setting these bits makes the appropriate signal active low.
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*/
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if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
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dumb_ctrl |= CFG_INV_CSYNC;
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if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
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dumb_ctrl |= CFG_INV_HSYNC;
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if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
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dumb_ctrl |= CFG_INV_VSYNC;
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if (dcrtc->dumb_ctrl != dumb_ctrl) {
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dcrtc->dumb_ctrl = dumb_ctrl;
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writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
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}
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}
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void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb,
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int x, int y)
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{
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const struct drm_format_info *format = fb->format;
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unsigned int num_planes = format->num_planes;
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u32 addr = drm_fb_obj(fb)->dev_addr;
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int i;
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if (num_planes > 3)
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num_planes = 3;
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addrs[0] = addr + fb->offsets[0] + y * fb->pitches[0] +
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x * format->cpp[0];
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y /= format->vsub;
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x /= format->hsub;
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for (i = 1; i < num_planes; i++)
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addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] +
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x * format->cpp[i];
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for (; i < 3; i++)
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addrs[i] = 0;
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}
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static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
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int x, int y, struct armada_regs *regs, bool interlaced)
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{
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unsigned pitch = fb->pitches[0];
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u32 addrs[3], addr_odd, addr_even;
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unsigned i = 0;
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DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
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pitch, x, y, fb->format->cpp[0] * 8);
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armada_drm_plane_calc_addrs(addrs, fb, x, y);
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addr_odd = addr_even = addrs[0];
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if (interlaced) {
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addr_even += pitch;
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pitch *= 2;
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}
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/* write offset, base, and pitch */
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armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
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armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
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armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
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return i;
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}
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static void armada_drm_plane_work_run(struct armada_crtc *dcrtc,
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struct drm_plane *plane)
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{
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struct armada_plane *dplane = drm_to_armada_plane(plane);
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struct armada_plane_work *work = xchg(&dplane->work, NULL);
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/* Handle any pending frame work. */
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if (work) {
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work->fn(dcrtc, dplane, work);
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drm_crtc_vblank_put(&dcrtc->crtc);
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}
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wake_up(&dplane->frame_wait);
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}
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int armada_drm_plane_work_queue(struct armada_crtc *dcrtc,
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struct armada_plane *plane, struct armada_plane_work *work)
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{
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int ret;
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ret = drm_crtc_vblank_get(&dcrtc->crtc);
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if (ret) {
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DRM_ERROR("failed to acquire vblank counter\n");
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return ret;
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}
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ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0;
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if (ret)
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drm_crtc_vblank_put(&dcrtc->crtc);
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return ret;
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}
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int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout)
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{
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return wait_event_timeout(plane->frame_wait, !plane->work, timeout);
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}
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struct armada_plane_work *armada_drm_plane_work_cancel(
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struct armada_crtc *dcrtc, struct armada_plane *plane)
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{
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struct armada_plane_work *work = xchg(&plane->work, NULL);
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if (work)
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drm_crtc_vblank_put(&dcrtc->crtc);
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return work;
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}
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static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
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struct armada_frame_work *work)
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{
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struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary);
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return armada_drm_plane_work_queue(dcrtc, plane, &work->work);
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}
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static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc,
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struct armada_plane *plane, struct armada_plane_work *work)
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{
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struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work);
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struct drm_device *dev = dcrtc->crtc.dev;
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unsigned long flags;
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spin_lock_irqsave(&dcrtc->irq_lock, flags);
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armada_drm_crtc_update_regs(dcrtc, fwork->regs);
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spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
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if (fwork->event) {
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spin_lock_irqsave(&dev->event_lock, flags);
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drm_crtc_send_vblank_event(&dcrtc->crtc, fwork->event);
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spin_unlock_irqrestore(&dev->event_lock, flags);
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}
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/* Finally, queue the process-half of the cleanup. */
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__armada_drm_queue_unref_work(dcrtc->crtc.dev, fwork->old_fb);
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kfree(fwork);
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}
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static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
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struct drm_framebuffer *fb, bool force)
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{
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struct armada_frame_work *work;
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if (!fb)
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return;
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if (force) {
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/* Display is disabled, so just drop the old fb */
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drm_framebuffer_put(fb);
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return;
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}
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work = kmalloc(sizeof(*work), GFP_KERNEL);
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if (work) {
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int i = 0;
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work->work.fn = armada_drm_crtc_complete_frame_work;
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work->event = NULL;
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work->old_fb = fb;
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armada_reg_queue_end(work->regs, i);
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if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
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return;
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kfree(work);
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}
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/*
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* Oops - just drop the reference immediately and hope for
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* the best. The worst that will happen is the buffer gets
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* reused before it has finished being displayed.
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*/
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drm_framebuffer_put(fb);
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}
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static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
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{
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/*
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* Tell the DRM core that vblank IRQs aren't going to happen for
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* a while. This cleans up any pending vblank events for us.
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*/
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drm_crtc_vblank_off(&dcrtc->crtc);
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armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
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}
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/* The mode_config.mutex will be held for this call */
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static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
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{
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struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
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if (dpms_blanked(dcrtc->dpms) != dpms_blanked(dpms)) {
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if (dpms_blanked(dpms))
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armada_drm_vblank_off(dcrtc);
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else if (!IS_ERR(dcrtc->clk))
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WARN_ON(clk_prepare_enable(dcrtc->clk));
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dcrtc->dpms = dpms;
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armada_drm_crtc_update(dcrtc);
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if (!dpms_blanked(dpms))
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drm_crtc_vblank_on(&dcrtc->crtc);
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else if (!IS_ERR(dcrtc->clk))
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clk_disable_unprepare(dcrtc->clk);
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} else if (dcrtc->dpms != dpms) {
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dcrtc->dpms = dpms;
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}
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}
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/*
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* Prepare for a mode set. Turn off overlay to ensure that we don't end
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* up with the overlay size being bigger than the active screen size.
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* We rely upon X refreshing this state after the mode set has completed.
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*
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* The mode_config.mutex will be held for this call
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*/
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static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
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{
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struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
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struct drm_plane *plane;
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/*
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* If we have an overlay plane associated with this CRTC, disable
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* it before the modeset to avoid its coordinates being outside
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* the new mode parameters.
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*/
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plane = dcrtc->plane;
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if (plane)
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drm_plane_force_disable(plane);
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}
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/* The mode_config.mutex will be held for this call */
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static void armada_drm_crtc_commit(struct drm_crtc *crtc)
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{
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struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
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if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
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dcrtc->dpms = DRM_MODE_DPMS_ON;
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armada_drm_crtc_update(dcrtc);
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}
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}
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/* The mode_config.mutex will be held for this call */
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static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
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const struct drm_display_mode *mode, struct drm_display_mode *adj)
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{
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struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
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int ret;
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/* We can't do interlaced modes if we don't have the SPU_ADV_REG */
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if (!dcrtc->variant->has_spu_adv_reg &&
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adj->flags & DRM_MODE_FLAG_INTERLACE)
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return false;
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/* Check whether the display mode is possible */
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ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
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if (ret)
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return false;
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return true;
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}
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/* These are locked by dev->vbl_lock */
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static void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
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{
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if (dcrtc->irq_ena & mask) {
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dcrtc->irq_ena &= ~mask;
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writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
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}
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}
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static void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
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{
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if ((dcrtc->irq_ena & mask) != mask) {
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dcrtc->irq_ena |= mask;
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writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
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if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
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writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
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}
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}
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static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
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{
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void __iomem *base = dcrtc->base;
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struct drm_plane *ovl_plane;
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if (stat & DMA_FF_UNDERFLOW)
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DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
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if (stat & GRA_FF_UNDERFLOW)
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DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
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if (stat & VSYNC_IRQ)
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drm_crtc_handle_vblank(&dcrtc->crtc);
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spin_lock(&dcrtc->irq_lock);
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ovl_plane = dcrtc->plane;
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if (ovl_plane)
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armada_drm_plane_work_run(dcrtc, ovl_plane);
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if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
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int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
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uint32_t val;
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writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
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writel_relaxed(dcrtc->v[i].spu_v_h_total,
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base + LCD_SPUT_V_H_TOTAL);
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val = readl_relaxed(base + LCD_SPU_ADV_REG);
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val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
|
|
val |= dcrtc->v[i].spu_adv_reg;
|
|
writel_relaxed(val, base + LCD_SPU_ADV_REG);
|
|
}
|
|
|
|
if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
|
|
writel_relaxed(dcrtc->cursor_hw_pos,
|
|
base + LCD_SPU_HWC_OVSA_HPXL_VLN);
|
|
writel_relaxed(dcrtc->cursor_hw_sz,
|
|
base + LCD_SPU_HWC_HPXL_VLN);
|
|
armada_updatel(CFG_HWC_ENA,
|
|
CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
|
|
base + LCD_SPU_DMA_CTRL0);
|
|
dcrtc->cursor_update = false;
|
|
armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
|
|
}
|
|
|
|
spin_unlock(&dcrtc->irq_lock);
|
|
|
|
if (stat & GRA_FRAME_IRQ)
|
|
armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
|
|
}
|
|
|
|
static irqreturn_t armada_drm_irq(int irq, void *arg)
|
|
{
|
|
struct armada_crtc *dcrtc = arg;
|
|
u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
|
|
|
|
/*
|
|
* This is rediculous - rather than writing bits to clear, we
|
|
* have to set the actual status register value. This is racy.
|
|
*/
|
|
writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
|
|
|
|
trace_armada_drm_irq(&dcrtc->crtc, stat);
|
|
|
|
/* Mask out those interrupts we haven't enabled */
|
|
v = stat & dcrtc->irq_ena;
|
|
|
|
if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
|
|
armada_drm_crtc_irq(dcrtc, stat);
|
|
return IRQ_HANDLED;
|
|
}
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
|
|
{
|
|
struct drm_display_mode *adj = &dcrtc->crtc.mode;
|
|
uint32_t val = 0;
|
|
|
|
if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
|
|
val |= CFG_CSC_YUV_CCIR709;
|
|
if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
|
|
val |= CFG_CSC_RGB_STUDIO;
|
|
|
|
/*
|
|
* In auto mode, set the colorimetry, based upon the HDMI spec.
|
|
* 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
|
|
* ITU601. It may be more appropriate to set this depending on
|
|
* the source - but what if the graphic frame is YUV and the
|
|
* video frame is RGB?
|
|
*/
|
|
if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
|
|
!(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
|
|
(adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
|
|
if (dcrtc->csc_yuv_mode == CSC_AUTO)
|
|
val |= CFG_CSC_YUV_CCIR709;
|
|
}
|
|
|
|
/*
|
|
* We assume we're connected to a TV-like device, so the YUV->RGB
|
|
* conversion should produce a limited range. We should set this
|
|
* depending on the connectors attached to this CRTC, and what
|
|
* kind of device they report being connected.
|
|
*/
|
|
if (dcrtc->csc_rgb_mode == CSC_AUTO)
|
|
val |= CFG_CSC_RGB_STUDIO;
|
|
|
|
return val;
|
|
}
|
|
|
|
static void armada_drm_primary_set(struct drm_crtc *crtc,
|
|
struct drm_plane *plane, int x, int y)
|
|
{
|
|
struct armada_plane_state *state = &drm_to_armada_plane(plane)->state;
|
|
struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
|
|
struct armada_regs regs[8];
|
|
bool interlaced = dcrtc->interlaced;
|
|
unsigned i;
|
|
u32 ctrl0;
|
|
|
|
i = armada_drm_crtc_calc_fb(plane->fb, x, y, regs, interlaced);
|
|
|
|
armada_reg_queue_set(regs, i, state->dst_yx, LCD_SPU_GRA_OVSA_HPXL_VLN);
|
|
armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN);
|
|
armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN);
|
|
|
|
ctrl0 = state->ctrl0;
|
|
if (interlaced)
|
|
ctrl0 |= CFG_GRA_FTOGGLE;
|
|
|
|
armada_reg_queue_mod(regs, i, ctrl0, CFG_GRAFORMAT |
|
|
CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
|
|
CFG_SWAPYU | CFG_YUV2RGB) |
|
|
CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
|
|
LCD_SPU_DMA_CTRL0);
|
|
armada_reg_queue_end(regs, i);
|
|
armada_drm_crtc_update_regs(dcrtc, regs);
|
|
}
|
|
|
|
/* The mode_config.mutex will be held for this call */
|
|
static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
|
|
struct drm_display_mode *mode, struct drm_display_mode *adj,
|
|
int x, int y, struct drm_framebuffer *old_fb)
|
|
{
|
|
struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
|
|
struct armada_regs regs[17];
|
|
uint32_t lm, rm, tm, bm, val, sclk;
|
|
unsigned long flags;
|
|
unsigned i;
|
|
bool interlaced;
|
|
|
|
drm_framebuffer_get(crtc->primary->fb);
|
|
|
|
interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
|
|
|
|
val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
|
|
val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
|
|
val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
|
|
|
|
if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
|
|
val |= CFG_PALETTE_ENA;
|
|
|
|
drm_to_armada_plane(crtc->primary)->state.ctrl0 = val;
|
|
drm_to_armada_plane(crtc->primary)->state.src_hw =
|
|
drm_to_armada_plane(crtc->primary)->state.dst_hw =
|
|
adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
|
|
drm_to_armada_plane(crtc->primary)->state.dst_yx = 0;
|
|
|
|
i = 0;
|
|
rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
|
|
lm = adj->crtc_htotal - adj->crtc_hsync_end;
|
|
bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
|
|
tm = adj->crtc_vtotal - adj->crtc_vsync_end;
|
|
|
|
DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
|
|
adj->crtc_hdisplay,
|
|
adj->crtc_hsync_start,
|
|
adj->crtc_hsync_end,
|
|
adj->crtc_htotal, lm, rm);
|
|
DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
|
|
adj->crtc_vdisplay,
|
|
adj->crtc_vsync_start,
|
|
adj->crtc_vsync_end,
|
|
adj->crtc_vtotal, tm, bm);
|
|
|
|
/* Wait for pending flips to complete */
|
|
armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
|
|
MAX_SCHEDULE_TIMEOUT);
|
|
|
|
drm_crtc_vblank_off(crtc);
|
|
|
|
val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
|
|
if (val != dcrtc->dumb_ctrl) {
|
|
dcrtc->dumb_ctrl = val;
|
|
writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
|
|
}
|
|
|
|
/*
|
|
* If we are blanked, we would have disabled the clock. Re-enable
|
|
* it so that compute_clock() does the right thing.
|
|
*/
|
|
if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms))
|
|
WARN_ON(clk_prepare_enable(dcrtc->clk));
|
|
|
|
/* Now compute the divider for real */
|
|
dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
|
|
|
|
/* Ensure graphic fifo is enabled */
|
|
armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
|
|
armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
|
|
|
|
if (interlaced ^ dcrtc->interlaced) {
|
|
if (adj->flags & DRM_MODE_FLAG_INTERLACE)
|
|
drm_crtc_vblank_get(&dcrtc->crtc);
|
|
else
|
|
drm_crtc_vblank_put(&dcrtc->crtc);
|
|
dcrtc->interlaced = interlaced;
|
|
}
|
|
|
|
spin_lock_irqsave(&dcrtc->irq_lock, flags);
|
|
|
|
/* Even interlaced/progressive frame */
|
|
dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
|
|
adj->crtc_htotal;
|
|
dcrtc->v[1].spu_v_porch = tm << 16 | bm;
|
|
val = adj->crtc_hsync_start;
|
|
dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
|
|
dcrtc->variant->spu_adv_reg;
|
|
|
|
if (interlaced) {
|
|
/* Odd interlaced frame */
|
|
dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
|
|
(1 << 16);
|
|
dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
|
|
val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
|
|
dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
|
|
dcrtc->variant->spu_adv_reg;
|
|
} else {
|
|
dcrtc->v[0] = dcrtc->v[1];
|
|
}
|
|
|
|
val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
|
|
|
|
armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
|
|
armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
|
|
armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
|
|
armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
|
|
LCD_SPUT_V_H_TOTAL);
|
|
|
|
if (dcrtc->variant->has_spu_adv_reg) {
|
|
armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
|
|
ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
|
|
ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
|
|
}
|
|
|
|
val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
|
|
armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
|
|
|
|
val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
|
|
armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
|
|
armada_reg_queue_end(regs, i);
|
|
|
|
armada_drm_crtc_update_regs(dcrtc, regs);
|
|
|
|
armada_drm_primary_set(crtc, crtc->primary, x, y);
|
|
spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
|
|
|
|
armada_drm_crtc_update(dcrtc);
|
|
|
|
drm_crtc_vblank_on(crtc);
|
|
armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* The mode_config.mutex will be held for this call */
|
|
static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
|
|
struct drm_framebuffer *old_fb)
|
|
{
|
|
struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
|
|
struct armada_regs regs[4];
|
|
unsigned i;
|
|
|
|
i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
|
|
dcrtc->interlaced);
|
|
armada_reg_queue_end(regs, i);
|
|
|
|
/* Wait for pending flips to complete */
|
|
armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
|
|
MAX_SCHEDULE_TIMEOUT);
|
|
|
|
/* Take a reference to the new fb as we're using it */
|
|
drm_framebuffer_get(crtc->primary->fb);
|
|
|
|
/* Update the base in the CRTC */
|
|
armada_drm_crtc_update_regs(dcrtc, regs);
|
|
|
|
/* Drop our previously held reference */
|
|
armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
|
|
|
|
return 0;
|
|
}
|
|
|
|
void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc,
|
|
struct drm_plane *plane)
|
|
{
|
|
u32 sram_para1, dma_ctrl0_mask;
|
|
|
|
/*
|
|
* Drop our reference on any framebuffer attached to this plane.
|
|
* We don't need to NULL this out as drm_plane_force_disable(),
|
|
* and __setplane_internal() will do so for an overlay plane, and
|
|
* __drm_helper_disable_unused_functions() will do so for the
|
|
* primary plane.
|
|
*/
|
|
if (plane->fb)
|
|
drm_framebuffer_put(plane->fb);
|
|
|
|
/* Power down most RAMs and FIFOs if this is the primary plane */
|
|
if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
|
|
sram_para1 = CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
|
|
CFG_PDWN32x32 | CFG_PDWN64x66;
|
|
dma_ctrl0_mask = CFG_GRA_ENA;
|
|
} else {
|
|
/* Power down the Y/U/V FIFOs */
|
|
sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
|
|
dma_ctrl0_mask = CFG_DMA_ENA;
|
|
}
|
|
|
|
spin_lock_irq(&dcrtc->irq_lock);
|
|
armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0);
|
|
spin_unlock_irq(&dcrtc->irq_lock);
|
|
|
|
armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1);
|
|
}
|
|
|
|
/* The mode_config.mutex will be held for this call */
|
|
static void armada_drm_crtc_disable(struct drm_crtc *crtc)
|
|
{
|
|
struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
|
|
|
|
armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
|
|
armada_drm_crtc_plane_disable(dcrtc, crtc->primary);
|
|
}
|
|
|
|
static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
|
|
.dpms = armada_drm_crtc_dpms,
|
|
.prepare = armada_drm_crtc_prepare,
|
|
.commit = armada_drm_crtc_commit,
|
|
.mode_fixup = armada_drm_crtc_mode_fixup,
|
|
.mode_set = armada_drm_crtc_mode_set,
|
|
.mode_set_base = armada_drm_crtc_mode_set_base,
|
|
.disable = armada_drm_crtc_disable,
|
|
};
|
|
|
|
static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
|
|
unsigned stride, unsigned width, unsigned height)
|
|
{
|
|
uint32_t addr;
|
|
unsigned y;
|
|
|
|
addr = SRAM_HWC32_RAM1;
|
|
for (y = 0; y < height; y++) {
|
|
uint32_t *p = &pix[y * stride];
|
|
unsigned x;
|
|
|
|
for (x = 0; x < width; x++, p++) {
|
|
uint32_t val = *p;
|
|
|
|
val = (val & 0xff00ff00) |
|
|
(val & 0x000000ff) << 16 |
|
|
(val & 0x00ff0000) >> 16;
|
|
|
|
writel_relaxed(val,
|
|
base + LCD_SPU_SRAM_WRDAT);
|
|
writel_relaxed(addr | SRAM_WRITE,
|
|
base + LCD_SPU_SRAM_CTRL);
|
|
readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
|
|
addr += 1;
|
|
if ((addr & 0x00ff) == 0)
|
|
addr += 0xf00;
|
|
if ((addr & 0x30ff) == 0)
|
|
addr = SRAM_HWC32_RAM2;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void armada_drm_crtc_cursor_tran(void __iomem *base)
|
|
{
|
|
unsigned addr;
|
|
|
|
for (addr = 0; addr < 256; addr++) {
|
|
/* write the default value */
|
|
writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
|
|
writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
|
|
base + LCD_SPU_SRAM_CTRL);
|
|
}
|
|
}
|
|
|
|
static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
|
|
{
|
|
uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
|
|
uint32_t yoff, yscr, h = dcrtc->cursor_h;
|
|
uint32_t para1;
|
|
|
|
/*
|
|
* Calculate the visible width and height of the cursor,
|
|
* screen position, and the position in the cursor bitmap.
|
|
*/
|
|
if (dcrtc->cursor_x < 0) {
|
|
xoff = -dcrtc->cursor_x;
|
|
xscr = 0;
|
|
w -= min(xoff, w);
|
|
} else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
|
|
xoff = 0;
|
|
xscr = dcrtc->cursor_x;
|
|
w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
|
|
} else {
|
|
xoff = 0;
|
|
xscr = dcrtc->cursor_x;
|
|
}
|
|
|
|
if (dcrtc->cursor_y < 0) {
|
|
yoff = -dcrtc->cursor_y;
|
|
yscr = 0;
|
|
h -= min(yoff, h);
|
|
} else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
|
|
yoff = 0;
|
|
yscr = dcrtc->cursor_y;
|
|
h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
|
|
} else {
|
|
yoff = 0;
|
|
yscr = dcrtc->cursor_y;
|
|
}
|
|
|
|
/* On interlaced modes, the vertical cursor size must be halved */
|
|
s = dcrtc->cursor_w;
|
|
if (dcrtc->interlaced) {
|
|
s *= 2;
|
|
yscr /= 2;
|
|
h /= 2;
|
|
}
|
|
|
|
if (!dcrtc->cursor_obj || !h || !w) {
|
|
spin_lock_irq(&dcrtc->irq_lock);
|
|
armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
|
|
dcrtc->cursor_update = false;
|
|
armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
|
|
spin_unlock_irq(&dcrtc->irq_lock);
|
|
return 0;
|
|
}
|
|
|
|
para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
|
|
armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
|
|
dcrtc->base + LCD_SPU_SRAM_PARA1);
|
|
|
|
/*
|
|
* Initialize the transparency if the SRAM was powered down.
|
|
* We must also reload the cursor data as well.
|
|
*/
|
|
if (!(para1 & CFG_CSB_256x32)) {
|
|
armada_drm_crtc_cursor_tran(dcrtc->base);
|
|
reload = true;
|
|
}
|
|
|
|
if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
|
|
spin_lock_irq(&dcrtc->irq_lock);
|
|
armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
|
|
dcrtc->cursor_update = false;
|
|
armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
|
|
spin_unlock_irq(&dcrtc->irq_lock);
|
|
reload = true;
|
|
}
|
|
if (reload) {
|
|
struct armada_gem_object *obj = dcrtc->cursor_obj;
|
|
uint32_t *pix;
|
|
/* Set the top-left corner of the cursor image */
|
|
pix = obj->addr;
|
|
pix += yoff * s + xoff;
|
|
armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
|
|
}
|
|
|
|
/* Reload the cursor position, size and enable in the IRQ handler */
|
|
spin_lock_irq(&dcrtc->irq_lock);
|
|
dcrtc->cursor_hw_pos = yscr << 16 | xscr;
|
|
dcrtc->cursor_hw_sz = h << 16 | w;
|
|
dcrtc->cursor_update = true;
|
|
armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
|
|
spin_unlock_irq(&dcrtc->irq_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void cursor_update(void *data)
|
|
{
|
|
armada_drm_crtc_cursor_update(data, true);
|
|
}
|
|
|
|
static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
|
|
struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
|
|
{
|
|
struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
|
|
struct armada_gem_object *obj = NULL;
|
|
int ret;
|
|
|
|
/* If no cursor support, replicate drm's return value */
|
|
if (!dcrtc->variant->has_spu_adv_reg)
|
|
return -ENXIO;
|
|
|
|
if (handle && w > 0 && h > 0) {
|
|
/* maximum size is 64x32 or 32x64 */
|
|
if (w > 64 || h > 64 || (w > 32 && h > 32))
|
|
return -ENOMEM;
|
|
|
|
obj = armada_gem_object_lookup(file, handle);
|
|
if (!obj)
|
|
return -ENOENT;
|
|
|
|
/* Must be a kernel-mapped object */
|
|
if (!obj->addr) {
|
|
drm_gem_object_put_unlocked(&obj->obj);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (obj->obj.size < w * h * 4) {
|
|
DRM_ERROR("buffer is too small\n");
|
|
drm_gem_object_put_unlocked(&obj->obj);
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
if (dcrtc->cursor_obj) {
|
|
dcrtc->cursor_obj->update = NULL;
|
|
dcrtc->cursor_obj->update_data = NULL;
|
|
drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
|
|
}
|
|
dcrtc->cursor_obj = obj;
|
|
dcrtc->cursor_w = w;
|
|
dcrtc->cursor_h = h;
|
|
ret = armada_drm_crtc_cursor_update(dcrtc, true);
|
|
if (obj) {
|
|
obj->update_data = dcrtc;
|
|
obj->update = cursor_update;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
|
|
{
|
|
struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
|
|
int ret;
|
|
|
|
/* If no cursor support, replicate drm's return value */
|
|
if (!dcrtc->variant->has_spu_adv_reg)
|
|
return -EFAULT;
|
|
|
|
dcrtc->cursor_x = x;
|
|
dcrtc->cursor_y = y;
|
|
ret = armada_drm_crtc_cursor_update(dcrtc, false);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
|
|
{
|
|
struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
|
|
struct armada_private *priv = crtc->dev->dev_private;
|
|
|
|
if (dcrtc->cursor_obj)
|
|
drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
|
|
|
|
priv->dcrtc[dcrtc->num] = NULL;
|
|
drm_crtc_cleanup(&dcrtc->crtc);
|
|
|
|
if (!IS_ERR(dcrtc->clk))
|
|
clk_disable_unprepare(dcrtc->clk);
|
|
|
|
writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
|
|
|
|
of_node_put(dcrtc->crtc.port);
|
|
|
|
kfree(dcrtc);
|
|
}
|
|
|
|
/*
|
|
* The mode_config lock is held here, to prevent races between this
|
|
* and a mode_set.
|
|
*/
|
|
static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
|
|
struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags,
|
|
struct drm_modeset_acquire_ctx *ctx)
|
|
{
|
|
struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
|
|
struct armada_frame_work *work;
|
|
unsigned i;
|
|
int ret;
|
|
|
|
/* We don't support changing the pixel format */
|
|
if (fb->format != crtc->primary->fb->format)
|
|
return -EINVAL;
|
|
|
|
work = kmalloc(sizeof(*work), GFP_KERNEL);
|
|
if (!work)
|
|
return -ENOMEM;
|
|
|
|
work->work.fn = armada_drm_crtc_complete_frame_work;
|
|
work->event = event;
|
|
work->old_fb = dcrtc->crtc.primary->fb;
|
|
|
|
i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
|
|
dcrtc->interlaced);
|
|
armada_reg_queue_end(work->regs, i);
|
|
|
|
/*
|
|
* Ensure that we hold a reference on the new framebuffer.
|
|
* This has to match the behaviour in mode_set.
|
|
*/
|
|
drm_framebuffer_get(fb);
|
|
|
|
ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
|
|
if (ret) {
|
|
/* Undo our reference above */
|
|
drm_framebuffer_put(fb);
|
|
kfree(work);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Don't take a reference on the new framebuffer;
|
|
* drm_mode_page_flip_ioctl() has already grabbed a reference and
|
|
* will _not_ drop that reference on successful return from this
|
|
* function. Simply mark this new framebuffer as the current one.
|
|
*/
|
|
dcrtc->crtc.primary->fb = fb;
|
|
|
|
/*
|
|
* Finally, if the display is blanked, we won't receive an
|
|
* interrupt, so complete it now.
|
|
*/
|
|
if (dpms_blanked(dcrtc->dpms))
|
|
armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
armada_drm_crtc_set_property(struct drm_crtc *crtc,
|
|
struct drm_property *property, uint64_t val)
|
|
{
|
|
struct armada_private *priv = crtc->dev->dev_private;
|
|
struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
|
|
bool update_csc = false;
|
|
|
|
if (property == priv->csc_yuv_prop) {
|
|
dcrtc->csc_yuv_mode = val;
|
|
update_csc = true;
|
|
} else if (property == priv->csc_rgb_prop) {
|
|
dcrtc->csc_rgb_mode = val;
|
|
update_csc = true;
|
|
}
|
|
|
|
if (update_csc) {
|
|
uint32_t val;
|
|
|
|
val = dcrtc->spu_iopad_ctrl |
|
|
armada_drm_crtc_calculate_csc(dcrtc);
|
|
writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* These are called under the vbl_lock. */
|
|
static int armada_drm_crtc_enable_vblank(struct drm_crtc *crtc)
|
|
{
|
|
struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
|
|
|
|
armada_drm_crtc_enable_irq(dcrtc, VSYNC_IRQ_ENA);
|
|
return 0;
|
|
}
|
|
|
|
static void armada_drm_crtc_disable_vblank(struct drm_crtc *crtc)
|
|
{
|
|
struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
|
|
|
|
armada_drm_crtc_disable_irq(dcrtc, VSYNC_IRQ_ENA);
|
|
}
|
|
|
|
static const struct drm_crtc_funcs armada_crtc_funcs = {
|
|
.cursor_set = armada_drm_crtc_cursor_set,
|
|
.cursor_move = armada_drm_crtc_cursor_move,
|
|
.destroy = armada_drm_crtc_destroy,
|
|
.set_config = drm_crtc_helper_set_config,
|
|
.page_flip = armada_drm_crtc_page_flip,
|
|
.set_property = armada_drm_crtc_set_property,
|
|
.enable_vblank = armada_drm_crtc_enable_vblank,
|
|
.disable_vblank = armada_drm_crtc_disable_vblank,
|
|
};
|
|
|
|
static const struct drm_plane_funcs armada_primary_plane_funcs = {
|
|
.update_plane = drm_primary_helper_update,
|
|
.disable_plane = drm_primary_helper_disable,
|
|
.destroy = drm_primary_helper_destroy,
|
|
};
|
|
|
|
int armada_drm_plane_init(struct armada_plane *plane)
|
|
{
|
|
init_waitqueue_head(&plane->frame_wait);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
|
|
{ CSC_AUTO, "Auto" },
|
|
{ CSC_YUV_CCIR601, "CCIR601" },
|
|
{ CSC_YUV_CCIR709, "CCIR709" },
|
|
};
|
|
|
|
static const struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
|
|
{ CSC_AUTO, "Auto" },
|
|
{ CSC_RGB_COMPUTER, "Computer system" },
|
|
{ CSC_RGB_STUDIO, "Studio" },
|
|
};
|
|
|
|
static int armada_drm_crtc_create_properties(struct drm_device *dev)
|
|
{
|
|
struct armada_private *priv = dev->dev_private;
|
|
|
|
if (priv->csc_yuv_prop)
|
|
return 0;
|
|
|
|
priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
|
|
"CSC_YUV", armada_drm_csc_yuv_enum_list,
|
|
ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
|
|
priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
|
|
"CSC_RGB", armada_drm_csc_rgb_enum_list,
|
|
ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
|
|
|
|
if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
|
|
return -ENOMEM;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
|
|
struct resource *res, int irq, const struct armada_variant *variant,
|
|
struct device_node *port)
|
|
{
|
|
struct armada_private *priv = drm->dev_private;
|
|
struct armada_crtc *dcrtc;
|
|
struct armada_plane *primary;
|
|
void __iomem *base;
|
|
int ret;
|
|
|
|
ret = armada_drm_crtc_create_properties(drm);
|
|
if (ret)
|
|
return ret;
|
|
|
|
base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
|
|
if (!dcrtc) {
|
|
DRM_ERROR("failed to allocate Armada crtc\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (dev != drm->dev)
|
|
dev_set_drvdata(dev, dcrtc);
|
|
|
|
dcrtc->variant = variant;
|
|
dcrtc->base = base;
|
|
dcrtc->num = drm->mode_config.num_crtc;
|
|
dcrtc->clk = ERR_PTR(-EINVAL);
|
|
dcrtc->csc_yuv_mode = CSC_AUTO;
|
|
dcrtc->csc_rgb_mode = CSC_AUTO;
|
|
dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
|
|
dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
|
|
spin_lock_init(&dcrtc->irq_lock);
|
|
dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
|
|
|
|
/* Initialize some registers which we don't otherwise set */
|
|
writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
|
|
writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
|
|
writel_relaxed(dcrtc->spu_iopad_ctrl,
|
|
dcrtc->base + LCD_SPU_IOPAD_CONTROL);
|
|
writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
|
|
writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
|
|
CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
|
|
CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
|
|
writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
|
|
writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
|
|
writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
|
|
|
|
ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
|
|
dcrtc);
|
|
if (ret < 0)
|
|
goto err_crtc;
|
|
|
|
if (dcrtc->variant->init) {
|
|
ret = dcrtc->variant->init(dcrtc, dev);
|
|
if (ret)
|
|
goto err_crtc;
|
|
}
|
|
|
|
/* Ensure AXI pipeline is enabled */
|
|
armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
|
|
|
|
priv->dcrtc[dcrtc->num] = dcrtc;
|
|
|
|
dcrtc->crtc.port = port;
|
|
|
|
primary = kzalloc(sizeof(*primary), GFP_KERNEL);
|
|
if (!primary) {
|
|
ret = -ENOMEM;
|
|
goto err_crtc;
|
|
}
|
|
|
|
ret = armada_drm_plane_init(primary);
|
|
if (ret) {
|
|
kfree(primary);
|
|
goto err_crtc;
|
|
}
|
|
|
|
ret = drm_universal_plane_init(drm, &primary->base, 0,
|
|
&armada_primary_plane_funcs,
|
|
armada_primary_formats,
|
|
ARRAY_SIZE(armada_primary_formats),
|
|
NULL,
|
|
DRM_PLANE_TYPE_PRIMARY, NULL);
|
|
if (ret) {
|
|
kfree(primary);
|
|
goto err_crtc;
|
|
}
|
|
|
|
ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL,
|
|
&armada_crtc_funcs, NULL);
|
|
if (ret)
|
|
goto err_crtc_init;
|
|
|
|
drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
|
|
|
|
drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
|
|
dcrtc->csc_yuv_mode);
|
|
drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
|
|
dcrtc->csc_rgb_mode);
|
|
|
|
return armada_overlay_plane_create(drm, 1 << dcrtc->num);
|
|
|
|
err_crtc_init:
|
|
primary->base.funcs->destroy(&primary->base);
|
|
err_crtc:
|
|
kfree(dcrtc);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
armada_lcd_bind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct drm_device *drm = data;
|
|
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
int irq = platform_get_irq(pdev, 0);
|
|
const struct armada_variant *variant;
|
|
struct device_node *port = NULL;
|
|
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
if (!dev->of_node) {
|
|
const struct platform_device_id *id;
|
|
|
|
id = platform_get_device_id(pdev);
|
|
if (!id)
|
|
return -ENXIO;
|
|
|
|
variant = (const struct armada_variant *)id->driver_data;
|
|
} else {
|
|
const struct of_device_id *match;
|
|
struct device_node *np, *parent = dev->of_node;
|
|
|
|
match = of_match_device(dev->driver->of_match_table, dev);
|
|
if (!match)
|
|
return -ENXIO;
|
|
|
|
np = of_get_child_by_name(parent, "ports");
|
|
if (np)
|
|
parent = np;
|
|
port = of_get_child_by_name(parent, "port");
|
|
of_node_put(np);
|
|
if (!port) {
|
|
dev_err(dev, "no port node found in %pOF\n", parent);
|
|
return -ENXIO;
|
|
}
|
|
|
|
variant = match->data;
|
|
}
|
|
|
|
return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
|
|
}
|
|
|
|
static void
|
|
armada_lcd_unbind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct armada_crtc *dcrtc = dev_get_drvdata(dev);
|
|
|
|
armada_drm_crtc_destroy(&dcrtc->crtc);
|
|
}
|
|
|
|
static const struct component_ops armada_lcd_ops = {
|
|
.bind = armada_lcd_bind,
|
|
.unbind = armada_lcd_unbind,
|
|
};
|
|
|
|
static int armada_lcd_probe(struct platform_device *pdev)
|
|
{
|
|
return component_add(&pdev->dev, &armada_lcd_ops);
|
|
}
|
|
|
|
static int armada_lcd_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &armada_lcd_ops);
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id armada_lcd_of_match[] = {
|
|
{
|
|
.compatible = "marvell,dove-lcd",
|
|
.data = &armada510_ops,
|
|
},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
|
|
|
|
static const struct platform_device_id armada_lcd_platform_ids[] = {
|
|
{
|
|
.name = "armada-lcd",
|
|
.driver_data = (unsigned long)&armada510_ops,
|
|
}, {
|
|
.name = "armada-510-lcd",
|
|
.driver_data = (unsigned long)&armada510_ops,
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
|
|
|
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struct platform_driver armada_lcd_platform_driver = {
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.probe = armada_lcd_probe,
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.remove = armada_lcd_remove,
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.driver = {
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.name = "armada-lcd",
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.owner = THIS_MODULE,
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.of_match_table = armada_lcd_of_match,
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},
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.id_table = armada_lcd_platform_ids,
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};
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