457 lines
12 KiB
C
457 lines
12 KiB
C
/*
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* sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
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*
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* Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
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*
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* Core file which registers crypto algorithms supported by the SS.
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*
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* You could find a link for the datasheet in Documentation/arm/sunxi/README
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/crypto.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <crypto/scatterwalk.h>
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#include <linux/scatterlist.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/reset.h>
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#include "sun4i-ss.h"
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static struct sun4i_ss_alg_template ss_algs[] = {
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{ .type = CRYPTO_ALG_TYPE_AHASH,
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.mode = SS_OP_MD5,
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.alg.hash = {
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.init = sun4i_hash_init,
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.update = sun4i_hash_update,
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.final = sun4i_hash_final,
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.finup = sun4i_hash_finup,
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.digest = sun4i_hash_digest,
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.export = sun4i_hash_export_md5,
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.import = sun4i_hash_import_md5,
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.halg = {
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.digestsize = MD5_DIGEST_SIZE,
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.statesize = sizeof(struct md5_state),
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.base = {
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.cra_name = "md5",
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.cra_driver_name = "md5-sun4i-ss",
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.cra_priority = 300,
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.cra_alignmask = 3,
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.cra_flags = CRYPTO_ALG_TYPE_AHASH,
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.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
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.cra_ctxsize = sizeof(struct sun4i_req_ctx),
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.cra_module = THIS_MODULE,
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.cra_type = &crypto_ahash_type,
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.cra_init = sun4i_hash_crainit
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}
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}
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}
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},
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{ .type = CRYPTO_ALG_TYPE_AHASH,
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.mode = SS_OP_SHA1,
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.alg.hash = {
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.init = sun4i_hash_init,
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.update = sun4i_hash_update,
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.final = sun4i_hash_final,
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.finup = sun4i_hash_finup,
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.digest = sun4i_hash_digest,
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.export = sun4i_hash_export_sha1,
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.import = sun4i_hash_import_sha1,
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.halg = {
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.digestsize = SHA1_DIGEST_SIZE,
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.statesize = sizeof(struct sha1_state),
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.base = {
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.cra_name = "sha1",
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.cra_driver_name = "sha1-sun4i-ss",
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.cra_priority = 300,
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.cra_alignmask = 3,
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.cra_flags = CRYPTO_ALG_TYPE_AHASH,
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.cra_blocksize = SHA1_BLOCK_SIZE,
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.cra_ctxsize = sizeof(struct sun4i_req_ctx),
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.cra_module = THIS_MODULE,
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.cra_type = &crypto_ahash_type,
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.cra_init = sun4i_hash_crainit
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}
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}
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}
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},
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{ .type = CRYPTO_ALG_TYPE_SKCIPHER,
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.alg.crypto = {
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.setkey = sun4i_ss_aes_setkey,
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.encrypt = sun4i_ss_cbc_aes_encrypt,
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.decrypt = sun4i_ss_cbc_aes_decrypt,
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.min_keysize = AES_MIN_KEY_SIZE,
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.max_keysize = AES_MAX_KEY_SIZE,
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.ivsize = AES_BLOCK_SIZE,
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.base = {
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.cra_name = "cbc(aes)",
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.cra_driver_name = "cbc-aes-sun4i-ss",
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.cra_priority = 300,
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.cra_blocksize = AES_BLOCK_SIZE,
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.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
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CRYPTO_ALG_KERN_DRIVER_ONLY,
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.cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
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.cra_module = THIS_MODULE,
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.cra_alignmask = 3,
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.cra_init = sun4i_ss_cipher_init,
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}
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}
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},
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{ .type = CRYPTO_ALG_TYPE_SKCIPHER,
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.alg.crypto = {
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.setkey = sun4i_ss_aes_setkey,
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.encrypt = sun4i_ss_ecb_aes_encrypt,
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.decrypt = sun4i_ss_ecb_aes_decrypt,
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.min_keysize = AES_MIN_KEY_SIZE,
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.max_keysize = AES_MAX_KEY_SIZE,
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.ivsize = AES_BLOCK_SIZE,
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.base = {
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.cra_name = "ecb(aes)",
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.cra_driver_name = "ecb-aes-sun4i-ss",
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.cra_priority = 300,
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.cra_blocksize = AES_BLOCK_SIZE,
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.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
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CRYPTO_ALG_KERN_DRIVER_ONLY,
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.cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
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.cra_module = THIS_MODULE,
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.cra_alignmask = 3,
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.cra_init = sun4i_ss_cipher_init,
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}
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}
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},
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{ .type = CRYPTO_ALG_TYPE_SKCIPHER,
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.alg.crypto = {
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.setkey = sun4i_ss_des_setkey,
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.encrypt = sun4i_ss_cbc_des_encrypt,
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.decrypt = sun4i_ss_cbc_des_decrypt,
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.min_keysize = DES_KEY_SIZE,
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.max_keysize = DES_KEY_SIZE,
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.ivsize = DES_BLOCK_SIZE,
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.base = {
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.cra_name = "cbc(des)",
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.cra_driver_name = "cbc-des-sun4i-ss",
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.cra_priority = 300,
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.cra_blocksize = DES_BLOCK_SIZE,
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.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
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CRYPTO_ALG_KERN_DRIVER_ONLY,
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.cra_ctxsize = sizeof(struct sun4i_req_ctx),
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.cra_module = THIS_MODULE,
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.cra_alignmask = 3,
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.cra_init = sun4i_ss_cipher_init,
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}
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}
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},
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{ .type = CRYPTO_ALG_TYPE_SKCIPHER,
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.alg.crypto = {
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.setkey = sun4i_ss_des_setkey,
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.encrypt = sun4i_ss_ecb_des_encrypt,
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.decrypt = sun4i_ss_ecb_des_decrypt,
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.min_keysize = DES_KEY_SIZE,
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.max_keysize = DES_KEY_SIZE,
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.base = {
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.cra_name = "ecb(des)",
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.cra_driver_name = "ecb-des-sun4i-ss",
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.cra_priority = 300,
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.cra_blocksize = DES_BLOCK_SIZE,
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.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
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CRYPTO_ALG_KERN_DRIVER_ONLY,
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.cra_ctxsize = sizeof(struct sun4i_req_ctx),
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.cra_module = THIS_MODULE,
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.cra_alignmask = 3,
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.cra_init = sun4i_ss_cipher_init,
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}
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}
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},
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{ .type = CRYPTO_ALG_TYPE_SKCIPHER,
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.alg.crypto = {
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.setkey = sun4i_ss_des3_setkey,
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.encrypt = sun4i_ss_cbc_des3_encrypt,
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.decrypt = sun4i_ss_cbc_des3_decrypt,
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.min_keysize = DES3_EDE_KEY_SIZE,
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.max_keysize = DES3_EDE_KEY_SIZE,
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.ivsize = DES3_EDE_BLOCK_SIZE,
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.base = {
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.cra_name = "cbc(des3_ede)",
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.cra_driver_name = "cbc-des3-sun4i-ss",
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.cra_priority = 300,
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.cra_blocksize = DES3_EDE_BLOCK_SIZE,
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.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
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CRYPTO_ALG_KERN_DRIVER_ONLY,
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.cra_ctxsize = sizeof(struct sun4i_req_ctx),
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.cra_module = THIS_MODULE,
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.cra_alignmask = 3,
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.cra_init = sun4i_ss_cipher_init,
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}
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}
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},
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{ .type = CRYPTO_ALG_TYPE_SKCIPHER,
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.alg.crypto = {
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.setkey = sun4i_ss_des3_setkey,
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.encrypt = sun4i_ss_ecb_des3_encrypt,
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.decrypt = sun4i_ss_ecb_des3_decrypt,
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.min_keysize = DES3_EDE_KEY_SIZE,
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.max_keysize = DES3_EDE_KEY_SIZE,
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.ivsize = DES3_EDE_BLOCK_SIZE,
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.base = {
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.cra_name = "ecb(des3_ede)",
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.cra_driver_name = "ecb-des3-sun4i-ss",
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.cra_priority = 300,
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.cra_blocksize = DES3_EDE_BLOCK_SIZE,
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.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER,
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.cra_ctxsize = sizeof(struct sun4i_req_ctx),
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.cra_module = THIS_MODULE,
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.cra_alignmask = 3,
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.cra_init = sun4i_ss_cipher_init,
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}
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}
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},
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#ifdef CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG
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{
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.type = CRYPTO_ALG_TYPE_RNG,
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.alg.rng = {
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.base = {
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.cra_name = "stdrng",
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.cra_driver_name = "sun4i_ss_rng",
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.cra_priority = 300,
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.cra_ctxsize = 0,
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.cra_module = THIS_MODULE,
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},
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.generate = sun4i_ss_prng_generate,
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.seed = sun4i_ss_prng_seed,
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.seedsize = SS_SEED_LEN / BITS_PER_BYTE,
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}
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},
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#endif
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};
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static int sun4i_ss_probe(struct platform_device *pdev)
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{
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struct resource *res;
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u32 v;
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int err, i;
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unsigned long cr;
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const unsigned long cr_ahb = 24 * 1000 * 1000;
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const unsigned long cr_mod = 150 * 1000 * 1000;
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struct sun4i_ss_ctx *ss;
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if (!pdev->dev.of_node)
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return -ENODEV;
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ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL);
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if (!ss)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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ss->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(ss->base)) {
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dev_err(&pdev->dev, "Cannot request MMIO\n");
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return PTR_ERR(ss->base);
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}
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ss->ssclk = devm_clk_get(&pdev->dev, "mod");
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if (IS_ERR(ss->ssclk)) {
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err = PTR_ERR(ss->ssclk);
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dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err);
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return err;
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}
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dev_dbg(&pdev->dev, "clock ss acquired\n");
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ss->busclk = devm_clk_get(&pdev->dev, "ahb");
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if (IS_ERR(ss->busclk)) {
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err = PTR_ERR(ss->busclk);
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dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err);
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return err;
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}
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dev_dbg(&pdev->dev, "clock ahb_ss acquired\n");
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ss->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
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if (IS_ERR(ss->reset)) {
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if (PTR_ERR(ss->reset) == -EPROBE_DEFER)
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return PTR_ERR(ss->reset);
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dev_info(&pdev->dev, "no reset control found\n");
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ss->reset = NULL;
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}
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/* Enable both clocks */
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err = clk_prepare_enable(ss->busclk);
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if (err) {
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dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
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return err;
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}
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err = clk_prepare_enable(ss->ssclk);
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if (err) {
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dev_err(&pdev->dev, "Cannot prepare_enable ssclk\n");
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goto error_ssclk;
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}
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/*
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* Check that clock have the correct rates given in the datasheet
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* Try to set the clock to the maximum allowed
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*/
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err = clk_set_rate(ss->ssclk, cr_mod);
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if (err) {
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dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n");
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goto error_clk;
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}
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/* Deassert reset if we have a reset control */
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if (ss->reset) {
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err = reset_control_deassert(ss->reset);
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if (err) {
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dev_err(&pdev->dev, "Cannot deassert reset control\n");
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goto error_clk;
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}
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}
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/*
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* The only impact on clocks below requirement are bad performance,
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* so do not print "errors"
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* warn on Overclocked clocks
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*/
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cr = clk_get_rate(ss->busclk);
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if (cr >= cr_ahb)
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dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
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cr, cr / 1000000, cr_ahb);
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else
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dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
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cr, cr / 1000000, cr_ahb);
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cr = clk_get_rate(ss->ssclk);
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if (cr <= cr_mod)
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if (cr < cr_mod)
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dev_warn(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
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cr, cr / 1000000, cr_mod);
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else
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dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
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cr, cr / 1000000, cr_mod);
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else
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dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n",
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cr, cr / 1000000, cr_mod);
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/*
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* Datasheet named it "Die Bonding ID"
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* I expect to be a sort of Security System Revision number.
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* Since the A80 seems to have an other version of SS
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* this info could be useful
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*/
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writel(SS_ENABLED, ss->base + SS_CTL);
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v = readl(ss->base + SS_CTL);
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v >>= 16;
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v &= 0x07;
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dev_info(&pdev->dev, "Die ID %d\n", v);
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writel(0, ss->base + SS_CTL);
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ss->dev = &pdev->dev;
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spin_lock_init(&ss->slock);
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for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
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ss_algs[i].ss = ss;
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switch (ss_algs[i].type) {
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case CRYPTO_ALG_TYPE_SKCIPHER:
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err = crypto_register_skcipher(&ss_algs[i].alg.crypto);
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if (err) {
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dev_err(ss->dev, "Fail to register %s\n",
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ss_algs[i].alg.crypto.base.cra_name);
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goto error_alg;
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}
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break;
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case CRYPTO_ALG_TYPE_AHASH:
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err = crypto_register_ahash(&ss_algs[i].alg.hash);
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if (err) {
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dev_err(ss->dev, "Fail to register %s\n",
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ss_algs[i].alg.hash.halg.base.cra_name);
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goto error_alg;
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}
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break;
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case CRYPTO_ALG_TYPE_RNG:
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err = crypto_register_rng(&ss_algs[i].alg.rng);
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if (err) {
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dev_err(ss->dev, "Fail to register %s\n",
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ss_algs[i].alg.rng.base.cra_name);
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}
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break;
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}
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}
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platform_set_drvdata(pdev, ss);
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return 0;
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error_alg:
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i--;
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for (; i >= 0; i--) {
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switch (ss_algs[i].type) {
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case CRYPTO_ALG_TYPE_SKCIPHER:
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crypto_unregister_skcipher(&ss_algs[i].alg.crypto);
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break;
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case CRYPTO_ALG_TYPE_AHASH:
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crypto_unregister_ahash(&ss_algs[i].alg.hash);
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break;
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case CRYPTO_ALG_TYPE_RNG:
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crypto_unregister_rng(&ss_algs[i].alg.rng);
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break;
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}
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}
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if (ss->reset)
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reset_control_assert(ss->reset);
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error_clk:
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clk_disable_unprepare(ss->ssclk);
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error_ssclk:
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clk_disable_unprepare(ss->busclk);
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return err;
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}
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static int sun4i_ss_remove(struct platform_device *pdev)
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{
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int i;
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struct sun4i_ss_ctx *ss = platform_get_drvdata(pdev);
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for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
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switch (ss_algs[i].type) {
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case CRYPTO_ALG_TYPE_SKCIPHER:
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crypto_unregister_skcipher(&ss_algs[i].alg.crypto);
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break;
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case CRYPTO_ALG_TYPE_AHASH:
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crypto_unregister_ahash(&ss_algs[i].alg.hash);
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break;
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case CRYPTO_ALG_TYPE_RNG:
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crypto_unregister_rng(&ss_algs[i].alg.rng);
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break;
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}
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}
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writel(0, ss->base + SS_CTL);
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if (ss->reset)
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reset_control_assert(ss->reset);
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clk_disable_unprepare(ss->busclk);
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clk_disable_unprepare(ss->ssclk);
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return 0;
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}
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static const struct of_device_id a20ss_crypto_of_match_table[] = {
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{ .compatible = "allwinner,sun4i-a10-crypto" },
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{}
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};
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MODULE_DEVICE_TABLE(of, a20ss_crypto_of_match_table);
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static struct platform_driver sun4i_ss_driver = {
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.probe = sun4i_ss_probe,
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.remove = sun4i_ss_remove,
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.driver = {
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.name = "sun4i-ss",
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.of_match_table = a20ss_crypto_of_match_table,
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},
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};
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module_platform_driver(sun4i_ss_driver);
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MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie@gmail.com>");
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