416 lines
14 KiB
C
416 lines
14 KiB
C
/*
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This file is provided under a dual BSD/GPLv2 license. When using or
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redistributing this file, you may do so under either license.
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GPL LICENSE SUMMARY
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Copyright(c) 2015 Intel Corporation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of version 2 of the GNU General Public License as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Contact Information:
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qat-linux@intel.com
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BSD LICENSE
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Copyright(c) 2015 Intel Corporation.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/delay.h>
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#include "adf_accel_devices.h"
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#include "adf_common_drv.h"
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#include "adf_pf2vf_msg.h"
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#define ADF_DH895XCC_EP_OFFSET 0x3A000
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#define ADF_DH895XCC_ERRMSK3 (ADF_DH895XCC_EP_OFFSET + 0x1C)
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#define ADF_DH895XCC_ERRMSK3_VF2PF_L_MASK(vf_mask) ((vf_mask & 0xFFFF) << 9)
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#define ADF_DH895XCC_ERRMSK5 (ADF_DH895XCC_EP_OFFSET + 0xDC)
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#define ADF_DH895XCC_ERRMSK5_VF2PF_U_MASK(vf_mask) (vf_mask >> 16)
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void adf_enable_pf2vf_interrupts(struct adf_accel_dev *accel_dev)
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{
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struct adf_accel_pci *pci_info = &accel_dev->accel_pci_dev;
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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void __iomem *pmisc_bar_addr =
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pci_info->pci_bars[hw_data->get_misc_bar_id(hw_data)].virt_addr;
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ADF_CSR_WR(pmisc_bar_addr, hw_data->get_vintmsk_offset(0), 0x0);
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}
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void adf_disable_pf2vf_interrupts(struct adf_accel_dev *accel_dev)
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{
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struct adf_accel_pci *pci_info = &accel_dev->accel_pci_dev;
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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void __iomem *pmisc_bar_addr =
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pci_info->pci_bars[hw_data->get_misc_bar_id(hw_data)].virt_addr;
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ADF_CSR_WR(pmisc_bar_addr, hw_data->get_vintmsk_offset(0), 0x2);
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}
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void adf_enable_vf2pf_interrupts(struct adf_accel_dev *accel_dev,
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u32 vf_mask)
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{
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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struct adf_bar *pmisc =
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&GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];
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void __iomem *pmisc_addr = pmisc->virt_addr;
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u32 reg;
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/* Enable VF2PF Messaging Ints - VFs 1 through 16 per vf_mask[15:0] */
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if (vf_mask & 0xFFFF) {
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reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK3);
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reg &= ~ADF_DH895XCC_ERRMSK3_VF2PF_L_MASK(vf_mask);
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ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK3, reg);
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}
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/* Enable VF2PF Messaging Ints - VFs 17 through 32 per vf_mask[31:16] */
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if (vf_mask >> 16) {
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reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK5);
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reg &= ~ADF_DH895XCC_ERRMSK5_VF2PF_U_MASK(vf_mask);
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ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK5, reg);
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}
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}
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void adf_disable_vf2pf_interrupts(struct adf_accel_dev *accel_dev, u32 vf_mask)
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{
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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struct adf_bar *pmisc =
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&GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];
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void __iomem *pmisc_addr = pmisc->virt_addr;
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u32 reg;
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/* Disable VF2PF interrupts for VFs 1 through 16 per vf_mask[15:0] */
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if (vf_mask & 0xFFFF) {
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reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK3) |
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ADF_DH895XCC_ERRMSK3_VF2PF_L_MASK(vf_mask);
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ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK3, reg);
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}
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/* Disable VF2PF interrupts for VFs 17 through 32 per vf_mask[31:16] */
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if (vf_mask >> 16) {
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reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK5) |
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ADF_DH895XCC_ERRMSK5_VF2PF_U_MASK(vf_mask);
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ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK5, reg);
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}
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}
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static int __adf_iov_putmsg(struct adf_accel_dev *accel_dev, u32 msg, u8 vf_nr)
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{
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struct adf_accel_pci *pci_info = &accel_dev->accel_pci_dev;
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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void __iomem *pmisc_bar_addr =
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pci_info->pci_bars[hw_data->get_misc_bar_id(hw_data)].virt_addr;
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u32 val, pf2vf_offset, count = 0;
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u32 local_in_use_mask, local_in_use_pattern;
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u32 remote_in_use_mask, remote_in_use_pattern;
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struct mutex *lock; /* lock preventing concurrent acces of CSR */
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u32 int_bit;
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int ret = 0;
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if (accel_dev->is_vf) {
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pf2vf_offset = hw_data->get_pf2vf_offset(0);
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lock = &accel_dev->vf.vf2pf_lock;
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local_in_use_mask = ADF_VF2PF_IN_USE_BY_VF_MASK;
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local_in_use_pattern = ADF_VF2PF_IN_USE_BY_VF;
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remote_in_use_mask = ADF_PF2VF_IN_USE_BY_PF_MASK;
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remote_in_use_pattern = ADF_PF2VF_IN_USE_BY_PF;
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int_bit = ADF_VF2PF_INT;
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} else {
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pf2vf_offset = hw_data->get_pf2vf_offset(vf_nr);
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lock = &accel_dev->pf.vf_info[vf_nr].pf2vf_lock;
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local_in_use_mask = ADF_PF2VF_IN_USE_BY_PF_MASK;
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local_in_use_pattern = ADF_PF2VF_IN_USE_BY_PF;
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remote_in_use_mask = ADF_VF2PF_IN_USE_BY_VF_MASK;
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remote_in_use_pattern = ADF_VF2PF_IN_USE_BY_VF;
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int_bit = ADF_PF2VF_INT;
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}
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mutex_lock(lock);
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/* Check if PF2VF CSR is in use by remote function */
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val = ADF_CSR_RD(pmisc_bar_addr, pf2vf_offset);
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if ((val & remote_in_use_mask) == remote_in_use_pattern) {
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dev_dbg(&GET_DEV(accel_dev),
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"PF2VF CSR in use by remote function\n");
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ret = -EBUSY;
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goto out;
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}
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/* Attempt to get ownership of PF2VF CSR */
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msg &= ~local_in_use_mask;
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msg |= local_in_use_pattern;
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ADF_CSR_WR(pmisc_bar_addr, pf2vf_offset, msg);
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/* Wait in case remote func also attempting to get ownership */
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msleep(ADF_IOV_MSG_COLLISION_DETECT_DELAY);
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val = ADF_CSR_RD(pmisc_bar_addr, pf2vf_offset);
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if ((val & local_in_use_mask) != local_in_use_pattern) {
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dev_dbg(&GET_DEV(accel_dev),
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"PF2VF CSR in use by remote - collision detected\n");
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ret = -EBUSY;
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goto out;
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}
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/*
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* This function now owns the PV2VF CSR. The IN_USE_BY pattern must
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* remain in the PF2VF CSR for all writes including ACK from remote
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* until this local function relinquishes the CSR. Send the message
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* by interrupting the remote.
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*/
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ADF_CSR_WR(pmisc_bar_addr, pf2vf_offset, msg | int_bit);
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/* Wait for confirmation from remote func it received the message */
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do {
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msleep(ADF_IOV_MSG_ACK_DELAY);
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val = ADF_CSR_RD(pmisc_bar_addr, pf2vf_offset);
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} while ((val & int_bit) && (count++ < ADF_IOV_MSG_ACK_MAX_RETRY));
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if (val & int_bit) {
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dev_dbg(&GET_DEV(accel_dev), "ACK not received from remote\n");
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val &= ~int_bit;
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ret = -EIO;
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}
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/* Finished with PF2VF CSR; relinquish it and leave msg in CSR */
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ADF_CSR_WR(pmisc_bar_addr, pf2vf_offset, val & ~local_in_use_mask);
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out:
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mutex_unlock(lock);
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return ret;
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}
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/**
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* adf_iov_putmsg() - send PF2VF message
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* @accel_dev: Pointer to acceleration device.
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* @msg: Message to send
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* @vf_nr: VF number to which the message will be sent
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*
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* Function sends a messge from the PF to a VF
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*
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* Return: 0 on success, error code otherwise.
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*/
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int adf_iov_putmsg(struct adf_accel_dev *accel_dev, u32 msg, u8 vf_nr)
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{
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u32 count = 0;
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int ret;
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do {
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ret = __adf_iov_putmsg(accel_dev, msg, vf_nr);
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if (ret)
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msleep(ADF_IOV_MSG_RETRY_DELAY);
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} while (ret && (count++ < ADF_IOV_MSG_MAX_RETRIES));
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return ret;
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}
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EXPORT_SYMBOL_GPL(adf_iov_putmsg);
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void adf_vf2pf_req_hndl(struct adf_accel_vf_info *vf_info)
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{
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struct adf_accel_dev *accel_dev = vf_info->accel_dev;
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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int bar_id = hw_data->get_misc_bar_id(hw_data);
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struct adf_bar *pmisc = &GET_BARS(accel_dev)[bar_id];
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void __iomem *pmisc_addr = pmisc->virt_addr;
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u32 msg, resp = 0, vf_nr = vf_info->vf_nr;
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/* Read message from the VF */
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msg = ADF_CSR_RD(pmisc_addr, hw_data->get_pf2vf_offset(vf_nr));
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/* To ACK, clear the VF2PFINT bit */
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msg &= ~ADF_VF2PF_INT;
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ADF_CSR_WR(pmisc_addr, hw_data->get_pf2vf_offset(vf_nr), msg);
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if (!(msg & ADF_VF2PF_MSGORIGIN_SYSTEM))
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/* Ignore legacy non-system (non-kernel) VF2PF messages */
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goto err;
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switch ((msg & ADF_VF2PF_MSGTYPE_MASK) >> ADF_VF2PF_MSGTYPE_SHIFT) {
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case ADF_VF2PF_MSGTYPE_COMPAT_VER_REQ:
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{
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u8 vf_compat_ver = msg >> ADF_VF2PF_COMPAT_VER_REQ_SHIFT;
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resp = (ADF_PF2VF_MSGORIGIN_SYSTEM |
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(ADF_PF2VF_MSGTYPE_VERSION_RESP <<
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ADF_PF2VF_MSGTYPE_SHIFT) |
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(ADF_PFVF_COMPATIBILITY_VERSION <<
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ADF_PF2VF_VERSION_RESP_VERS_SHIFT));
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dev_dbg(&GET_DEV(accel_dev),
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"Compatibility Version Request from VF%d vers=%u\n",
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vf_nr + 1, vf_compat_ver);
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if (vf_compat_ver < hw_data->min_iov_compat_ver) {
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dev_err(&GET_DEV(accel_dev),
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"VF (vers %d) incompatible with PF (vers %d)\n",
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vf_compat_ver, ADF_PFVF_COMPATIBILITY_VERSION);
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resp |= ADF_PF2VF_VF_INCOMPATIBLE <<
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ADF_PF2VF_VERSION_RESP_RESULT_SHIFT;
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} else if (vf_compat_ver > ADF_PFVF_COMPATIBILITY_VERSION) {
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dev_err(&GET_DEV(accel_dev),
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"VF (vers %d) compat with PF (vers %d) unkn.\n",
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vf_compat_ver, ADF_PFVF_COMPATIBILITY_VERSION);
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resp |= ADF_PF2VF_VF_COMPAT_UNKNOWN <<
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ADF_PF2VF_VERSION_RESP_RESULT_SHIFT;
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} else {
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dev_dbg(&GET_DEV(accel_dev),
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"VF (vers %d) compatible with PF (vers %d)\n",
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vf_compat_ver, ADF_PFVF_COMPATIBILITY_VERSION);
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resp |= ADF_PF2VF_VF_COMPATIBLE <<
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ADF_PF2VF_VERSION_RESP_RESULT_SHIFT;
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}
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}
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break;
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case ADF_VF2PF_MSGTYPE_VERSION_REQ:
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dev_dbg(&GET_DEV(accel_dev),
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"Legacy VersionRequest received from VF%d 0x%x\n",
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vf_nr + 1, msg);
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resp = (ADF_PF2VF_MSGORIGIN_SYSTEM |
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(ADF_PF2VF_MSGTYPE_VERSION_RESP <<
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ADF_PF2VF_MSGTYPE_SHIFT) |
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(ADF_PFVF_COMPATIBILITY_VERSION <<
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ADF_PF2VF_VERSION_RESP_VERS_SHIFT));
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resp |= ADF_PF2VF_VF_COMPATIBLE <<
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ADF_PF2VF_VERSION_RESP_RESULT_SHIFT;
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/* Set legacy major and minor version num */
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resp |= 1 << ADF_PF2VF_MAJORVERSION_SHIFT |
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1 << ADF_PF2VF_MINORVERSION_SHIFT;
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break;
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case ADF_VF2PF_MSGTYPE_INIT:
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{
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dev_dbg(&GET_DEV(accel_dev),
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"Init message received from VF%d 0x%x\n",
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vf_nr + 1, msg);
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vf_info->init = true;
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}
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break;
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case ADF_VF2PF_MSGTYPE_SHUTDOWN:
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{
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dev_dbg(&GET_DEV(accel_dev),
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"Shutdown message received from VF%d 0x%x\n",
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vf_nr + 1, msg);
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vf_info->init = false;
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}
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break;
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default:
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goto err;
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}
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if (resp && adf_iov_putmsg(accel_dev, resp, vf_nr))
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dev_err(&GET_DEV(accel_dev), "Failed to send response to VF\n");
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/* re-enable interrupt on PF from this VF */
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adf_enable_vf2pf_interrupts(accel_dev, (1 << vf_nr));
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return;
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err:
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dev_dbg(&GET_DEV(accel_dev), "Unknown message from VF%d (0x%x);\n",
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vf_nr + 1, msg);
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}
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void adf_pf2vf_notify_restarting(struct adf_accel_dev *accel_dev)
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{
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struct adf_accel_vf_info *vf;
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u32 msg = (ADF_PF2VF_MSGORIGIN_SYSTEM |
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(ADF_PF2VF_MSGTYPE_RESTARTING << ADF_PF2VF_MSGTYPE_SHIFT));
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int i, num_vfs = pci_num_vf(accel_to_pci_dev(accel_dev));
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for (i = 0, vf = accel_dev->pf.vf_info; i < num_vfs; i++, vf++) {
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if (vf->init && adf_iov_putmsg(accel_dev, msg, i))
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dev_err(&GET_DEV(accel_dev),
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"Failed to send restarting msg to VF%d\n", i);
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}
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}
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static int adf_vf2pf_request_version(struct adf_accel_dev *accel_dev)
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{
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unsigned long timeout = msecs_to_jiffies(ADF_IOV_MSG_RESP_TIMEOUT);
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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u32 msg = 0;
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int ret;
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msg = ADF_VF2PF_MSGORIGIN_SYSTEM;
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msg |= ADF_VF2PF_MSGTYPE_COMPAT_VER_REQ << ADF_VF2PF_MSGTYPE_SHIFT;
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msg |= ADF_PFVF_COMPATIBILITY_VERSION << ADF_VF2PF_COMPAT_VER_REQ_SHIFT;
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BUILD_BUG_ON(ADF_PFVF_COMPATIBILITY_VERSION > 255);
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/* Send request from VF to PF */
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ret = adf_iov_putmsg(accel_dev, msg, 0);
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if (ret) {
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dev_err(&GET_DEV(accel_dev),
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"Failed to send Compatibility Version Request.\n");
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return ret;
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}
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/* Wait for response */
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if (!wait_for_completion_timeout(&accel_dev->vf.iov_msg_completion,
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timeout)) {
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dev_err(&GET_DEV(accel_dev),
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"IOV request/response message timeout expired\n");
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return -EIO;
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}
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/* Response from PF received, check compatibility */
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switch (accel_dev->vf.compatible) {
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case ADF_PF2VF_VF_COMPATIBLE:
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break;
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case ADF_PF2VF_VF_COMPAT_UNKNOWN:
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/* VF is newer than PF and decides whether it is compatible */
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if (accel_dev->vf.pf_version >= hw_data->min_iov_compat_ver)
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break;
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/* fall through */
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case ADF_PF2VF_VF_INCOMPATIBLE:
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dev_err(&GET_DEV(accel_dev),
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"PF (vers %d) and VF (vers %d) are not compatible\n",
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accel_dev->vf.pf_version,
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ADF_PFVF_COMPATIBILITY_VERSION);
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return -EINVAL;
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default:
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dev_err(&GET_DEV(accel_dev),
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"Invalid response from PF; assume not compatible\n");
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return -EINVAL;
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}
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return ret;
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}
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/**
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* adf_enable_vf2pf_comms() - Function enables communication from vf to pf
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*
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* @accel_dev: Pointer to acceleration device virtual function.
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*
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* Return: 0 on success, error code otherwise.
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*/
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int adf_enable_vf2pf_comms(struct adf_accel_dev *accel_dev)
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{
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adf_enable_pf2vf_interrupts(accel_dev);
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return adf_vf2pf_request_version(accel_dev);
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}
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EXPORT_SYMBOL_GPL(adf_enable_vf2pf_comms);
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