486 lines
14 KiB
C
486 lines
14 KiB
C
/*
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* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Common Clock Framework support for S3C2410 and following SoCs.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#include <dt-bindings/clock/s3c2410.h>
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#include "clk.h"
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#include "clk-pll.h"
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#define LOCKTIME 0x00
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#define MPLLCON 0x04
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#define UPLLCON 0x08
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#define CLKCON 0x0c
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#define CLKSLOW 0x10
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#define CLKDIVN 0x14
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#define CAMDIVN 0x18
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/* the soc types */
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enum supported_socs {
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S3C2410,
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S3C2440,
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S3C2442,
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};
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/* list of PLLs to be registered */
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enum s3c2410_plls {
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mpll, upll,
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};
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static void __iomem *reg_base;
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#ifdef CONFIG_PM_SLEEP
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static struct samsung_clk_reg_dump *s3c2410_save;
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/*
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* list of controller registers to be saved and restored during a
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* suspend/resume cycle.
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*/
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static unsigned long s3c2410_clk_regs[] __initdata = {
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LOCKTIME,
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MPLLCON,
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UPLLCON,
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CLKCON,
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CLKSLOW,
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CLKDIVN,
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CAMDIVN,
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};
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static int s3c2410_clk_suspend(void)
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{
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samsung_clk_save(reg_base, s3c2410_save,
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ARRAY_SIZE(s3c2410_clk_regs));
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return 0;
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}
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static void s3c2410_clk_resume(void)
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{
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samsung_clk_restore(reg_base, s3c2410_save,
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ARRAY_SIZE(s3c2410_clk_regs));
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}
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static struct syscore_ops s3c2410_clk_syscore_ops = {
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.suspend = s3c2410_clk_suspend,
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.resume = s3c2410_clk_resume,
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};
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static void __init s3c2410_clk_sleep_init(void)
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{
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s3c2410_save = samsung_clk_alloc_reg_dump(s3c2410_clk_regs,
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ARRAY_SIZE(s3c2410_clk_regs));
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if (!s3c2410_save) {
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pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
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__func__);
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return;
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}
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register_syscore_ops(&s3c2410_clk_syscore_ops);
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return;
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}
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#else
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static void __init s3c2410_clk_sleep_init(void) {}
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#endif
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PNAME(fclk_p) = { "mpll", "div_slow" };
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struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {
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MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
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};
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static struct clk_div_table divslow_d[] = {
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{ .val = 0, .div = 1 },
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{ .val = 1, .div = 2 },
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{ .val = 2, .div = 4 },
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{ .val = 3, .div = 6 },
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{ .val = 4, .div = 8 },
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{ .val = 5, .div = 10 },
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{ .val = 6, .div = 12 },
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{ .val = 7, .div = 14 },
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{ /* sentinel */ },
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};
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struct samsung_div_clock s3c2410_common_dividers[] __initdata = {
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DIV_T(0, "div_slow", "xti", CLKSLOW, 0, 3, divslow_d),
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DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
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};
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struct samsung_gate_clock s3c2410_common_gates[] __initdata = {
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GATE(PCLK_SPI, "spi", "pclk", CLKCON, 18, 0, 0),
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GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 17, 0, 0),
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GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 16, 0, 0),
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GATE(PCLK_ADC, "adc", "pclk", CLKCON, 15, 0, 0),
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GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 14, 0, 0),
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GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 13, CLK_IGNORE_UNUSED, 0),
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GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 12, 0, 0),
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GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0),
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GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0),
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GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 9, 0, 0),
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GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 8, 0, 0),
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GATE(HCLK_USBD, "usb-device", "hclk", CLKCON, 7, 0, 0),
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GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
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GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
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GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
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};
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/* should be added _after_ the soc-specific clocks are created */
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struct samsung_clock_alias s3c2410_common_aliases[] __initdata = {
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ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
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ALIAS(PCLK_ADC, NULL, "adc"),
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ALIAS(PCLK_RTC, NULL, "rtc"),
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ALIAS(PCLK_PWM, NULL, "timers"),
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ALIAS(HCLK_LCD, NULL, "lcd"),
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ALIAS(HCLK_USBD, NULL, "usb-device"),
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ALIAS(HCLK_USBH, NULL, "usb-host"),
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ALIAS(UCLK, NULL, "usb-bus-host"),
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ALIAS(UCLK, NULL, "usb-bus-gadget"),
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ALIAS(ARMCLK, NULL, "armclk"),
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ALIAS(UCLK, NULL, "uclk"),
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ALIAS(HCLK, NULL, "hclk"),
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ALIAS(MPLL, NULL, "mpll"),
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ALIAS(FCLK, NULL, "fclk"),
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ALIAS(PCLK, NULL, "watchdog"),
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ALIAS(PCLK_SDI, NULL, "sdi"),
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ALIAS(HCLK_NAND, NULL, "nand"),
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ALIAS(PCLK_I2S, NULL, "iis"),
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ALIAS(PCLK_I2C, NULL, "i2c"),
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};
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/* S3C2410 specific clocks */
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static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = {
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/* sorted in descending order */
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/* 2410A extras */
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PLL_35XX_RATE(270000000, 127, 1, 1),
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PLL_35XX_RATE(268000000, 126, 1, 1),
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PLL_35XX_RATE(266000000, 125, 1, 1),
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PLL_35XX_RATE(226000000, 105, 1, 1),
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PLL_35XX_RATE(210000000, 132, 2, 1),
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/* 2410 common */
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PLL_35XX_RATE(203000000, 161, 3, 1),
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PLL_35XX_RATE(192000000, 88, 1, 1),
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PLL_35XX_RATE(186000000, 85, 1, 1),
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PLL_35XX_RATE(180000000, 82, 1, 1),
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PLL_35XX_RATE(170000000, 77, 1, 1),
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PLL_35XX_RATE(158000000, 71, 1, 1),
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PLL_35XX_RATE(152000000, 68, 1, 1),
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PLL_35XX_RATE(147000000, 90, 2, 1),
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PLL_35XX_RATE(135000000, 82, 2, 1),
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PLL_35XX_RATE(124000000, 116, 1, 2),
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PLL_35XX_RATE(118000000, 150, 2, 2),
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PLL_35XX_RATE(113000000, 105, 1, 2),
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PLL_35XX_RATE(101000000, 127, 2, 2),
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PLL_35XX_RATE(90000000, 112, 2, 2),
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PLL_35XX_RATE(85000000, 105, 2, 2),
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PLL_35XX_RATE(79000000, 71, 1, 2),
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PLL_35XX_RATE(68000000, 82, 2, 2),
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PLL_35XX_RATE(56000000, 142, 2, 3),
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PLL_35XX_RATE(48000000, 120, 2, 3),
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PLL_35XX_RATE(51000000, 161, 3, 3),
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PLL_35XX_RATE(45000000, 82, 1, 3),
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PLL_35XX_RATE(34000000, 82, 2, 3),
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{ /* sentinel */ },
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};
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static struct samsung_pll_clock s3c2410_plls[] __initdata = {
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[mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
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LOCKTIME, MPLLCON, NULL),
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[upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
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LOCKTIME, UPLLCON, NULL),
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};
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struct samsung_div_clock s3c2410_dividers[] __initdata = {
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DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
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};
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struct samsung_fixed_factor_clock s3c2410_ffactor[] __initdata = {
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/*
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* armclk is directly supplied by the fclk, without
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* switching possibility like on the s3c244x below.
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*/
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FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
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/* uclk is fed from the unmodified upll */
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FFACTOR(UCLK, "uclk", "upll", 1, 1, 0),
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};
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struct samsung_clock_alias s3c2410_aliases[] __initdata = {
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ALIAS(PCLK_UART0, "s3c2410-uart.0", "uart"),
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ALIAS(PCLK_UART1, "s3c2410-uart.1", "uart"),
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ALIAS(PCLK_UART2, "s3c2410-uart.2", "uart"),
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ALIAS(PCLK_UART0, "s3c2410-uart.0", "clk_uart_baud0"),
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ALIAS(PCLK_UART1, "s3c2410-uart.1", "clk_uart_baud0"),
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ALIAS(PCLK_UART2, "s3c2410-uart.2", "clk_uart_baud0"),
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ALIAS(UCLK, NULL, "clk_uart_baud1"),
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};
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/* S3C244x specific clocks */
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static struct samsung_pll_rate_table pll_s3c244x_12mhz_tbl[] __initdata = {
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/* sorted in descending order */
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PLL_35XX_RATE(400000000, 0x5c, 1, 1),
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PLL_35XX_RATE(390000000, 0x7a, 2, 1),
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PLL_35XX_RATE(380000000, 0x57, 1, 1),
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PLL_35XX_RATE(370000000, 0xb1, 4, 1),
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PLL_35XX_RATE(360000000, 0x70, 2, 1),
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PLL_35XX_RATE(350000000, 0xa7, 4, 1),
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PLL_35XX_RATE(340000000, 0x4d, 1, 1),
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PLL_35XX_RATE(330000000, 0x66, 2, 1),
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PLL_35XX_RATE(320000000, 0x98, 4, 1),
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PLL_35XX_RATE(310000000, 0x93, 4, 1),
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PLL_35XX_RATE(300000000, 0x75, 3, 1),
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PLL_35XX_RATE(240000000, 0x70, 1, 2),
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PLL_35XX_RATE(230000000, 0x6b, 1, 2),
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PLL_35XX_RATE(220000000, 0x66, 1, 2),
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PLL_35XX_RATE(210000000, 0x84, 2, 2),
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PLL_35XX_RATE(200000000, 0x5c, 1, 2),
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PLL_35XX_RATE(190000000, 0x57, 1, 2),
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PLL_35XX_RATE(180000000, 0x70, 2, 2),
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PLL_35XX_RATE(170000000, 0x4d, 1, 2),
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PLL_35XX_RATE(160000000, 0x98, 4, 2),
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PLL_35XX_RATE(150000000, 0x75, 3, 2),
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PLL_35XX_RATE(120000000, 0x70, 1, 3),
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PLL_35XX_RATE(110000000, 0x66, 1, 3),
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PLL_35XX_RATE(100000000, 0x5c, 1, 3),
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PLL_35XX_RATE(90000000, 0x70, 2, 3),
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PLL_35XX_RATE(80000000, 0x98, 4, 3),
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PLL_35XX_RATE(75000000, 0x75, 3, 3),
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{ /* sentinel */ },
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};
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static struct samsung_pll_clock s3c244x_common_plls[] __initdata = {
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[mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
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LOCKTIME, MPLLCON, NULL),
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[upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
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LOCKTIME, UPLLCON, NULL),
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};
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PNAME(hclk_p) = { "fclk", "div_hclk_2", "div_hclk_4", "div_hclk_3" };
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PNAME(armclk_p) = { "fclk", "hclk" };
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struct samsung_mux_clock s3c244x_common_muxes[] __initdata = {
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MUX(HCLK, "hclk", hclk_p, CLKDIVN, 1, 2),
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MUX(ARMCLK, "armclk", armclk_p, CAMDIVN, 12, 1),
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};
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struct samsung_fixed_factor_clock s3c244x_common_ffactor[] __initdata = {
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FFACTOR(0, "div_hclk_2", "fclk", 1, 2, 0),
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FFACTOR(0, "ff_cam", "div_cam", 2, 1, CLK_SET_RATE_PARENT),
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};
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static struct clk_div_table div_hclk_4_d[] = {
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{ .val = 0, .div = 4 },
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{ .val = 1, .div = 8 },
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{ /* sentinel */ },
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};
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static struct clk_div_table div_hclk_3_d[] = {
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{ .val = 0, .div = 3 },
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{ .val = 1, .div = 6 },
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{ /* sentinel */ },
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};
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struct samsung_div_clock s3c244x_common_dividers[] __initdata = {
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DIV(UCLK, "uclk", "upll", CLKDIVN, 3, 1),
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DIV(0, "div_hclk", "fclk", CLKDIVN, 1, 1),
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DIV_T(0, "div_hclk_4", "fclk", CAMDIVN, 9, 1, div_hclk_4_d),
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DIV_T(0, "div_hclk_3", "fclk", CAMDIVN, 8, 1, div_hclk_3_d),
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DIV(0, "div_cam", "upll", CAMDIVN, 0, 3),
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};
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struct samsung_gate_clock s3c244x_common_gates[] __initdata = {
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GATE(HCLK_CAM, "cam", "hclk", CLKCON, 19, 0, 0),
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};
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struct samsung_clock_alias s3c244x_common_aliases[] __initdata = {
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ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
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ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
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ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
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ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
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ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
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ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
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ALIAS(HCLK_CAM, NULL, "camif"),
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ALIAS(CAMIF, NULL, "camif-upll"),
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};
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/* S3C2440 specific clocks */
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PNAME(s3c2440_camif_p) = { "upll", "ff_cam" };
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struct samsung_mux_clock s3c2440_muxes[] __initdata = {
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MUX(CAMIF, "camif", s3c2440_camif_p, CAMDIVN, 4, 1),
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};
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struct samsung_gate_clock s3c2440_gates[] __initdata = {
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GATE(PCLK_AC97, "ac97", "pclk", CLKCON, 20, 0, 0),
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};
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/* S3C2442 specific clocks */
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struct samsung_fixed_factor_clock s3c2442_ffactor[] __initdata = {
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FFACTOR(0, "upll_3", "upll", 1, 3, 0),
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};
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PNAME(s3c2442_camif_p) = { "upll", "ff_cam", "upll", "upll_3" };
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struct samsung_mux_clock s3c2442_muxes[] __initdata = {
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MUX(CAMIF, "camif", s3c2442_camif_p, CAMDIVN, 4, 2),
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};
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/*
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* fixed rate clocks generated outside the soc
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* Only necessary until the devicetree-move is complete
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*/
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#define XTI 1
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struct samsung_fixed_rate_clock s3c2410_common_frate_clks[] __initdata = {
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FRATE(XTI, "xti", NULL, 0, 0),
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};
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static void __init s3c2410_common_clk_register_fixed_ext(
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struct samsung_clk_provider *ctx,
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unsigned long xti_f)
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{
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struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
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s3c2410_common_frate_clks[0].fixed_rate = xti_f;
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samsung_clk_register_fixed_rate(ctx, s3c2410_common_frate_clks,
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ARRAY_SIZE(s3c2410_common_frate_clks));
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samsung_clk_register_alias(ctx, &xti_alias, 1);
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}
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void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
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int current_soc,
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void __iomem *base)
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{
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struct samsung_clk_provider *ctx;
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reg_base = base;
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if (np) {
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reg_base = of_iomap(np, 0);
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if (!reg_base)
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panic("%s: failed to map registers\n", __func__);
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}
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ctx = samsung_clk_init(np, reg_base, NR_CLKS);
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/* Register external clocks only in non-dt cases */
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if (!np)
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s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
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if (current_soc == S3C2410) {
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if (_get_rate("xti") == 12 * MHZ) {
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s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
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s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
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}
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/* Register PLLs. */
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samsung_clk_register_pll(ctx, s3c2410_plls,
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ARRAY_SIZE(s3c2410_plls), reg_base);
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} else { /* S3C2440, S3C2442 */
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if (_get_rate("xti") == 12 * MHZ) {
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/*
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* plls follow different calculation schemes, with the
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* upll following the same scheme as the s3c2410 plls
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*/
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s3c244x_common_plls[mpll].rate_table =
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pll_s3c244x_12mhz_tbl;
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s3c244x_common_plls[upll].rate_table =
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pll_s3c2410_12mhz_tbl;
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}
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/* Register PLLs. */
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samsung_clk_register_pll(ctx, s3c244x_common_plls,
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ARRAY_SIZE(s3c244x_common_plls), reg_base);
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}
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|
|
|
/* Register common internal clocks. */
|
|
samsung_clk_register_mux(ctx, s3c2410_common_muxes,
|
|
ARRAY_SIZE(s3c2410_common_muxes));
|
|
samsung_clk_register_div(ctx, s3c2410_common_dividers,
|
|
ARRAY_SIZE(s3c2410_common_dividers));
|
|
samsung_clk_register_gate(ctx, s3c2410_common_gates,
|
|
ARRAY_SIZE(s3c2410_common_gates));
|
|
|
|
if (current_soc == S3C2440 || current_soc == S3C2442) {
|
|
samsung_clk_register_div(ctx, s3c244x_common_dividers,
|
|
ARRAY_SIZE(s3c244x_common_dividers));
|
|
samsung_clk_register_gate(ctx, s3c244x_common_gates,
|
|
ARRAY_SIZE(s3c244x_common_gates));
|
|
samsung_clk_register_mux(ctx, s3c244x_common_muxes,
|
|
ARRAY_SIZE(s3c244x_common_muxes));
|
|
samsung_clk_register_fixed_factor(ctx, s3c244x_common_ffactor,
|
|
ARRAY_SIZE(s3c244x_common_ffactor));
|
|
}
|
|
|
|
/* Register SoC-specific clocks. */
|
|
switch (current_soc) {
|
|
case S3C2410:
|
|
samsung_clk_register_div(ctx, s3c2410_dividers,
|
|
ARRAY_SIZE(s3c2410_dividers));
|
|
samsung_clk_register_fixed_factor(ctx, s3c2410_ffactor,
|
|
ARRAY_SIZE(s3c2410_ffactor));
|
|
samsung_clk_register_alias(ctx, s3c2410_aliases,
|
|
ARRAY_SIZE(s3c2410_aliases));
|
|
break;
|
|
case S3C2440:
|
|
samsung_clk_register_mux(ctx, s3c2440_muxes,
|
|
ARRAY_SIZE(s3c2440_muxes));
|
|
samsung_clk_register_gate(ctx, s3c2440_gates,
|
|
ARRAY_SIZE(s3c2440_gates));
|
|
break;
|
|
case S3C2442:
|
|
samsung_clk_register_mux(ctx, s3c2442_muxes,
|
|
ARRAY_SIZE(s3c2442_muxes));
|
|
samsung_clk_register_fixed_factor(ctx, s3c2442_ffactor,
|
|
ARRAY_SIZE(s3c2442_ffactor));
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Register common aliases at the end, as some of the aliased clocks
|
|
* are SoC specific.
|
|
*/
|
|
samsung_clk_register_alias(ctx, s3c2410_common_aliases,
|
|
ARRAY_SIZE(s3c2410_common_aliases));
|
|
|
|
if (current_soc == S3C2440 || current_soc == S3C2442) {
|
|
samsung_clk_register_alias(ctx, s3c244x_common_aliases,
|
|
ARRAY_SIZE(s3c244x_common_aliases));
|
|
}
|
|
|
|
s3c2410_clk_sleep_init();
|
|
|
|
samsung_clk_of_add_provider(np, ctx);
|
|
}
|
|
|
|
static void __init s3c2410_clk_init(struct device_node *np)
|
|
{
|
|
s3c2410_common_clk_init(np, 0, S3C2410, 0);
|
|
}
|
|
CLK_OF_DECLARE(s3c2410_clk, "samsung,s3c2410-clock", s3c2410_clk_init);
|
|
|
|
static void __init s3c2440_clk_init(struct device_node *np)
|
|
{
|
|
s3c2410_common_clk_init(np, 0, S3C2440, 0);
|
|
}
|
|
CLK_OF_DECLARE(s3c2440_clk, "samsung,s3c2440-clock", s3c2440_clk_init);
|
|
|
|
static void __init s3c2442_clk_init(struct device_node *np)
|
|
{
|
|
s3c2410_common_clk_init(np, 0, S3C2442, 0);
|
|
}
|
|
CLK_OF_DECLARE(s3c2442_clk, "samsung,s3c2442-clock", s3c2442_clk_init);
|