145 lines
4.0 KiB
C
145 lines
4.0 KiB
C
/*
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* Copyright (c) 2017 AmLogic, Inc.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* i2s master clock divider: The algorithm of the generic clk-divider used with
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* a very precise clock parent such as the mpll tends to select a low divider
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* factor. This gives poor results with this particular divider, especially with
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* high frequencies (> 100 MHz)
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*
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* This driver try to select the maximum possible divider with the rate the
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* upstream clock can provide.
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*/
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#include <linux/clk-provider.h>
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#include "clkc.h"
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#define to_meson_clk_audio_divider(_hw) container_of(_hw, \
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struct meson_clk_audio_divider, hw)
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static int _div_round(unsigned long parent_rate, unsigned long rate,
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unsigned long flags)
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{
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if (flags & CLK_DIVIDER_ROUND_CLOSEST)
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return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, rate);
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return DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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}
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static int _get_val(unsigned long parent_rate, unsigned long rate)
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{
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return DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
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}
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static int _valid_divider(struct clk_hw *hw, int divider)
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{
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struct meson_clk_audio_divider *adiv =
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to_meson_clk_audio_divider(hw);
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int max_divider;
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u8 width;
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width = adiv->div.width;
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max_divider = 1 << width;
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return clamp(divider, 1, max_divider);
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}
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static unsigned long audio_divider_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct meson_clk_audio_divider *adiv =
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to_meson_clk_audio_divider(hw);
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struct parm *p;
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unsigned long reg, divider;
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p = &adiv->div;
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reg = readl(adiv->base + p->reg_off);
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divider = PARM_GET(p->width, p->shift, reg) + 1;
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return DIV_ROUND_UP_ULL((u64)parent_rate, divider);
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}
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static long audio_divider_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate)
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{
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struct meson_clk_audio_divider *adiv =
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to_meson_clk_audio_divider(hw);
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unsigned long max_prate;
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int divider;
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if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
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divider = _div_round(*parent_rate, rate, adiv->flags);
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divider = _valid_divider(hw, divider);
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return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
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}
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/* Get the maximum parent rate */
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max_prate = clk_hw_round_rate(clk_hw_get_parent(hw), ULONG_MAX);
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/* Get the corresponding rounded down divider */
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divider = max_prate / rate;
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divider = _valid_divider(hw, divider);
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/* Get actual rate of the parent */
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*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
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divider * rate);
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return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
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}
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static int audio_divider_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct meson_clk_audio_divider *adiv =
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to_meson_clk_audio_divider(hw);
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struct parm *p;
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unsigned long reg, flags = 0;
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int val;
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val = _get_val(parent_rate, rate);
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if (adiv->lock)
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spin_lock_irqsave(adiv->lock, flags);
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else
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__acquire(adiv->lock);
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p = &adiv->div;
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reg = readl(adiv->base + p->reg_off);
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reg = PARM_SET(p->width, p->shift, reg, val);
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writel(reg, adiv->base + p->reg_off);
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if (adiv->lock)
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spin_unlock_irqrestore(adiv->lock, flags);
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else
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__release(adiv->lock);
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return 0;
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}
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const struct clk_ops meson_clk_audio_divider_ro_ops = {
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.recalc_rate = audio_divider_recalc_rate,
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.round_rate = audio_divider_round_rate,
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};
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const struct clk_ops meson_clk_audio_divider_ops = {
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.recalc_rate = audio_divider_recalc_rate,
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.round_rate = audio_divider_round_rate,
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.set_rate = audio_divider_set_rate,
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};
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