753 lines
19 KiB
C
753 lines
19 KiB
C
#include <linux/perf_event.h>
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#include <linux/export.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <asm/apicdef.h>
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#include "../perf_event.h"
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static __initconst const u64 amd_hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(L1D) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
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[ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
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[ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
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},
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},
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[ C(L1I ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */
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[ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(LL ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
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[ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */
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[ C(RESULT_MISS) ] = 0,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(DTLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
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[ C(RESULT_MISS) ] = 0x0746, /* L1_DTLB_AND_L2_DLTB_MISS.ALL */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(ITLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
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[ C(RESULT_MISS) ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(BPU ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */
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[ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(NODE) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0xb8e9, /* CPU Request to Memory, l+r */
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[ C(RESULT_MISS) ] = 0x98e9, /* CPU Request to Memory, r */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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};
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/*
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* AMD Performance Monitor K7 and later.
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*/
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static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] =
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{
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[PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
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[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
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[PERF_COUNT_HW_CACHE_REFERENCES] = 0x077d,
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[PERF_COUNT_HW_CACHE_MISSES] = 0x077e,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
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[PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00d0, /* "Decoder empty" event */
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[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x00d1, /* "Dispatch stalls" event */
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};
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static u64 amd_pmu_event_map(int hw_event)
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{
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return amd_perfmon_event_map[hw_event];
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}
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/*
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* Previously calculated offsets
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*/
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static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;
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static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
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/*
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* Legacy CPUs:
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* 4 counters starting at 0xc0010000 each offset by 1
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*
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* CPUs with core performance counter extensions:
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* 6 counters starting at 0xc0010200 each offset by 2
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*/
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static inline int amd_pmu_addr_offset(int index, bool eventsel)
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{
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int offset;
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if (!index)
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return index;
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if (eventsel)
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offset = event_offsets[index];
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else
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offset = count_offsets[index];
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if (offset)
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return offset;
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if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
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offset = index;
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else
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offset = index << 1;
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if (eventsel)
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event_offsets[index] = offset;
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else
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count_offsets[index] = offset;
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return offset;
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}
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static int amd_core_hw_config(struct perf_event *event)
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{
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if (event->attr.exclude_host && event->attr.exclude_guest)
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/*
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* When HO == GO == 1 the hardware treats that as GO == HO == 0
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* and will count in both modes. We don't want to count in that
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* case so we emulate no-counting by setting US = OS = 0.
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*/
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event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
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ARCH_PERFMON_EVENTSEL_OS);
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else if (event->attr.exclude_host)
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event->hw.config |= AMD64_EVENTSEL_GUESTONLY;
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else if (event->attr.exclude_guest)
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event->hw.config |= AMD64_EVENTSEL_HOSTONLY;
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return 0;
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}
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/*
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* AMD64 events are detected based on their event codes.
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*/
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static inline unsigned int amd_get_event_code(struct hw_perf_event *hwc)
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{
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return ((hwc->config >> 24) & 0x0f00) | (hwc->config & 0x00ff);
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}
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static inline int amd_is_nb_event(struct hw_perf_event *hwc)
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{
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return (hwc->config & 0xe0) == 0xe0;
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}
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static inline int amd_has_nb(struct cpu_hw_events *cpuc)
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{
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struct amd_nb *nb = cpuc->amd_nb;
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return nb && nb->nb_id != -1;
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}
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static int amd_pmu_hw_config(struct perf_event *event)
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{
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int ret;
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/* pass precise event sampling to ibs: */
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if (event->attr.precise_ip && get_ibs_caps())
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return -ENOENT;
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if (has_branch_stack(event))
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return -EOPNOTSUPP;
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ret = x86_pmu_hw_config(event);
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if (ret)
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return ret;
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if (event->attr.type == PERF_TYPE_RAW)
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event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
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return amd_core_hw_config(event);
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}
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static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
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struct perf_event *event)
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{
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struct amd_nb *nb = cpuc->amd_nb;
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int i;
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/*
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* need to scan whole list because event may not have
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* been assigned during scheduling
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*
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* no race condition possible because event can only
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* be removed on one CPU at a time AND PMU is disabled
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* when we come here
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*/
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for (i = 0; i < x86_pmu.num_counters; i++) {
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if (cmpxchg(nb->owners + i, event, NULL) == event)
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break;
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}
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}
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/*
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* AMD64 NorthBridge events need special treatment because
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* counter access needs to be synchronized across all cores
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* of a package. Refer to BKDG section 3.12
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*
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* NB events are events measuring L3 cache, Hypertransport
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* traffic. They are identified by an event code >= 0xe00.
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* They measure events on the NorthBride which is shared
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* by all cores on a package. NB events are counted on a
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* shared set of counters. When a NB event is programmed
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* in a counter, the data actually comes from a shared
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* counter. Thus, access to those counters needs to be
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* synchronized.
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*
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* We implement the synchronization such that no two cores
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* can be measuring NB events using the same counters. Thus,
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* we maintain a per-NB allocation table. The available slot
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* is propagated using the event_constraint structure.
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*
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* We provide only one choice for each NB event based on
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* the fact that only NB events have restrictions. Consequently,
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* if a counter is available, there is a guarantee the NB event
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* will be assigned to it. If no slot is available, an empty
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* constraint is returned and scheduling will eventually fail
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* for this event.
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*
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* Note that all cores attached the same NB compete for the same
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* counters to host NB events, this is why we use atomic ops. Some
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* multi-chip CPUs may have more than one NB.
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*
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* Given that resources are allocated (cmpxchg), they must be
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* eventually freed for others to use. This is accomplished by
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* calling __amd_put_nb_event_constraints()
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*
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* Non NB events are not impacted by this restriction.
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*/
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static struct event_constraint *
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__amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
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struct event_constraint *c)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct amd_nb *nb = cpuc->amd_nb;
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struct perf_event *old;
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int idx, new = -1;
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if (!c)
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c = &unconstrained;
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if (cpuc->is_fake)
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return c;
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/*
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* detect if already present, if so reuse
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*
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* cannot merge with actual allocation
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* because of possible holes
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*
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* event can already be present yet not assigned (in hwc->idx)
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* because of successive calls to x86_schedule_events() from
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* hw_perf_group_sched_in() without hw_perf_enable()
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*/
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for_each_set_bit(idx, c->idxmsk, x86_pmu.num_counters) {
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if (new == -1 || hwc->idx == idx)
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/* assign free slot, prefer hwc->idx */
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old = cmpxchg(nb->owners + idx, NULL, event);
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else if (nb->owners[idx] == event)
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/* event already present */
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old = event;
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else
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continue;
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if (old && old != event)
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continue;
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/* reassign to this slot */
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if (new != -1)
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cmpxchg(nb->owners + new, event, NULL);
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new = idx;
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/* already present, reuse */
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if (old == event)
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break;
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}
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if (new == -1)
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return &emptyconstraint;
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return &nb->event_constraints[new];
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}
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static struct amd_nb *amd_alloc_nb(int cpu)
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{
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struct amd_nb *nb;
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int i;
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nb = kzalloc_node(sizeof(struct amd_nb), GFP_KERNEL, cpu_to_node(cpu));
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if (!nb)
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return NULL;
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nb->nb_id = -1;
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/*
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* initialize all possible NB constraints
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*/
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for (i = 0; i < x86_pmu.num_counters; i++) {
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__set_bit(i, nb->event_constraints[i].idxmsk);
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nb->event_constraints[i].weight = 1;
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}
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return nb;
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}
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static int amd_pmu_cpu_prepare(int cpu)
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{
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struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
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WARN_ON_ONCE(cpuc->amd_nb);
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if (!x86_pmu.amd_nb_constraints)
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return 0;
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cpuc->amd_nb = amd_alloc_nb(cpu);
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if (!cpuc->amd_nb)
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return -ENOMEM;
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return 0;
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}
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static void amd_pmu_cpu_starting(int cpu)
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{
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struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
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void **onln = &cpuc->kfree_on_online[X86_PERF_KFREE_SHARED];
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struct amd_nb *nb;
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int i, nb_id;
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cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
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if (!x86_pmu.amd_nb_constraints)
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return;
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nb_id = amd_get_nb_id(cpu);
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WARN_ON_ONCE(nb_id == BAD_APICID);
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for_each_online_cpu(i) {
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nb = per_cpu(cpu_hw_events, i).amd_nb;
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if (WARN_ON_ONCE(!nb))
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continue;
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if (nb->nb_id == nb_id) {
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*onln = cpuc->amd_nb;
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cpuc->amd_nb = nb;
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break;
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}
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}
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cpuc->amd_nb->nb_id = nb_id;
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cpuc->amd_nb->refcnt++;
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}
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static void amd_pmu_cpu_dead(int cpu)
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{
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struct cpu_hw_events *cpuhw;
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if (!x86_pmu.amd_nb_constraints)
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return;
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cpuhw = &per_cpu(cpu_hw_events, cpu);
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if (cpuhw->amd_nb) {
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struct amd_nb *nb = cpuhw->amd_nb;
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if (nb->nb_id == -1 || --nb->refcnt == 0)
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kfree(nb);
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cpuhw->amd_nb = NULL;
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}
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}
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static struct event_constraint *
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amd_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
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struct perf_event *event)
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{
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/*
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* if not NB event or no NB, then no constraints
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*/
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if (!(amd_has_nb(cpuc) && amd_is_nb_event(&event->hw)))
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return &unconstrained;
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return __amd_get_nb_event_constraints(cpuc, event, NULL);
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}
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static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
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struct perf_event *event)
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{
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if (amd_has_nb(cpuc) && amd_is_nb_event(&event->hw))
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__amd_put_nb_event_constraints(cpuc, event);
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}
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PMU_FORMAT_ATTR(event, "config:0-7,32-35");
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PMU_FORMAT_ATTR(umask, "config:8-15" );
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PMU_FORMAT_ATTR(edge, "config:18" );
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PMU_FORMAT_ATTR(inv, "config:23" );
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PMU_FORMAT_ATTR(cmask, "config:24-31" );
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static struct attribute *amd_format_attr[] = {
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&format_attr_event.attr,
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&format_attr_umask.attr,
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&format_attr_edge.attr,
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&format_attr_inv.attr,
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&format_attr_cmask.attr,
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NULL,
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};
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/* AMD Family 15h */
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#define AMD_EVENT_TYPE_MASK 0x000000F0ULL
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#define AMD_EVENT_FP 0x00000000ULL ... 0x00000010ULL
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#define AMD_EVENT_LS 0x00000020ULL ... 0x00000030ULL
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#define AMD_EVENT_DC 0x00000040ULL ... 0x00000050ULL
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#define AMD_EVENT_CU 0x00000060ULL ... 0x00000070ULL
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#define AMD_EVENT_IC_DE 0x00000080ULL ... 0x00000090ULL
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#define AMD_EVENT_EX_LS 0x000000C0ULL
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#define AMD_EVENT_DE 0x000000D0ULL
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#define AMD_EVENT_NB 0x000000E0ULL ... 0x000000F0ULL
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/*
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* AMD family 15h event code/PMC mappings:
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*
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* type = event_code & 0x0F0:
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*
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* 0x000 FP PERF_CTL[5:3]
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* 0x010 FP PERF_CTL[5:3]
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* 0x020 LS PERF_CTL[5:0]
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* 0x030 LS PERF_CTL[5:0]
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* 0x040 DC PERF_CTL[5:0]
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* 0x050 DC PERF_CTL[5:0]
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* 0x060 CU PERF_CTL[2:0]
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* 0x070 CU PERF_CTL[2:0]
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* 0x080 IC/DE PERF_CTL[2:0]
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* 0x090 IC/DE PERF_CTL[2:0]
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* 0x0A0 ---
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* 0x0B0 ---
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* 0x0C0 EX/LS PERF_CTL[5:0]
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* 0x0D0 DE PERF_CTL[2:0]
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* 0x0E0 NB NB_PERF_CTL[3:0]
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* 0x0F0 NB NB_PERF_CTL[3:0]
|
|
*
|
|
* Exceptions:
|
|
*
|
|
* 0x000 FP PERF_CTL[3], PERF_CTL[5:3] (*)
|
|
* 0x003 FP PERF_CTL[3]
|
|
* 0x004 FP PERF_CTL[3], PERF_CTL[5:3] (*)
|
|
* 0x00B FP PERF_CTL[3]
|
|
* 0x00D FP PERF_CTL[3]
|
|
* 0x023 DE PERF_CTL[2:0]
|
|
* 0x02D LS PERF_CTL[3]
|
|
* 0x02E LS PERF_CTL[3,0]
|
|
* 0x031 LS PERF_CTL[2:0] (**)
|
|
* 0x043 CU PERF_CTL[2:0]
|
|
* 0x045 CU PERF_CTL[2:0]
|
|
* 0x046 CU PERF_CTL[2:0]
|
|
* 0x054 CU PERF_CTL[2:0]
|
|
* 0x055 CU PERF_CTL[2:0]
|
|
* 0x08F IC PERF_CTL[0]
|
|
* 0x187 DE PERF_CTL[0]
|
|
* 0x188 DE PERF_CTL[0]
|
|
* 0x0DB EX PERF_CTL[5:0]
|
|
* 0x0DC LS PERF_CTL[5:0]
|
|
* 0x0DD LS PERF_CTL[5:0]
|
|
* 0x0DE LS PERF_CTL[5:0]
|
|
* 0x0DF LS PERF_CTL[5:0]
|
|
* 0x1C0 EX PERF_CTL[5:3]
|
|
* 0x1D6 EX PERF_CTL[5:0]
|
|
* 0x1D8 EX PERF_CTL[5:0]
|
|
*
|
|
* (*) depending on the umask all FPU counters may be used
|
|
* (**) only one unitmask enabled at a time
|
|
*/
|
|
|
|
static struct event_constraint amd_f15_PMC0 = EVENT_CONSTRAINT(0, 0x01, 0);
|
|
static struct event_constraint amd_f15_PMC20 = EVENT_CONSTRAINT(0, 0x07, 0);
|
|
static struct event_constraint amd_f15_PMC3 = EVENT_CONSTRAINT(0, 0x08, 0);
|
|
static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
|
|
static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0);
|
|
static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
|
|
|
|
static struct event_constraint *
|
|
amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, int idx,
|
|
struct perf_event *event)
|
|
{
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
unsigned int event_code = amd_get_event_code(hwc);
|
|
|
|
switch (event_code & AMD_EVENT_TYPE_MASK) {
|
|
case AMD_EVENT_FP:
|
|
switch (event_code) {
|
|
case 0x000:
|
|
if (!(hwc->config & 0x0000F000ULL))
|
|
break;
|
|
if (!(hwc->config & 0x00000F00ULL))
|
|
break;
|
|
return &amd_f15_PMC3;
|
|
case 0x004:
|
|
if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1)
|
|
break;
|
|
return &amd_f15_PMC3;
|
|
case 0x003:
|
|
case 0x00B:
|
|
case 0x00D:
|
|
return &amd_f15_PMC3;
|
|
}
|
|
return &amd_f15_PMC53;
|
|
case AMD_EVENT_LS:
|
|
case AMD_EVENT_DC:
|
|
case AMD_EVENT_EX_LS:
|
|
switch (event_code) {
|
|
case 0x023:
|
|
case 0x043:
|
|
case 0x045:
|
|
case 0x046:
|
|
case 0x054:
|
|
case 0x055:
|
|
return &amd_f15_PMC20;
|
|
case 0x02D:
|
|
return &amd_f15_PMC3;
|
|
case 0x02E:
|
|
return &amd_f15_PMC30;
|
|
case 0x031:
|
|
if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1)
|
|
return &amd_f15_PMC20;
|
|
return &emptyconstraint;
|
|
case 0x1C0:
|
|
return &amd_f15_PMC53;
|
|
default:
|
|
return &amd_f15_PMC50;
|
|
}
|
|
case AMD_EVENT_CU:
|
|
case AMD_EVENT_IC_DE:
|
|
case AMD_EVENT_DE:
|
|
switch (event_code) {
|
|
case 0x08F:
|
|
case 0x187:
|
|
case 0x188:
|
|
return &amd_f15_PMC0;
|
|
case 0x0DB ... 0x0DF:
|
|
case 0x1D6:
|
|
case 0x1D8:
|
|
return &amd_f15_PMC50;
|
|
default:
|
|
return &amd_f15_PMC20;
|
|
}
|
|
case AMD_EVENT_NB:
|
|
/* moved to uncore.c */
|
|
return &emptyconstraint;
|
|
default:
|
|
return &emptyconstraint;
|
|
}
|
|
}
|
|
|
|
static ssize_t amd_event_sysfs_show(char *page, u64 config)
|
|
{
|
|
u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT) |
|
|
(config & AMD64_EVENTSEL_EVENT) >> 24;
|
|
|
|
return x86_event_sysfs_show(page, config, event);
|
|
}
|
|
|
|
static __initconst const struct x86_pmu amd_pmu = {
|
|
.name = "AMD",
|
|
.handle_irq = x86_pmu_handle_irq,
|
|
.disable_all = x86_pmu_disable_all,
|
|
.enable_all = x86_pmu_enable_all,
|
|
.enable = x86_pmu_enable_event,
|
|
.disable = x86_pmu_disable_event,
|
|
.hw_config = amd_pmu_hw_config,
|
|
.schedule_events = x86_schedule_events,
|
|
.eventsel = MSR_K7_EVNTSEL0,
|
|
.perfctr = MSR_K7_PERFCTR0,
|
|
.addr_offset = amd_pmu_addr_offset,
|
|
.event_map = amd_pmu_event_map,
|
|
.max_events = ARRAY_SIZE(amd_perfmon_event_map),
|
|
.num_counters = AMD64_NUM_COUNTERS,
|
|
.cntval_bits = 48,
|
|
.cntval_mask = (1ULL << 48) - 1,
|
|
.apic = 1,
|
|
/* use highest bit to detect overflow */
|
|
.max_period = (1ULL << 47) - 1,
|
|
.get_event_constraints = amd_get_event_constraints,
|
|
.put_event_constraints = amd_put_event_constraints,
|
|
|
|
.format_attrs = amd_format_attr,
|
|
.events_sysfs_show = amd_event_sysfs_show,
|
|
|
|
.cpu_prepare = amd_pmu_cpu_prepare,
|
|
.cpu_starting = amd_pmu_cpu_starting,
|
|
.cpu_dead = amd_pmu_cpu_dead,
|
|
|
|
.amd_nb_constraints = 1,
|
|
};
|
|
|
|
static int __init amd_core_pmu_init(void)
|
|
{
|
|
if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
|
|
return 0;
|
|
|
|
switch (boot_cpu_data.x86) {
|
|
case 0x15:
|
|
pr_cont("Fam15h ");
|
|
x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
|
|
break;
|
|
case 0x17:
|
|
pr_cont("Fam17h ");
|
|
/*
|
|
* In family 17h, there are no event constraints in the PMC hardware.
|
|
* We fallback to using default amd_get_event_constraints.
|
|
*/
|
|
break;
|
|
default:
|
|
pr_err("core perfctr but no constraints; unknown hardware!\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/*
|
|
* If core performance counter extensions exists, we must use
|
|
* MSR_F15H_PERF_CTL/MSR_F15H_PERF_CTR msrs. See also
|
|
* amd_pmu_addr_offset().
|
|
*/
|
|
x86_pmu.eventsel = MSR_F15H_PERF_CTL;
|
|
x86_pmu.perfctr = MSR_F15H_PERF_CTR;
|
|
x86_pmu.num_counters = AMD64_NUM_COUNTERS_CORE;
|
|
/*
|
|
* AMD Core perfctr has separate MSRs for the NB events, see
|
|
* the amd/uncore.c driver.
|
|
*/
|
|
x86_pmu.amd_nb_constraints = 0;
|
|
|
|
pr_cont("core perfctr, ");
|
|
return 0;
|
|
}
|
|
|
|
__init int amd_pmu_init(void)
|
|
{
|
|
int ret;
|
|
|
|
/* Performance-monitoring supported from K7 and later: */
|
|
if (boot_cpu_data.x86 < 6)
|
|
return -ENODEV;
|
|
|
|
x86_pmu = amd_pmu;
|
|
|
|
ret = amd_core_pmu_init();
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (num_possible_cpus() == 1) {
|
|
/*
|
|
* No point in allocating data structures to serialize
|
|
* against other CPUs, when there is only the one CPU.
|
|
*/
|
|
x86_pmu.amd_nb_constraints = 0;
|
|
}
|
|
|
|
/* Events are common for all AMDs */
|
|
memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
|
|
sizeof(hw_cache_event_ids));
|
|
|
|
return 0;
|
|
}
|
|
|
|
void amd_pmu_enable_virt(void)
|
|
{
|
|
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
|
|
|
|
cpuc->perf_ctr_virt_mask = 0;
|
|
|
|
/* Reload all events */
|
|
x86_pmu_disable_all();
|
|
x86_pmu_enable_all(0);
|
|
}
|
|
EXPORT_SYMBOL_GPL(amd_pmu_enable_virt);
|
|
|
|
void amd_pmu_disable_virt(void)
|
|
{
|
|
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
|
|
|
|
/*
|
|
* We only mask out the Host-only bit so that host-only counting works
|
|
* when SVM is disabled. If someone sets up a guest-only counter when
|
|
* SVM is disabled the Guest-only bits still gets set and the counter
|
|
* will not count anything.
|
|
*/
|
|
cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
|
|
|
|
/* Reload all events */
|
|
x86_pmu_disable_all();
|
|
x86_pmu_enable_all(0);
|
|
}
|
|
EXPORT_SYMBOL_GPL(amd_pmu_disable_virt);
|