393 lines
10 KiB
C
393 lines
10 KiB
C
/*
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* SuperH KGDB support
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*
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* Copyright (C) 2008 - 2012 Paul Mundt
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*
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* Single stepping taken from the old stub by Henry Bell and Jeremy Siegel.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kgdb.h>
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#include <linux/kdebug.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/sched.h>
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#include <linux/sched/task_stack.h>
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#include <asm/cacheflush.h>
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#include <asm/traps.h>
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/* Macros for single step instruction identification */
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#define OPCODE_BT(op) (((op) & 0xff00) == 0x8900)
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#define OPCODE_BF(op) (((op) & 0xff00) == 0x8b00)
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#define OPCODE_BTF_DISP(op) (((op) & 0x80) ? (((op) | 0xffffff80) << 1) : \
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(((op) & 0x7f ) << 1))
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#define OPCODE_BFS(op) (((op) & 0xff00) == 0x8f00)
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#define OPCODE_BTS(op) (((op) & 0xff00) == 0x8d00)
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#define OPCODE_BRA(op) (((op) & 0xf000) == 0xa000)
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#define OPCODE_BRA_DISP(op) (((op) & 0x800) ? (((op) | 0xfffff800) << 1) : \
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(((op) & 0x7ff) << 1))
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#define OPCODE_BRAF(op) (((op) & 0xf0ff) == 0x0023)
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#define OPCODE_BRAF_REG(op) (((op) & 0x0f00) >> 8)
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#define OPCODE_BSR(op) (((op) & 0xf000) == 0xb000)
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#define OPCODE_BSR_DISP(op) (((op) & 0x800) ? (((op) | 0xfffff800) << 1) : \
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(((op) & 0x7ff) << 1))
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#define OPCODE_BSRF(op) (((op) & 0xf0ff) == 0x0003)
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#define OPCODE_BSRF_REG(op) (((op) >> 8) & 0xf)
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#define OPCODE_JMP(op) (((op) & 0xf0ff) == 0x402b)
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#define OPCODE_JMP_REG(op) (((op) >> 8) & 0xf)
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#define OPCODE_JSR(op) (((op) & 0xf0ff) == 0x400b)
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#define OPCODE_JSR_REG(op) (((op) >> 8) & 0xf)
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#define OPCODE_RTS(op) ((op) == 0xb)
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#define OPCODE_RTE(op) ((op) == 0x2b)
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#define SR_T_BIT_MASK 0x1
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#define STEP_OPCODE 0xc33d
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/* Calculate the new address for after a step */
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static short *get_step_address(struct pt_regs *linux_regs)
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{
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insn_size_t op = __raw_readw(linux_regs->pc);
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long addr;
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/* BT */
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if (OPCODE_BT(op)) {
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if (linux_regs->sr & SR_T_BIT_MASK)
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addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op);
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else
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addr = linux_regs->pc + 2;
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}
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/* BTS */
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else if (OPCODE_BTS(op)) {
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if (linux_regs->sr & SR_T_BIT_MASK)
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addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op);
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else
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addr = linux_regs->pc + 4; /* Not in delay slot */
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}
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/* BF */
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else if (OPCODE_BF(op)) {
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if (!(linux_regs->sr & SR_T_BIT_MASK))
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addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op);
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else
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addr = linux_regs->pc + 2;
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}
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/* BFS */
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else if (OPCODE_BFS(op)) {
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if (!(linux_regs->sr & SR_T_BIT_MASK))
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addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op);
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else
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addr = linux_regs->pc + 4; /* Not in delay slot */
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}
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/* BRA */
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else if (OPCODE_BRA(op))
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addr = linux_regs->pc + 4 + OPCODE_BRA_DISP(op);
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/* BRAF */
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else if (OPCODE_BRAF(op))
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addr = linux_regs->pc + 4
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+ linux_regs->regs[OPCODE_BRAF_REG(op)];
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/* BSR */
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else if (OPCODE_BSR(op))
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addr = linux_regs->pc + 4 + OPCODE_BSR_DISP(op);
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/* BSRF */
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else if (OPCODE_BSRF(op))
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addr = linux_regs->pc + 4
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+ linux_regs->regs[OPCODE_BSRF_REG(op)];
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/* JMP */
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else if (OPCODE_JMP(op))
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addr = linux_regs->regs[OPCODE_JMP_REG(op)];
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/* JSR */
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else if (OPCODE_JSR(op))
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addr = linux_regs->regs[OPCODE_JSR_REG(op)];
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/* RTS */
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else if (OPCODE_RTS(op))
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addr = linux_regs->pr;
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/* RTE */
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else if (OPCODE_RTE(op))
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addr = linux_regs->regs[15];
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/* Other */
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else
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addr = linux_regs->pc + instruction_size(op);
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flush_icache_range(addr, addr + instruction_size(op));
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return (short *)addr;
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}
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/*
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* Replace the instruction immediately after the current instruction
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* (i.e. next in the expected flow of control) with a trap instruction,
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* so that returning will cause only a single instruction to be executed.
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* Note that this model is slightly broken for instructions with delay
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* slots (e.g. B[TF]S, BSR, BRA etc), where both the branch and the
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* instruction in the delay slot will be executed.
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*/
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static unsigned long stepped_address;
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static insn_size_t stepped_opcode;
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static void do_single_step(struct pt_regs *linux_regs)
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{
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/* Determine where the target instruction will send us to */
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unsigned short *addr = get_step_address(linux_regs);
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stepped_address = (int)addr;
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/* Replace it */
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stepped_opcode = __raw_readw((long)addr);
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*addr = STEP_OPCODE;
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/* Flush and return */
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flush_icache_range((long)addr, (long)addr +
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instruction_size(stepped_opcode));
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}
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/* Undo a single step */
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static void undo_single_step(struct pt_regs *linux_regs)
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{
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/* If we have stepped, put back the old instruction */
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/* Use stepped_address in case we stopped elsewhere */
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if (stepped_opcode != 0) {
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__raw_writew(stepped_opcode, stepped_address);
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flush_icache_range(stepped_address, stepped_address + 2);
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}
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stepped_opcode = 0;
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}
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struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = {
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{ "r0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[0]) },
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{ "r1", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[1]) },
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{ "r2", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[2]) },
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{ "r3", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[3]) },
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{ "r4", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[4]) },
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{ "r5", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[5]) },
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{ "r6", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[6]) },
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{ "r7", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[7]) },
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{ "r8", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[8]) },
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{ "r9", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[9]) },
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{ "r10", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[10]) },
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{ "r11", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[11]) },
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{ "r12", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[12]) },
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{ "r13", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[13]) },
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{ "r14", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[14]) },
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{ "r15", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[15]) },
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{ "pc", GDB_SIZEOF_REG, offsetof(struct pt_regs, pc) },
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{ "pr", GDB_SIZEOF_REG, offsetof(struct pt_regs, pr) },
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{ "sr", GDB_SIZEOF_REG, offsetof(struct pt_regs, sr) },
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{ "gbr", GDB_SIZEOF_REG, offsetof(struct pt_regs, gbr) },
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{ "mach", GDB_SIZEOF_REG, offsetof(struct pt_regs, mach) },
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{ "macl", GDB_SIZEOF_REG, offsetof(struct pt_regs, macl) },
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{ "vbr", GDB_SIZEOF_REG, -1 },
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};
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int dbg_set_reg(int regno, void *mem, struct pt_regs *regs)
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{
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if (regno < 0 || regno >= DBG_MAX_REG_NUM)
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return -EINVAL;
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if (dbg_reg_def[regno].offset != -1)
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memcpy((void *)regs + dbg_reg_def[regno].offset, mem,
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dbg_reg_def[regno].size);
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return 0;
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}
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char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs)
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{
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if (regno >= DBG_MAX_REG_NUM || regno < 0)
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return NULL;
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if (dbg_reg_def[regno].size != -1)
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memcpy(mem, (void *)regs + dbg_reg_def[regno].offset,
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dbg_reg_def[regno].size);
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switch (regno) {
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case GDB_VBR:
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__asm__ __volatile__ ("stc vbr, %0" : "=r" (mem));
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break;
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}
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return dbg_reg_def[regno].name;
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}
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void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
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{
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struct pt_regs *thread_regs = task_pt_regs(p);
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int reg;
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/* Initialize to zero */
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for (reg = 0; reg < DBG_MAX_REG_NUM; reg++)
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gdb_regs[reg] = 0;
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/*
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* Copy out GP regs 8 to 14.
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*
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* switch_to() relies on SR.RB toggling, so regs 0->7 are banked
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* and need privileged instructions to get to. The r15 value we
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* fetch from the thread info directly.
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*/
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for (reg = GDB_R8; reg < GDB_R15; reg++)
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gdb_regs[reg] = thread_regs->regs[reg];
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gdb_regs[GDB_R15] = p->thread.sp;
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gdb_regs[GDB_PC] = p->thread.pc;
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/*
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* Additional registers we have context for
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*/
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gdb_regs[GDB_PR] = thread_regs->pr;
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gdb_regs[GDB_GBR] = thread_regs->gbr;
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}
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int kgdb_arch_handle_exception(int e_vector, int signo, int err_code,
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char *remcomInBuffer, char *remcomOutBuffer,
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struct pt_regs *linux_regs)
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{
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unsigned long addr;
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char *ptr;
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/* Undo any stepping we may have done */
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undo_single_step(linux_regs);
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switch (remcomInBuffer[0]) {
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case 'c':
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case 's':
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/* try to read optional parameter, pc unchanged if no parm */
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ptr = &remcomInBuffer[1];
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if (kgdb_hex2long(&ptr, &addr))
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linux_regs->pc = addr;
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case 'D':
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case 'k':
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atomic_set(&kgdb_cpu_doing_single_step, -1);
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if (remcomInBuffer[0] == 's') {
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do_single_step(linux_regs);
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kgdb_single_step = 1;
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atomic_set(&kgdb_cpu_doing_single_step,
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raw_smp_processor_id());
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}
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return 0;
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}
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/* this means that we do not want to exit from the handler: */
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return -1;
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}
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unsigned long kgdb_arch_pc(int exception, struct pt_regs *regs)
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{
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if (exception == 60)
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return instruction_pointer(regs) - 2;
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return instruction_pointer(regs);
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}
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void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
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{
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regs->pc = ip;
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}
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/*
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* The primary entry points for the kgdb debug trap table entries.
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*/
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BUILD_TRAP_HANDLER(singlestep)
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{
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unsigned long flags;
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TRAP_HANDLER_DECL;
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local_irq_save(flags);
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regs->pc -= instruction_size(__raw_readw(regs->pc - 4));
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kgdb_handle_exception(0, SIGTRAP, 0, regs);
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local_irq_restore(flags);
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}
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static void kgdb_call_nmi_hook(void *ignored)
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{
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kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
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}
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void kgdb_roundup_cpus(unsigned long flags)
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{
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local_irq_enable();
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smp_call_function(kgdb_call_nmi_hook, NULL, 0);
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local_irq_disable();
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}
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static int __kgdb_notify(struct die_args *args, unsigned long cmd)
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{
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int ret;
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switch (cmd) {
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case DIE_BREAKPOINT:
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/*
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* This means a user thread is single stepping
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* a system call which should be ignored
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*/
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if (test_thread_flag(TIF_SINGLESTEP))
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return NOTIFY_DONE;
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ret = kgdb_handle_exception(args->trapnr & 0xff, args->signr,
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args->err, args->regs);
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if (ret)
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return NOTIFY_DONE;
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break;
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}
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return NOTIFY_STOP;
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}
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static int
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kgdb_notify(struct notifier_block *self, unsigned long cmd, void *ptr)
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{
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unsigned long flags;
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int ret;
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local_irq_save(flags);
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ret = __kgdb_notify(ptr, cmd);
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local_irq_restore(flags);
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return ret;
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}
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static struct notifier_block kgdb_notifier = {
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.notifier_call = kgdb_notify,
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/*
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* Lowest-prio notifier priority, we want to be notified last:
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*/
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.priority = -INT_MAX,
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};
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int kgdb_arch_init(void)
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{
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return register_die_notifier(&kgdb_notifier);
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}
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void kgdb_arch_exit(void)
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{
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unregister_die_notifier(&kgdb_notifier);
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}
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struct kgdb_arch arch_kgdb_ops = {
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/* Breakpoint instruction: trapa #0x3c */
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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.gdb_bpt_instr = { 0x3c, 0xc3 },
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#else
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.gdb_bpt_instr = { 0xc3, 0x3c },
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#endif
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};
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